platform: msm_shared: Update clock & usb phy driver
clock driver: Add timeout for branch block enable
Phy driver: Get the phy settings from target code, update phy status
register for mdmcalifornium and add phy lock timeout
Change-Id: Ib9516327638eeb9d8fd1ef31bd11d87ba6e6d50b
diff --git a/platform/msm_shared/clock_lib2.c b/platform/msm_shared/clock_lib2.c
index ad088cb..50042f2 100644
--- a/platform/msm_shared/clock_lib2.c
+++ b/platform/msm_shared/clock_lib2.c
@@ -32,7 +32,7 @@
#include <clock.h>
#include <clock_pll.h>
#include <clock_lib2.h>
-
+#include <platform/timer.h>
/*=============== CXO clock ops =============*/
int cxo_clk_enable(struct clk *clk)
@@ -55,14 +55,32 @@
{
int rc = 0;
uint32_t cbcr_val;
+ int retry = 100;
struct branch_clk *bclk = to_branch_clk(clk);
cbcr_val = readl(bclk->cbcr_reg);
cbcr_val |= CBCR_BRANCH_ENABLE_BIT;
writel(cbcr_val, bclk->cbcr_reg);
+ /* Some clocks do not need to check the enable status, return
+ * if the halt_check is not set
+ */
+ if (!bclk->halt_check)
+ return rc;
+
/* wait until status shows it is enabled */
- while(readl(bclk->cbcr_reg) & CBCR_BRANCH_OFF_BIT);
+ while(readl(bclk->cbcr_reg) & CBCR_BRANCH_OFF_BIT)
+ {
+ /* Add 100 ms of time out, bail out if the clock is not enable
+ * within 100 ms */
+ if (!retry)
+ {
+ rc = 1;
+ break;
+ }
+ retry--;
+ mdelay(1);
+ }
return rc;
}