diff --git a/platform/msm_shared/mipi_dsi_autopll.c b/platform/msm_shared/mipi_dsi_autopll.c
index d21e8d7..0dfcdc1 100755
--- a/platform/msm_shared/mipi_dsi_autopll.c
+++ b/platform/msm_shared/mipi_dsi_autopll.c
@@ -105,7 +105,7 @@
 
 	writel(0x2b, ctl_base + 0x0278); /* Cal CFG3 */
 	writel(0x66, ctl_base + 0x027c); /* Cal CFG4 */
-	writel(0x05, ctl_base + 0x0264); /* LKDetect CFG2 */
+	writel(0x0d, ctl_base + 0x0264); /* LKDetect CFG2 */
 
 	rem = pd->vco_clock % VCO_REF_CLOCK_RATE;
 	if (rem) {
@@ -149,11 +149,6 @@
 	cal_cfg11 = gen_vco_clk / 256000000;
 	cal_cfg10 = (gen_vco_clk % 256000000) / 1000000;
 
-	writel(0x02, ctl_base + 0x0208); /* PUMP CFG */
-	writel(0x2b, ctl_base + 0x0278); /* CAL CFG3 */
-	writel(0x66, ctl_base + 0x027c); /* CAL CFG4 */
-	writel(0x0d, ctl_base + 0x0264); /* LKDetect CFG2 */
-
 	writel(sdm_cfg1 & 0xff , ctl_base + 0x023c); /* SDM CFG1 */
 	writel(sdm_cfg2 & 0xff , ctl_base + 0x0240); /* SDM CFG2 */
 	writel(sdm_cfg3 & 0xff, ctl_base + 0x0244); /* SDM CFG3 */
diff --git a/target/msm8226/target_display.c b/target/msm8226/target_display.c
index a176b58..06ce3cf 100755
--- a/target/msm8226/target_display.c
+++ b/target/msm8226/target_display.c
@@ -46,6 +46,7 @@
 
 #define HFPLL_LDO_ID 8
 #define MAX_M_SEQ_COUNTER 7
+#define DSI_PLL_POLL_MAX_READS 10
 
 static struct pm8x41_wled_data wled_ctrl = {
 	.mod_scheme      = 0x00,
@@ -56,6 +57,20 @@
 	.fdbck = 0x1
 };
 
+static int mdss_dsi_pll_lock_status(uint32_t ctl_base)
+{
+	int pll_locked = 0, i = 0;
+
+	while (i < DSI_PLL_POLL_MAX_READS) {
+		pll_locked = (readl(ctl_base + 0x02c0) & 0x01);
+		if (pll_locked)
+			break;
+		udelay(50);
+		i++;
+	}
+	return pll_locked;
+}
+
 static uint32_t dsi_pll_enable_seq_m(uint32_t ctl_base)
 {
 	uint32_t i = 0;
@@ -77,7 +92,7 @@
 	udelay(600);
 
 	mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
-	pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+	pll_locked = mdss_dsi_pll_lock_status(ctl_base);
 	for (i = 0; (i < MAX_M_SEQ_COUNTER) && !pll_locked; i++) {
 		writel(0x00, ctl_base + 0x0214); /* PWRGEN CFG */
 		udelay(50);
@@ -86,7 +101,7 @@
 		writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
 		udelay(600);
 		mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
-		pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+		pll_locked = mdss_dsi_pll_lock_status(ctl_base);
 	}
 
 	return pll_locked;
@@ -119,7 +134,7 @@
 	udelay(600);
 
 	mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
-	pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+	pll_locked = mdss_dsi_pll_lock_status(ctl_base);
 
 	return pll_locked;
 }
@@ -149,7 +164,7 @@
 	udelay(600);
 
 	mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
-	pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+	pll_locked = mdss_dsi_pll_lock_status(ctl_base);
 
 	return pll_locked;
 }
@@ -175,7 +190,7 @@
 	udelay(600);
 
 	mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
-	pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+	pll_locked = mdss_dsi_pll_lock_status(ctl_base);
 
 	return pll_locked;
 }
@@ -203,7 +218,7 @@
 	udelay(600);
 
 	mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
-	pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+	pll_locked = mdss_dsi_pll_lock_status(ctl_base);
 
 	return pll_locked;
 }