platform: msm8992: Update sdcc1 freq table
Add support for 172 and 344 MHZ frequency for sdcc1 using
gpll4
Change-Id: Ib34b26cd28073387ad7df0c22b04c287a71cd112
diff --git a/platform/msm8994/acpuclock.c b/platform/msm8994/acpuclock.c
index 6b77ea0..c59e61a 100644
--- a/platform/msm8994/acpuclock.c
+++ b/platform/msm8994/acpuclock.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -37,6 +37,7 @@
#include <platform/timer.h>
#include <rpm-smd.h>
#include <regulator.h>
+#include <platform.h>
#define RPM_CE_CLK_TYPE 0x6563
#define CE2_CLK_ID 0x1
@@ -161,7 +162,10 @@
}
else if(freq == MMC_CLK_192MHZ)
{
- ret = clk_get_set_enable(clk_name, 192000000, 1);
+ if (platform_is_msm8992())
+ ret = clk_get_set_enable(clk_name, 172000000, 1);
+ else
+ ret = clk_get_set_enable(clk_name, 192000000, 1);
}
else if(freq == MMC_CLK_200MHZ)
{
@@ -169,7 +173,10 @@
}
else if(freq == MMC_CLK_400MHZ)
{
- ret = clk_get_set_enable(clk_name, 384000000, 1);
+ if (platform_is_msm8992())
+ ret = clk_get_set_enable(clk_name, 344000000, 1);
+ else
+ ret = clk_get_set_enable(clk_name, 384000000, 1);
}
else
{
diff --git a/platform/msm8994/msm8994-clock.c b/platform/msm8994/msm8994-clock.c
index 358db25..8653f8d 100644
--- a/platform/msm8994/msm8994-clock.c
+++ b/platform/msm8994/msm8994-clock.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -34,6 +34,7 @@
#include <clock_lib2.h>
#include <platform/clock.h>
#include <platform/iomap.h>
+#include <platform.h>
/* Mux source select values */
@@ -256,6 +257,19 @@
F_END
};
+static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk_8992[] =
+{
+ F( 144000, cxo, 16, 3, 25),
+ F( 400000, cxo, 12, 1, 4),
+ F( 20000000, gpll0, 15, 1, 2),
+ F( 25000000, gpll0, 12, 1, 2),
+ F( 50000000, gpll0, 12, 0, 0),
+ F( 96000000, gpll4, 6, 0, 0),
+ F(172000000, gpll4, 2, 0, 0),
+ F(344000000, gpll4, 1, 0, 0),
+ F_END
+};
+
static struct clk_freq_tbl ftbl_gcc_sdcc2_4_apps_clk[] =
{
F( 144000, cxo, 16, 3, 25),
@@ -825,7 +839,16 @@
CLK_LOOKUP("edp_aux_clk", mdss_edpaux_clk.c),
};
+void msm8992_sdc1_clock_override()
+{
+ sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_8992;
+}
+
void platform_clock_init(void)
{
+ if (platform_is_msm8992())
+ {
+ msm8992_sdc1_clock_override();
+ }
clk_init(msm_8994_clocks, ARRAY_SIZE(msm_8994_clocks));
}