mdm9615: Fix bug which turns off hardware gating for usb_hs1_pclk
LK was inadvertently overwriting the settings for the clock
control register usb_hs1_pclk when it does a write to enable
the clock.
Changing this behavior to read-modify-write leaves the
SBL settings intact.
diff --git a/platform/mdm9x15/acpuclock.c b/platform/mdm9x15/acpuclock.c
index d29055b..6096731 100644
--- a/platform/mdm9x15/acpuclock.c
+++ b/platform/mdm9x15/acpuclock.c
@@ -95,6 +95,8 @@
void hsusb_clock_init(void)
{
+ uint32_t reg;
+
pll8_enable();
/* Setup USB HS1 System clock - 60 Mhz */
@@ -113,7 +115,9 @@
USB_HS1_XCVR_FS_CLK_MD);
/* HS-USB: enable cc_usb_hs1_hs_clk */
- writel( 0x1 << 4, USB_HS1_HCLK_CTL);
+ reg = readl(USB_HS1_HCLK_CTL);
+ reg |= 0x1 << 4;
+ writel( reg, USB_HS1_HCLK_CTL);
}
/* Configure UART clock - based on the gsbi id */