commit 13ff40277a865653083b4d830ca664e976adbdae
author bait_dispatcher_monitor_system <bait_dispatcher_monitor_system@localhost> Fri Feb 20 04:44:32 2015 -0800
committer Gerrit - the friendly Code Review server <code-review@localhost> Fri Feb 20 04:44:32 2015 -0800
tree c30eb2f1e91970c257dcc24002bcde098e6b1100
parent d71cb2926ce661b8a861311adda035b0bcd2c11a
parent 8da5e5d9c4a49b5ca3ecaa3a731c3173e7a5d357

Merge "platform: msm_shared: add support to keep clock lane in HS"

platform/msm_shared/mipi_dsi.c

diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 3481e54..b18a508 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -380,6 +380,14 @@
 			lane_swap_dsi1 = lane_swap;
 		writel(lane_swap_dsi1, mipi->sctl_base + LANE_SWAP_CTL);
 		writel(timing_ctl, mipi->sctl_base + TIMING_CTL);
+
+		if (mipi->force_clk_lane_hs) {
+			uint32_t tmp;
+
+			tmp = readl(mipi->sctl_base + LANE_CTL);
+			tmp |= BIT(28);
+			writel(tmp, mipi->sctl_base + LANE_CTL);
+		}
 	}
 
 	writel(0x0001, mipi->ctl_base + SOFT_RESET);
@@ -396,6 +404,14 @@
 
 	writel(lane_swap, mipi->ctl_base + LANE_SWAP_CTL);
 	writel(timing_ctl, mipi->ctl_base + TIMING_CTL);
+
+	if (mipi->force_clk_lane_hs) {
+		uint32_t tmp;
+
+		tmp = readl(mipi->ctl_base + LANE_CTL);
+		tmp |= BIT(28);
+		writel(tmp, mipi->ctl_base + LANE_CTL);
+	}
 #endif
 
 	return 0;