platform: msm8974: Clock support for hs400
Add support for gpll4, sdc_ff & sdc_sleep clocks.
Also update sdc1 frquency table to run sdc1 core clock
at 400 MHZ
CRs-Fixed: 501718
Change-Id: I7c08a4f65c7850f23c0184342875a4bf035e6d5e
diff --git a/platform/msm8974/acpuclock.c b/platform/msm8974/acpuclock.c
index e66208c..da1b024 100644
--- a/platform/msm8974/acpuclock.c
+++ b/platform/msm8974/acpuclock.c
@@ -128,6 +128,10 @@
{
ret = clk_get_set_enable(clk_name, 400000, 1);
}
+ else if(freq == MMC_CLK_25MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 25000000, 1);
+ }
else if(freq == MMC_CLK_50MHZ)
{
ret = clk_get_set_enable(clk_name, 50000000, 1);
@@ -136,10 +140,18 @@
{
ret = clk_get_set_enable(clk_name, 100000000, 1);
}
+ else if(freq == MMC_CLK_192MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 192000000, 1);
+ }
else if(freq == MMC_CLK_200MHZ)
{
ret = clk_get_set_enable(clk_name, 200000000, 1);
}
+ else if(freq == MMC_CLK_400MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 384000000, 1);
+ }
else
{
dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
@@ -159,6 +171,29 @@
#endif
}
+/* Configure clocks needed for CDCLP533 circuit */
+void clock_config_cdc(uint32_t interface)
+{
+ int ret = 0;
+ char clk_name[64];
+
+ snprintf(clk_name, sizeof(clk_name), "gcc_sdcc%u_cdccal_sleep_clk", interface);
+ ret = clk_get_set_enable(clk_name, 0 , 1);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to enable clock: %s\n", clk_name);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "gcc_sdcc%u_cdccal_ff_clk", interface);
+ ret = clk_get_set_enable(clk_name, 0 , 1);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to enable clock: %s\n", clk_name);
+ ASSERT(0);
+ }
+}
+
/* Configure UART clock based on the UART block id*/
void clock_config_uart_dm(uint8_t id)
{