display: Correctly setting up mdss interface offsets
Mdss interface offsets have changed between 8974 V1 and
V2.
Change-Id: I551ffaafd6e8884800e0aaac2caf9f00011f7e8a
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index 497b4d0..357663e 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -54,6 +54,11 @@
#define MDP_VP_0_LAYER_3_BLEND_OP REG_MDP(0x32B0)
#define MDP_VP_0_LAYER_3_BLEND0_FG_ALPHA REG_MDP(0x32B4)
+
+#define MDSS_MDP_HW_REV_100 0x10000000
+#define MDSS_MDP_HW_REV_102 0x10020000
+
+#define MDP_HW_REV REG_MDP(0x0100)
#define MDP_INTR_EN REG_MDP(0x0110)
#define MDP_INTR_CLEAR REG_MDP(0x0118)
#define MDP_HIST_INTR_EN REG_MDP(0x011C)
@@ -63,29 +68,29 @@
#define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x02EC)
#define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x04F8)
-#define MDP_INTF_1_TIMING_ENGINE_EN REG_MDP(0x21300)
+#define MDP_INTF_1_TIMING_ENGINE_EN REG_MDP(0x12700)
#define MDP_CTL_0_LAYER_0 REG_MDP(0x600)
#define MDP_CTL_0_TOP REG_MDP(0x614)
#define MDP_CTL_0_FLUSH REG_MDP(0x618)
-#define MDP_INTF_1_HSYNC_CTL REG_MDP(0x21308)
-#define MDP_INTF_1_VSYNC_PERIOD_F0 REG_MDP(0x2130C)
-#define MDP_INTF_1_VSYNC_PERIOD_F1 REG_MDP(0x21310)
-#define MDP_INTF_1_VSYNC_PULSE_WIDTH_F0 REG_MDP(0x21314)
-#define MDP_INTF_1_VSYNC_PULSE_WIDTH_F1 REG_MDP(0x21318)
-#define MDP_INTF_1_DISPLAY_HCTL REG_MDP(0x2133C)
-#define MDP_INTF_1_DISPLAY_V_START_F0 REG_MDP(0x2131C)
-#define MDP_INTF_1_DISPLAY_V_START_F1 REG_MDP(0x21320)
-#define MDP_INTF_1_DISPLAY_V_END_F0 REG_MDP(0x21324)
-#define MDP_INTF_1_DISPLAY_V_END_F1 REG_MDP(0x21328)
-#define MDP_INTF_1_ACTIVE_HCTL REG_MDP(0x21340)
-#define MDP_INTF_1_ACTIVE_V_START_F0 REG_MDP(0x2132C)
-#define MDP_INTF_1_ACTIVE_V_START_F1 REG_MDP(0x21330)
-#define MDP_INTF_1_ACTIVE_V_END_F0 REG_MDP(0x21334)
-#define MDP_INTF_1_ACTIVE_V_END_F1 REG_MDP(0x21338)
-#define MDP_INTF_1_UNDERFFLOW_COLOR REG_MDP(0x21348)
-#define MDP_INTF_1_PANEL_FORMAT REG_MDP(0x21390)
+#define MDP_INTF_1_HSYNC_CTL REG_MDP(0x12708)
+#define MDP_INTF_1_VSYNC_PERIOD_F0 REG_MDP(0x1270C)
+#define MDP_INTF_1_VSYNC_PERIOD_F1 REG_MDP(0x12710)
+#define MDP_INTF_1_VSYNC_PULSE_WIDTH_F0 REG_MDP(0x12714)
+#define MDP_INTF_1_VSYNC_PULSE_WIDTH_F1 REG_MDP(0x12718)
+#define MDP_INTF_1_DISPLAY_HCTL REG_MDP(0x1273C)
+#define MDP_INTF_1_DISPLAY_V_START_F0 REG_MDP(0x1271C)
+#define MDP_INTF_1_DISPLAY_V_START_F1 REG_MDP(0x12720)
+#define MDP_INTF_1_DISPLAY_V_END_F0 REG_MDP(0x12724)
+#define MDP_INTF_1_DISPLAY_V_END_F1 REG_MDP(0x12728)
+#define MDP_INTF_1_ACTIVE_HCTL REG_MDP(0x12740)
+#define MDP_INTF_1_ACTIVE_V_START_F0 REG_MDP(0x1272C)
+#define MDP_INTF_1_ACTIVE_V_START_F1 REG_MDP(0x12730)
+#define MDP_INTF_1_ACTIVE_V_END_F0 REG_MDP(0x12734)
+#define MDP_INTF_1_ACTIVE_V_END_F1 REG_MDP(0x12738)
+#define MDP_INTF_1_UNDERFFLOW_COLOR REG_MDP(0x12748)
+#define MDP_INTF_1_PANEL_FORMAT REG_MDP(0x12790)
#define MDP_CLK_CTRL0 REG_MDP(0x03AC)
#define MDP_CLK_CTRL1 REG_MDP(0x03B4)