diff --git a/dev/gcdb/display/fastboot_oem_display.h b/dev/gcdb/display/fastboot_oem_display.h
index 95c9147..a8af486 100644
--- a/dev/gcdb/display/fastboot_oem_display.h
+++ b/dev/gcdb/display/fastboot_oem_display.h
@@ -111,7 +111,10 @@
 	{"sharp_120hz_1080p_cmd", "qcom,mdss_dual_sharp_1080p_120hz_cmd",
 		true},
 	{"mirrorlake1_hdplus_video", "qcom,mdss_dsi_icn9706_720_1440p_video", false},
-	{"hx8399c_truly_video", "qcom,mdss_dsi_hx8399c_truly_video", false},
+	{"hx8399c_fhd_plus_video", "qcom,mdss_dsi_hx8399c_truly_video", false},
+	{"hx8399c_hd_plus_video", "qcom,mdss_dsi_hx8399c_hd_video", false},
+	{"nt35695b_truly_fhd_video", "qcom,mdss_dsi_nt35695b_truly_fhd_video", false},
+	{"nt35695b_truly_fhd_cmd", "qcom,mdss_dsi_nt35695b_truly_fhd_cmd", false},
 };
 
 struct sim_lookup_list lookup_sim[] = {
diff --git a/dev/gcdb/display/gcdb_autopll.c b/dev/gcdb/display/gcdb_autopll.c
index 562ca0b..970270c 100755
--- a/dev/gcdb/display/gcdb_autopll.c
+++ b/dev/gcdb/display/gcdb_autopll.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, 2018, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -389,6 +389,65 @@
 	return NO_ERROR;
 }
 
+static uint32_t calculate_p_div_mux(uint32_t hr_bitclk)
+{
+	uint32_t hr_bitclk_mhz = (hr_bitclk / 1000000);
+
+	if (hr_bitclk_mhz >= 1000 && hr_bitclk_mhz <= 1250)
+		return 0x0;
+	else if (hr_bitclk_mhz >= 500 && hr_bitclk_mhz < 1000)
+		return 0x1;
+	else if (hr_bitclk_mhz >= 250 && hr_bitclk_mhz < 500)
+		return 0x2;
+	else if (hr_bitclk_mhz >= 125 && hr_bitclk_mhz < 250)
+		return 0x3;
+	else if (hr_bitclk_mhz >= 63 && hr_bitclk_mhz < 125)
+		return 0x4;
+	else
+		return 0x5;
+}
+
+static void calculate_divhf(uint32_t hr_bitclk, uint8_t bpp,
+	uint8_t lanes)
+{
+	int m = 1;
+	int n = 1;
+	uint32_t dsi_clk = 0;
+
+	if (bpp == BITS_18) {
+		if (lanes == 2) {
+			m = 2;
+			n = 9;
+		} else if (lanes == 4) {
+			m = 4;
+			n = 9;
+		}
+	} else if (bpp == BITS_16) {
+		if (lanes == 3) {
+			m = 3;
+			n = 8;
+		}
+	}
+
+	dsi_clk = (pll_data.pixel_clock * n) / m;
+	pll_data.divhf = ((pll_data.halfbit_clock / dsi_clk) - 1);
+
+	pll_data.pclk_m = m;	/* M */
+	pll_data.pclk_n = ~(n - m);	/* ~(N-M) */
+	pll_data.pclk_d = ~n;	/* ~N  */
+}
+
+static uint32_t calculate_vco_12nm(uint8_t bpp, uint8_t lanes)
+{
+	pll_data.vco_min = MIN_12NM_VCO_RATE;
+	pll_data.vco_max = MAX_12NM_VCO_RATE;
+	pll_data.p_div_mux = calculate_p_div_mux(pll_data.halfbit_clock);
+	pll_data.gp_div_mux = pll_data.p_div_mux;
+	pll_data.vco_clock = pll_data.halfbit_clock * (1 << pll_data.p_div_mux);
+	calculate_divhf(pll_data.halfbit_clock, bpp, lanes);
+	return NO_ERROR;
+}
+
 uint32_t calculate_clock_config(struct msm_panel_info *pinfo)
 {
 	uint32_t ret = NO_ERROR;
@@ -403,6 +462,9 @@
 	case DSI_PLL_TYPE_THULIUM:
 		ret = calculate_vco_thulium(pinfo->bpp, pinfo->mipi.num_of_lanes);
 		break;
+	case DSI_PLL_TYPE_12NM:
+		ret = calculate_vco_12nm(pinfo->bpp, pinfo->mipi.num_of_lanes);
+		break;
 	case DSI_PLL_TYPE_28NM:
 	default:
 		ret = calculate_vco_28nm(pinfo->bpp, pinfo->mipi.num_of_lanes);
diff --git a/dev/gcdb/display/gcdb_autopll.h b/dev/gcdb/display/gcdb_autopll.h
index ddfcf1c..8ee8717 100755
--- a/dev/gcdb/display/gcdb_autopll.h
+++ b/dev/gcdb/display/gcdb_autopll.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, 2018, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -59,6 +59,9 @@
 #define FIX_PIXEL_CLOCK_DIV 2
 #define FIX_N_DIV           1
 
+#define MIN_12NM_VCO_RATE 1000000000
+#define MAX_12NM_VCO_RATE 2000000000
+
 /*---------------------------------------------------------------------------*/
 /* Structure definition                                                      */
 /*---------------------------------------------------------------------------*/
diff --git a/dev/gcdb/display/include/panel_hx8399c_fhd_pluse_video.h b/dev/gcdb/display/include/panel_hx8399c_fhd_pluse_video.h
index 2915fe2..9258672 100644
--- a/dev/gcdb/display/include/panel_hx8399c_fhd_pluse_video.h
+++ b/dev/gcdb/display/include/panel_hx8399c_fhd_pluse_video.h
@@ -295,6 +295,10 @@
 	0x24, 0x1C, 0x34, 0x00, 0x58, 0x4d, 0x36, 0x3f, 0x53, 0x03, 0x04, 0x00
 };
 
+static const uint32_t hx8399c_fhd_pluse_video_12nm_timings[] = {
+	0x18, 0x0A, 0x10, 0x06, 0x03, 0x08, 0x06, 0x0E
+};
+
 static const uint32_t hx8399c_fhd_pluse_14nm_video_timings[] = {
 	0x24, 0x1f, 0x08, 0x09, 0x05, 0x03, 0x04, 0xa0,
 	0x24, 0x1f, 0x08, 0x09, 0x05, 0x03, 0x04, 0xa0,
@@ -321,7 +325,7 @@
 /* Backlight setting                                                         */
 /*---------------------------------------------------------------------------*/
 static struct backlight hx8399c_fhd_pluse_video_backlight = {
-	1, 1, 4095, 100, 1, "PMIC_8941"
+	0, 1, 4095, 100, 1, "PMIC_8941"
 };
 
 #define HX8399C_FHD_PLUSE_VIDEO_SIGNATURE 0xA0000
diff --git a/dev/gcdb/display/include/panel_hx8399c_hd_plus_video.h b/dev/gcdb/display/include/panel_hx8399c_hd_plus_video.h
new file mode 100644
index 0000000..fdb7f7d
--- /dev/null
+++ b/dev/gcdb/display/include/panel_hx8399c_hd_plus_video.h
@@ -0,0 +1,353 @@
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  * Neither the name of The Linux Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PANEL_HX8399C_HD_PLUS_VIDEO_H_
+
+#define _PANEL_HX8399C_HD_PLUS_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files                                                              */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration                                                       */
+/*---------------------------------------------------------------------------*/
+static struct panel_config hx8399c_hd_plus_video_panel_data = {
+	"qcom,mdss_dsi_hx8399c_hd_video", "dsi:0:", "qcom,mdss-dsi-panel",
+	10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, NULL
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution                                                          */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution hx8399c_hd_plus_video_panel_res = {
+	720, 1440, 24, 24, 16, 0, 36, 40, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information                                                   */
+/*---------------------------------------------------------------------------*/
+static struct color_info hx8399c_hd_plus_video_color = {
+	24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information                                          */
+/*---------------------------------------------------------------------------*/
+static char hx8399c_hd_plus_video_on_cmd0[] = {
+	0x04, 0x00, 0x39, 0xC0,
+	0xB9, 0xFF, 0x83, 0x99,
+};
+
+static char hx8399c_hd_plus_video_on_cmd1[] = {
+	0x02, 0x00, 0x39, 0xC0,
+	0xD2, 0x88, 0xFF, 0xFF,
+};
+
+static char hx8399c_hd_plus_video_on_cmd2[] = {
+	0x10, 0x00, 0x39, 0xC0,
+	0xB1, 0x02, 0x04, 0x74,
+	0x94, 0x01, 0x32, 0x33,
+	0x11, 0x11, 0xE6, 0x5D,
+	0x56, 0x73, 0x02, 0x02,
+};
+
+static char hx8399c_hd_plus_video_on_cmd3[] = {
+	0x10, 0x00, 0x39, 0xC0,
+	0xB2, 0x00, 0x80, 0x80,
+	0xCC, 0x05, 0x07, 0x5A,
+	0x11, 0x10, 0x10, 0x00,
+	0x1E, 0x70, 0x03, 0xD4,
+};
+
+static char hx8399c_hd_plus_video_on_cmd4[] = {
+	0x2D, 0x00, 0x39, 0xC0,
+	0xB4, 0x00, 0xFF, 0x59,
+	0x59, 0x0C, 0xAC, 0x00,
+	0x00, 0x0C, 0x00, 0x07,
+	0x0A, 0x00, 0x28, 0x07,
+	0x08, 0x0C, 0x21, 0x03,
+	0x00, 0x00, 0x00, 0xAE,
+	0x87, 0x59, 0x59, 0x0C,
+	0xAC, 0x00, 0x00, 0x0C,
+	0x00, 0x07, 0x0A, 0x00,
+	0x28, 0x07, 0x08, 0x0C,
+	0x01, 0x00, 0x00, 0xAE,
+	0x01, 0xFF, 0xFF, 0xFF,
+};
+
+static char hx8399c_hd_plus_video_on_cmd5[] = {
+	0x22, 0x00, 0x39, 0xC0,
+	0xD3, 0x00, 0x00, 0x01,
+	0x01, 0x00, 0x00, 0x10,
+	0x10, 0x00, 0x00, 0x03,
+	0x00, 0x03, 0x00, 0x08,
+	0x78, 0x08, 0x78, 0x00,
+	0x00, 0x00, 0x00, 0x00,
+	0x24, 0x02, 0x05, 0x05,
+	0x03, 0x00, 0x00, 0x00,
+	0x05, 0x40, 0xFF, 0xFF,
+};
+
+static char hx8399c_hd_plus_video_on_cmd6[] = {
+	0x21, 0x00, 0x39, 0xC0,
+	0xD5, 0x20, 0x20, 0x19,
+	0x19, 0x18, 0x18, 0x02,
+	0x03, 0x00, 0x01, 0x24,
+	0x24, 0x18, 0x18, 0x18,
+	0x18, 0x24, 0x24, 0x00,
+	0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x2F,
+	0x2F, 0x30, 0x30, 0x31,
+	0x31, 0xFF, 0xFF, 0xFF,
+};
+
+static char hx8399c_hd_plus_video_on_cmd7[] = {
+	0x21, 0x00, 0x39, 0xC0,
+	0xD6, 0x24, 0x24, 0x18,
+	0x18, 0x19, 0x19, 0x01,
+	0x00, 0x03, 0x02, 0x24,
+	0x24, 0x18, 0x18, 0x18,
+	0x18, 0x20, 0x20, 0x40,
+	0x40, 0x40, 0x40, 0x40,
+	0x40, 0x40, 0x40, 0x2F,
+	0x2F, 0x30, 0x30, 0x31,
+	0x31, 0xFF, 0xFF, 0xFF,
+};
+
+static char hx8399c_hd_plus_video_on_cmd8[] = {
+	0x02, 0x00, 0x39, 0xC0,
+	0xBD, 0x00, 0xFF, 0xFF,
+};
+
+static char hx8399c_hd_plus_video_on_cmd9[] = {
+	0x11, 0x00, 0x39, 0xC0,
+	0xD8, 0xAA, 0xAA, 0xAA,
+	0xAA, 0xAA, 0xAA, 0xAA,
+	0xAA, 0xAA, 0xBA, 0xAA,
+	0xAA, 0xAA, 0xBA, 0xAA,
+	0xAA, 0xFF, 0xFF, 0xFF,
+};
+
+static char hx8399c_hd_plus_video_on_cmd10[] = {
+	0x02, 0x00, 0x39, 0xC0,
+	0xBD, 0x01, 0xFF, 0xFF,
+};
+
+static char hx8399c_hd_plus_video_on_cmd11[] = {
+	0x11, 0x00, 0x39, 0xC0,
+	0xD8, 0x82, 0xEA, 0xAA,
+	0xAA, 0x82, 0xEA, 0xAA,
+	0xAA, 0x82, 0xEA, 0xAA,
+	0xAA, 0x82, 0xEA, 0xAA,
+	0xAA, 0xFF, 0xFF, 0xFF,
+};
+
+static char hx8399c_hd_plus_video_on_cmd12[] = {
+	0x02, 0x00, 0x39, 0xC0,
+	0xBD, 0x02, 0xFF, 0xFF,
+};
+
+static char hx8399c_hd_plus_video_on_cmd13[] = {
+	0x09, 0x00, 0x39, 0xC0,
+	0xD8, 0xFF, 0xFF, 0xC0,
+	0x3F, 0xFF, 0xFF, 0xC0,
+	0x3F, 0xFF, 0xFF, 0xFF,
+};
+
+static char hx8399c_hd_plus_video_on_cmd14[] = {
+	0x02, 0x00, 0x39, 0xC0,
+	0xBD, 0x00, 0xFF, 0xFF,
+};
+
+static char hx8399c_hd_plus_video_on_cmd15[] = {
+	0x02, 0x00, 0x39, 0xC0,
+	0xDD, 0x03, 0xFF, 0xFF,
+};
+
+static char hx8399c_hd_plus_video_on_cmd16[] = {
+	0x37, 0x00, 0x39, 0xC0,
+	0xE0, 0x08, 0x2A, 0x39,
+	0x35, 0x74, 0x7C, 0x87,
+	0x7F, 0x84, 0x8A, 0x8E,
+	0x91, 0x93, 0x96, 0x9B,
+	0x9C, 0x9E, 0xA5, 0xA6,
+	0xAE, 0xA1, 0xAF, 0xB2,
+	0x5C, 0x58, 0x63, 0x74,
+	0x08, 0x2A, 0x39, 0x35,
+	0x74, 0x7C, 0x87, 0x7F,
+	0x84, 0x8A, 0x8E, 0x91,
+	0x93, 0x96, 0x9B, 0x9C,
+	0x9E, 0xA5, 0xA6, 0xAE,
+	0xA1, 0xAF, 0xB2, 0x5C,
+	0x58, 0x63, 0x74, 0xFF,
+};
+
+static char hx8399c_hd_plus_video_on_cmd17[] = {
+	0x03, 0x00, 0x39, 0xC0,
+	0xB6, 0x7E, 0x7E, 0xFF,
+};
+
+static char hx8399c_hd_plus_video_on_cmd18[] = {
+	0x02, 0x00, 0x39, 0xC0,
+	0xCC, 0x08, 0xFF, 0xFF,
+};
+
+static char hx8399c_hd_plus_video_on_cmd19[] = {
+	0x06, 0x00, 0x39, 0xC0,
+	0xC7, 0x00, 0x08, 0x00,
+	0x01, 0x08, 0xFF, 0xFF,
+};
+
+static char hx8399c_hd_plus_video_on_cmd20[] = {
+	0x02, 0x00, 0x39, 0xC0,
+	0XC0, 0x25, 0x5A, 0xFF,
+};
+
+static char hx8399c_hd_plus_video_on_cmd21[] = {
+	0x11, 0x00, 0x05, 0x80,
+};
+
+static char hx8399c_hd_plus_video_on_cmd22[] = {
+	0x29, 0x00, 0x05, 0x80,
+};
+
+static struct mipi_dsi_cmd hx8399c_hd_plus_video_on_command[] = {
+	{0x08, hx8399c_hd_plus_video_on_cmd0, 0x00},
+	{0x08, hx8399c_hd_plus_video_on_cmd1, 0x00},
+	{0x14, hx8399c_hd_plus_video_on_cmd2, 0x00},
+	{0x14, hx8399c_hd_plus_video_on_cmd3, 0x00},
+	{0x34, hx8399c_hd_plus_video_on_cmd4, 0x00},
+	{0x28, hx8399c_hd_plus_video_on_cmd5, 0x05},
+	{0x28, hx8399c_hd_plus_video_on_cmd6, 0x05},
+	{0x28, hx8399c_hd_plus_video_on_cmd7, 0x05},
+	{0x08, hx8399c_hd_plus_video_on_cmd8, 0x00},
+	{0x18, hx8399c_hd_plus_video_on_cmd9, 0x00},
+	{0x08, hx8399c_hd_plus_video_on_cmd10, 0x00},
+	{0x18, hx8399c_hd_plus_video_on_cmd11, 0x00},
+	{0x08, hx8399c_hd_plus_video_on_cmd12, 0x00},
+	{0x10, hx8399c_hd_plus_video_on_cmd13, 0x00},
+	{0x08, hx8399c_hd_plus_video_on_cmd14, 0x00},
+	{0x08, hx8399c_hd_plus_video_on_cmd15, 0x00},
+	{0x3C, hx8399c_hd_plus_video_on_cmd16, 0x05},
+	{0x08, hx8399c_hd_plus_video_on_cmd17, 0x00},
+	{0x08, hx8399c_hd_plus_video_on_cmd18, 0x00},
+	{0x0C, hx8399c_hd_plus_video_on_cmd19, 0x00},
+	{0x08, hx8399c_hd_plus_video_on_cmd20, 0x00},
+	{0x04, hx8399c_hd_plus_video_on_cmd21, 0x78},
+	{0x04, hx8399c_hd_plus_video_on_cmd22, 0x14}
+};
+
+#define HX8399C_HD_PLUS_VIDEO_ON_COMMAND 23
+
+
+static char hx8399c_hd_plus_videooff_cmd0[] = {
+	0x28, 0x00, 0x05, 0x80
+};
+
+static char hx8399c_hd_plus_videooff_cmd1[] = {
+	0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd hx8399c_hd_plus_video_off_command[] = {
+	{0x4, hx8399c_hd_plus_videooff_cmd0, 0x14},
+	{0x4, hx8399c_hd_plus_videooff_cmd1, 0x78}
+};
+
+#define HX8399C_HD_PLUS_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state hx8399c_hd_plus_video_state = {
+	0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information                                            */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info hx8399c_hd_plus_video_command_panel = {
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information                                              */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info hx8399c_hd_plus_video_video_panel = {
+	0, 0, 0, 0, 1, 1, 1, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration                                                        */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration hx8399c_hd_plus_video_lane_config = {
+	4, 0, 1, 1, 1, 1, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing                                                              */
+/*---------------------------------------------------------------------------*/
+static const uint32_t hx8399c_hd_plus_video_timings[] = {
+	0x7E, 0x48, 0x3C, 0x00, 0x64, 0x59, 0x3B, 0x4A, 0x2E, 0x03, 0x04, 0x00
+};
+
+static const uint32_t hx8399c_hd_plus_video_12nm_timings[] = {
+	0x08, 0x06, 0x0A, 0x02, 0x00, 0x04, 0x02, 0x08
+};
+
+static const uint32_t hx8399c_hd_plus_14nm_video_timings[] = {
+	0x24, 0x1f, 0x08, 0x09, 0x05, 0x03, 0x04, 0xa0,
+	0x24, 0x1f, 0x08, 0x09, 0x05, 0x03, 0x04, 0xa0,
+	0x24, 0x1f, 0x08, 0x09, 0x05, 0x03, 0x04, 0xa0,
+	0x24, 0x1f, 0x08, 0x09, 0x05, 0x03, 0x04, 0xa0,
+	0x24, 0x1c, 0x08, 0x09, 0x05, 0x03, 0x04, 0xa0,
+};
+static struct panel_timing hx8399c_hd_plus_video_timing_info = {
+	0, 4, 0x0e, 0x31
+};
+
+static struct labibb_desc hx8399c_hd_plus_video_labibb = {
+	0, 1, 5700000, 5700000, 5700000, 5700000, 3, 3, 1, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence                                                      */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence hx8399c_hd_plus_video_panel_reset_seq = {
+	{1, 0, 1, }, {10, 10, 10, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting                                                         */
+/*---------------------------------------------------------------------------*/
+static struct backlight hx8399c_hd_plus_video_backlight = {
+	0, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+#define HX8399C_HD_PLUS_VIDEO_SIGNATURE 0xFFFF
+
+#endif /*_PANEL_HX8399C_HD_PLUS_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_nt35695b_truly_fhd_cmd.h b/dev/gcdb/display/include/panel_nt35695b_truly_fhd_cmd.h
new file mode 100644
index 0000000..943759d
--- /dev/null
+++ b/dev/gcdb/display/include/panel_nt35695b_truly_fhd_cmd.h
@@ -0,0 +1,769 @@
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  * Neither the name of The Linux Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PANEL_NT35695B_TRULY_FHD_CMD_H_
+
+#define _PANEL_NT35695B_TRULY_FHD_CMD_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files                                                              */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration                                                       */
+/*---------------------------------------------------------------------------*/
+
+static struct panel_config nt35695b_truly_fhd_cmd_panel_data = {
+	"qcom,mdss_dsi_nt35695b_truly_fhd_cmd", "dsi:0:", "qcom,mdss-dsi-panel",
+	11, 1, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution                                                          */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution nt35695b_truly_fhd_cmd_panel_res = {
+	1080, 1920, 120, 60, 12, 0, 12, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information                                                   */
+/*---------------------------------------------------------------------------*/
+static struct color_info nt35695b_truly_fhd_cmd_color = {
+	24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information                                                 */
+/*---------------------------------------------------------------------------*/
+static char nt35695b_truly_fhd_cmd_on_cmd0[] = {
+	0xFF, 0x20, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd1[] = {
+	0XFB, 0x01, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd2[] = {
+	0x00, 0x01, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd3[] = {
+	0x01, 0x55, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd4[] = {
+	0x02, 0x45, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd5[] = {
+	0x03, 0x55, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd6[] = {
+	0x05, 0x50, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd7[] = {
+	0x06, 0xa8, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd8[] = {
+	0x07, 0xAD, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd9[] = {
+	0x08, 0x0C, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd10[] = {
+	0x0B, 0xAA, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd11[] = {
+	0x0C, 0xAA, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd12[] = {
+	0x0E, 0xB0, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd13[] = {
+	0x0F, 0xB3, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd14[] = {
+	0x11, 0x28, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd15[] = {
+	0x12, 0x10, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd16[] = {
+	0x13, 0x01, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd17[] = {
+	0x14, 0x4A, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd18[] = {
+	0x15, 0x12, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd19[] = {
+	0x16, 0x12, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd20[] = {
+	0x30, 0x01, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd21[] = {
+	0x72, 0x11, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd22[] = {
+	0x58, 0x82, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd23[] = {
+	0x59, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd24[] = {
+	0x5A, 0x02, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd25[] = {
+	0x5B, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd26[] = {
+	0x5C, 0x82, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd27[] = {
+	0x5D, 0x80, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd28[] = {
+	0x5E, 0x02, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd29[] = {
+	0x5F, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd30[] = {
+	0xFF, 0x24, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd31[] = {
+	0xFB, 0x01, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd32[] = {
+	0x00, 0x01, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd33[] = {
+	0x01, 0x0B, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd34[] = {
+	0x02, 0x0C, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd35[] = {
+	0x03, 0x89, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd36[] = {
+	0x04, 0x8A, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd37[] = {
+	0x05, 0x0F, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd38[] = {
+	0x06, 0x10, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd39[] = {
+	0x07, 0x01, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd40[] = {
+	0x08, 0x1C, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd41[] = {
+	0X09, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd42[] = {
+	0x0A, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd43[] = {
+	0x0B, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd44[] = {
+	0x0C, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd45[] = {
+	0x0D, 0x13, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd46[] = {
+	0x0E, 0x15, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd47[] = {
+	0x0F, 0x17, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd48[] = {
+	0x10, 0x01, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd49[] = {
+	0x11, 0x0B, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd50[] = {
+	0x12, 0x0C, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd51[] = {
+	0X13, 0x89, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd52[] = {
+	0x14, 0x8A, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd53[] = {
+	0x15, 0x0F, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd54[] = {
+	0x16, 0x10, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd55[] = {
+	0x17, 0x10, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd56[] = {
+	0x18, 0x1C, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd57[] = {
+	0x19, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd58[] = {
+	0x1A, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd59[] = {
+	0x1B, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd60[] = {
+	0x1C, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd61[] = {
+	0X1D, 0x13, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd62[] = {
+	0x1E, 0x15, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd63[] = {
+	0x1F, 0x17, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd64[] = {
+	0x20, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd65[] = {
+	0x21, 0x01, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd66[] = {
+	0x22, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd67[] = {
+	0x23, 0x40, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd68[] = {
+	0x24, 0x40, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd69[] = {
+	0x25, 0x6D, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd70[] = {
+	0x26, 0x40, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd71[] = {
+	0X27, 0x40, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd72[] = {
+	0x29, 0xD8, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd73[] = {
+	0x2A, 0x2A, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd74[] = {
+	0x4B, 0x03, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd75[] = {
+	0x4C, 0x11, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd76[] = {
+	0x4D, 0x10, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd77[] = {
+	0x4E, 0x01, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd78[] = {
+	0x4F, 0x01, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd79[] = {
+	0x50, 0x10, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd80[] = {
+	0x51, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd81[] = {
+	0X52, 0x80, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd82[] = {
+	0x53, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd83[] = {
+	0x54, 0x07, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd84[] = {
+	0x55, 0x25, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd85[] = {
+	0x56, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd86[] = {
+	0x58, 0x07, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd87[] = {
+	0x5B, 0x43, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd88[] = {
+	0x5C, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd89[] = {
+	0x5F, 0x73, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd90[] = {
+	0x60, 0x73, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd91[] = {
+	0x63, 0x22, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd92[] = {
+	0x64, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd93[] = {
+	0x67, 0x08, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd94[] = {
+	0x68, 0x04, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd95[] = {
+	0x7A, 0x80, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd96[] = {
+	0x7B, 0x91, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd97[] = {
+	0x7C, 0xD8, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd98[] = {
+	0x7D, 0x60, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd99[] = {
+	0x93, 0x06, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd100[] = {
+	0x94, 0x06, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd101[] = {
+	0X8A, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd102[] = {
+	0x9B, 0x0F, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd103[] = {
+	0xB3, 0xC0, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd104[] = {
+	0xB4, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd105[] = {
+	0xB5, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd106[] = {
+	0xB6, 0x21, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd107[] = {
+	0xB7, 0x22, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd108[] = {
+	0xB8, 0x07, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd109[] = {
+	0xB9, 0x07, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd110[] = {
+	0xBA, 0x22, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd111[] = {
+	0XBD, 0x20, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd112[] = {
+	0xBE, 0x07, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd113[] = {
+	0xBF, 0x07, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd114[] = {
+	0xC1, 0x6D, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd115[] = {
+	0xC4, 0x24, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd116[] = {
+	0xE3, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd117[] = {
+	0xEC, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd118[] = {
+	0xFF, 0x10, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd119[] = {
+	0xBB, 0x10, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd120[] = {
+	0x35, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd121[] = {
+	0x11, 0x00, 0x05, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_on_cmd122[] = {
+	0x29, 0x00, 0x05, 0x80,
+};
+
+static struct mipi_dsi_cmd nt35695b_truly_fhd_cmd_on_command[] = {
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd0, 0x10},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd1, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd2, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd3, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd4, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd5, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd6, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd7, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd8, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd9, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd10, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd11, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd12, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd13, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd14, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd15, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd16, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd17, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd18, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd19, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd20, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd21, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd22, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd23, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd24, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd25, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd26, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd27, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd28, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd29, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd30, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd31, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd32, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd33, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd34, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd35, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd36, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd37, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd38, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd39, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd40, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd41, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd42, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd43, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd44, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd45, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd46, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd47, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd48, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd49, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd50, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd51, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd52, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd53, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd54, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd55, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd56, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd57, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd58, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd59, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd60, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd61, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd62, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd63, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd64, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd65, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd66, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd67, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd68, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd69, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd70, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd71, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd72, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd73, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd74, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd75, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd76, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd77, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd78, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd79, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd80, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd81, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd82, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd83, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd84, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd85, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd86, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd87, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd88, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd89, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd90, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd91, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd92, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd93, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd94, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd95, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd96, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd97, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd98, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd99, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd100, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd101, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd102, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd103, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd104, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd105, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd106, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd107, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd108, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd109, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd110, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd111, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd112, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd113, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd114, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd115, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd116, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd117, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd118, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd119, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd120, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd121, 0x78},
+	{ 0x4 , nt35695b_truly_fhd_cmd_on_cmd122, 0x78}
+};
+#define NT35695B_TRULY_FHD_CMD_ON_COMMAND 123
+
+
+static char nt35695b_truly_fhd_cmd_off_cmd0[] = {
+	0x28, 0x00, 0x05, 0x80,
+};
+
+static char nt35695b_truly_fhd_cmd_off_cmd1[] = {
+	0x10, 0x00, 0x05, 0x80,
+};
+
+static struct mipi_dsi_cmd nt35695b_truly_fhd_cmd_off_command[] = {
+	{ 0x4 , nt35695b_truly_fhd_cmd_off_cmd0, 0x14},
+	{ 0x4 , nt35695b_truly_fhd_cmd_off_cmd1, 0x78}
+};
+#define NT35695B_TRULY_FHD_CMD_OFF_COMMAND 2
+
+static struct command_state nt35695b_truly_fhd_cmd_state = {
+	0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information                                            */
+/*---------------------------------------------------------------------------*/
+
+static struct commandpanel_info nt35695b_truly_fhd_cmd_command_panel = {
+	0x1, 0x1, 0x1, 0, 0, 0, 0, 0, 0, 0x1, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information                                              */
+/*---------------------------------------------------------------------------*/
+
+static struct videopanel_info nt35695b_truly_fhd_cmd_video_panel = {
+	0, 0, 0, 0, 1, 1, 1, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration                                                        */
+/*---------------------------------------------------------------------------*/
+
+static struct lane_configuration nt35695b_truly_fhd_cmd_lane_config = {
+	4, 0, 1, 1, 1, 1, 0
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing                                                              */
+/*---------------------------------------------------------------------------*/
+const uint32_t nt35695b_truly_fhd_cmd_timings[] = {
+	0xE6, 0x38, 0x26, 0x00, 0x68, 0x6e, 0x2A, 0x3c, 0x44, 0x03, 0x04, 0x00
+};
+
+const uint32_t nt35695b_truly_fhd_cmd_12nm_timings[] = {
+	0x17, 0x0A, 0x0F, 0x06, 0x03, 0x08, 0x06, 0x0E
+};
+
+
+static struct panel_timing nt35695b_truly_fhd_cmd_timing_info = {
+	0, 4, 0x02, 0x2d
+};
+
+static const uint32_t nt35695b_truly_fhd_14nm_cmd_timings[] = {
+	0x23, 0x1e, 0x7, 0x8, 0x5, 0x3, 0x4, 0xa0,
+	0x23, 0x1e, 0x7, 0x8, 0x5, 0x3, 0x4, 0xa0,
+	0x23, 0x1e, 0x7, 0x8, 0x5, 0x3, 0x4, 0xa0,
+	0x23, 0x1e, 0x7, 0x8, 0x5, 0x3, 0x4, 0xa0,
+	0x23, 0x18, 0x7, 0x8, 0x5, 0x3, 0x4, 0xa0,
+};
+
+static struct labibb_desc nt35695b_truly_fhd_cmd_labibb = {
+	0, 1, 5700000, 5700000, 5700000, 5700000, 3, 3, 1, 0
+};
+
+static struct panel_reset_sequence nt35695b_truly_fhd_cmd_panel_reset_seq = {
+	{ 1, 0, 1, }, { 10, 10, 10, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings                                                        */
+/*---------------------------------------------------------------------------*/
+
+static struct backlight nt35695b_truly_fhd_cmd_backlight = {
+	0, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+#define NT35695B_TRULY_FHD_CMD_SIGNATURE 0xFFFF
+
+#endif /*_NT35695B_TRULY_FHD_CMD_H_*/
diff --git a/dev/gcdb/display/include/panel_nt35695b_truly_fhd_video.h b/dev/gcdb/display/include/panel_nt35695b_truly_fhd_video.h
new file mode 100644
index 0000000..737d394
--- /dev/null
+++ b/dev/gcdb/display/include/panel_nt35695b_truly_fhd_video.h
@@ -0,0 +1,763 @@
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  * Neither the name of The Linux Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PANEL_NT35695B_TRULY_FHD_VIDEO_H_
+
+#define _PANEL_NT35695B_TRULY_FHD_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files                                                              */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration                                                       */
+/*---------------------------------------------------------------------------*/
+
+static struct panel_config nt35695b_truly_fhd_video_panel_data = {
+  "qcom,mdss_dsi_nt35695b_truly_fhd_video", "dsi:0:", "qcom,mdss-dsi-panel",
+  10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution                                                          */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution nt35695b_truly_fhd_video_panel_res = {
+  1080, 1920, 120, 60, 12, 0, 12, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information                                                   */
+/*---------------------------------------------------------------------------*/
+static struct color_info nt35695b_truly_fhd_video_color = {
+  24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information                                                 */
+/*---------------------------------------------------------------------------*/
+static char nt35695b_truly_fhd_video_on_cmd0[] = {
+	0xFF, 0x20, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd1[] = {
+	0XFB, 0x01, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd2[] = {
+	0x00, 0x01, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd3[] = {
+	0x01, 0x55, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd4[] = {
+	0x02, 0x45, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd5[] = {
+	0x03, 0x55, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd6[] = {
+	0x05, 0x50, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd7[] = {
+	0x06, 0xa8, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd8[] = {
+	0x07, 0xAD, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd9[] = {
+	0x08, 0x0C, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd10[] = {
+	0x0B, 0xAA, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd11[] = {
+	0x0C, 0xAA, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd12[] = {
+	0x0E, 0xB0, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd13[] = {
+	0x0F, 0xB3, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd14[] = {
+	0x11, 0x28, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd15[] = {
+	0x12, 0x10, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd16[] = {
+	0x13, 0x01, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd17[] = {
+	0x14, 0x4A, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd18[] = {
+	0x15, 0x12, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd19[] = {
+	0x16, 0x12, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd20[] = {
+	0x30, 0x01, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd21[] = {
+	0x72, 0x11, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd22[] = {
+	0x58, 0x82, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd23[] = {
+	0x59, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd24[] = {
+	0x5A, 0x02, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd25[] = {
+	0x5B, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd26[] = {
+	0x5C, 0x82, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd27[] = {
+	0x5D, 0x80, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd28[] = {
+	0x5E, 0x02, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd29[] = {
+	0x5F, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd30[] = {
+	0xFF, 0x24, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd31[] = {
+	0xFB, 0x01, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd32[] = {
+	0x00, 0x01, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd33[] = {
+	0x01, 0x0B, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd34[] = {
+	0x02, 0x0C, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd35[] = {
+	0x03, 0x89, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd36[] = {
+	0x04, 0x8A, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd37[] = {
+	0x05, 0x0F, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd38[] = {
+	0x06, 0x10, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd39[] = {
+	0x07, 0x01, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd40[] = {
+	0x08, 0x1C, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd41[] = {
+	0X09, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd42[] = {
+	0x0A, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd43[] = {
+	0x0B, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd44[] = {
+	0x0C, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd45[] = {
+	0x0D, 0x13, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd46[] = {
+	0x0E, 0x15, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd47[] = {
+	0x0F, 0x17, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd48[] = {
+	0x10, 0x01, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd49[] = {
+	0x11, 0x0B, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd50[] = {
+	0x12, 0x0C, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd51[] = {
+	0X13, 0x89, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd52[] = {
+	0x14, 0x8A, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd53[] = {
+	0x15, 0x0F, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd54[] = {
+	0x16, 0x10, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd55[] = {
+	0x17, 0x10, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd56[] = {
+	0x18, 0x1C, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd57[] = {
+	0x19, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd58[] = {
+	0x1A, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd59[] = {
+	0x1B, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd60[] = {
+	0x1C, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd61[] = {
+	0X1D, 0x13, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd62[] = {
+	0x1E, 0x15, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd63[] = {
+	0x1F, 0x17, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd64[] = {
+	0x20, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd65[] = {
+	0x21, 0x01, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd66[] = {
+	0x22, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd67[] = {
+	0x23, 0x40, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd68[] = {
+	0x24, 0x40, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd69[] = {
+	0x25, 0x6D, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd70[] = {
+	0x26, 0x40, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd71[] = {
+	0X27, 0x40, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd72[] = {
+	0x29, 0xD8, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd73[] = {
+	0x2A, 0x2A, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd74[] = {
+	0x4B, 0x03, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd75[] = {
+	0x4C, 0x11, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd76[] = {
+	0x4D, 0x10, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd77[] = {
+	0x4E, 0x01, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd78[] = {
+	0x4F, 0x01, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd79[] = {
+	0x50, 0x10, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd80[] = {
+	0x51, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd81[] = {
+	0X52, 0x80, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd82[] = {
+	0x53, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd83[] = {
+	0x54, 0x07, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd84[] = {
+	0x55, 0x25, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd85[] = {
+	0x56, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd86[] = {
+	0x58, 0x07, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd87[] = {
+	0x5b, 0x43, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd88[] = {
+	0x5c, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd89[] = {
+	0x5F, 0x73, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd90[] = {
+	0x60, 0x73, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd91[] = {
+	0x63, 0x22, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd92[] = {
+	0x64, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd93[] = {
+	0x67, 0x08, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd94[] = {
+	0x68, 0x04, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd95[] = {
+	0x7A, 0x80, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd96[] = {
+	0x7B, 0x91, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd97[] = {
+	0x7C, 0xD8, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd98[] = {
+	0x7D, 0x60, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd99[] = {
+	0x93, 0x06, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd100[] = {
+	0x94, 0x06, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd101[] = {
+	0X8A, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd102[] = {
+	0x9B, 0x0F, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd103[] = {
+	0xB3, 0xC0, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd104[] = {
+	0xB4, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd105[] = {
+	0xB5, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd106[] = {
+	0xB6, 0x21, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd107[] = {
+	0xB7, 0x22, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd108[] = {
+	0xB8, 0x07, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd109[] = {
+	0xB9, 0x07, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd110[] = {
+	0xBA, 0x22, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd111[] = {
+	0XBD, 0x20, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd112[] = {
+	0xBE, 0x07, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd113[] = {
+	0xBF, 0x07, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd114[] = {
+	0xC1, 0x6D, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd115[] = {
+	0xC4, 0x24, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd116[] = {
+	0xE3, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd117[] = {
+	0xEC, 0x00, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd118[] = {
+	0xFF, 0x10, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd119[] = {
+	0xBB, 0x03, 0x15, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd120[] = {
+	0x11, 0x00, 0x05, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_on_cmd121[] = {
+	0x29, 0x00, 0x05, 0x80,
+};
+
+static struct mipi_dsi_cmd nt35695b_truly_fhd_video_on_command[] = {
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd0, 0x10},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd1, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd2, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd3, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd4, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd5, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd6, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd7, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd8, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd9, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd10, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd11, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd12, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd13, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd14, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd15, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd16, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd17, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd18, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd19, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd20, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd21, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd22, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd23, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd24, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd25, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd26, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd27, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd28, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd29, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd30, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd31, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd32, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd33, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd34, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd35, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd36, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd37, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd38, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd39, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd40, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd41, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd42, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd43, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd44, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd45, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd46, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd47, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd48, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd49, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd50, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd51, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd52, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd53, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd54, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd55, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd56, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd57, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd58, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd59, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd60, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd61, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd62, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd63, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd64, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd65, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd66, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd67, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd68, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd69, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd70, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd71, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd72, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd73, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd74, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd75, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd76, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd77, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd78, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd79, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd80, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd81, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd82, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd83, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd84, 0x00},
+	{ 0x4 ,	nt35695b_truly_fhd_video_on_cmd85, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd86, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd87, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd88, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd89, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd90, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd91, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd92, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd93, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd94, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd95, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd96, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd97, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd98, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd99, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd100, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd101, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd102, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd103, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd104, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd105, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd106, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd107, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd108, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd109, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd110, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd111, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd112, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd113, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd114, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd115, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd116, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd117, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd118, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd119, 0x00},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd120, 0x78},
+	{ 0x4 , nt35695b_truly_fhd_video_on_cmd121, 0x78}
+};
+#define NT35695B_TRULY_FHD_VIDEO_ON_COMMAND 122
+
+static char nt35695b_truly_fhd_video_off_cmd0[] = {
+	0x28, 0x00, 0x05, 0x80,
+};
+
+static char nt35695b_truly_fhd_video_off_cmd1[] = {
+	0x10, 0x00, 0x05, 0x80,
+};
+
+static struct mipi_dsi_cmd nt35695b_truly_fhd_video_off_command[] = {
+	{ 0x4 , nt35695b_truly_fhd_video_off_cmd0, 0x14},
+	{ 0x4 , nt35695b_truly_fhd_video_off_cmd1, 0x78}
+};
+#define NT35695B_TRULY_FHD_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state nt35695b_truly_fhd_video_state = {
+  0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information                                            */
+/*---------------------------------------------------------------------------*/
+
+static struct commandpanel_info nt35695b_truly_fhd_video_command_panel = {
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information                                              */
+/*---------------------------------------------------------------------------*/
+
+static struct videopanel_info nt35695b_truly_fhd_video_video_panel = {
+  0, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration                                                        */
+/*---------------------------------------------------------------------------*/
+
+static struct lane_configuration nt35695b_truly_fhd_video_lane_config = {
+  4, 0, 1, 1, 1, 1, 0
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing                                                              */
+/*---------------------------------------------------------------------------*/
+const uint32_t nt35695b_truly_fhd_video_timings[] = {
+  0xE6, 0x38, 0x26, 0x00, 0x68, 0x6e, 0x2A, 0x3c, 0x44, 0x03, 0x04, 0x00
+};
+
+const uint32_t nt35695b_truly_fhd_video_12nm_timings[] = {
+  0x17, 0x0A, 0x0F, 0x06, 0x03, 0x08, 0x06, 0x0E
+};
+
+static const uint32_t nt35695b_truly_fhd_14nm_video_timings[] = {
+	0x23, 0x1e, 0x8, 0x9, 0x5, 0x3, 0x4, 0xa0,
+	0x23, 0x1e, 0x8, 0x9, 0x5, 0x3, 0x4, 0xa0,
+	0x23, 0x1e, 0x8, 0x9, 0x5, 0x3, 0x4, 0xa0,
+	0x23, 0x1e, 0x8, 0x9, 0x5, 0x3, 0x4, 0xa0,
+	0x23, 0x1a, 0x8, 0x9, 0x5, 0x3, 0x4, 0xa0,
+};
+
+static struct panel_timing nt35695b_truly_fhd_video_timing_info = {
+  0, 4, 0x02, 0x2d
+};
+
+static struct labibb_desc nt35695b_truly_fhd_video_labibb = {
+	0, 1, 5700000, 5700000, 5700000, 5700000, 3, 3, 1, 0
+};
+
+static struct panel_reset_sequence nt35695b_truly_fhd_video_panel_reset_seq = {
+{ 1, 0, 1, }, { 10, 10, 10, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings                                                        */
+/*---------------------------------------------------------------------------*/
+
+static struct backlight nt35695b_truly_fhd_video_backlight = {
+  0, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+#define NT35695B_TRULY_FHD_VIDEO_SIGNATURE 0xFFFF
+
+#endif /*_NT35695B_TRULY_FHD_VIDEO_H_*/
diff --git a/dev/gcdb/display/panel_display.h b/dev/gcdb/display/panel_display.h
index ed99a98..c305a4c 100755
--- a/dev/gcdb/display/panel_display.h
+++ b/dev/gcdb/display/panel_display.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, 2018, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -39,6 +39,7 @@
 #define BPP_24 24
 
 #define TIMING_SIZE 48
+#define TIMING_SIZE_12NM 32
 #define REGULATOR_SIZE 28
 
 #define DUAL_DSI_FLAG 0x1
diff --git a/dev/pmic/pm8x41/include/pm8x41.h b/dev/pmic/pm8x41/include/pm8x41.h
index 65011ec..014834a 100644
--- a/dev/pmic/pm8x41/include/pm8x41.h
+++ b/dev/pmic/pm8x41/include/pm8x41.h
@@ -41,7 +41,7 @@
 /* 1.5uA + 30uA boost */
 #define PM_GPIO_PULL_UP_1_5_30  3
 #define PM_GPIO_PULLDOWN_10     4
-#define PM_GPIO_PULL_RESV_2     5
+#define PM_GPIO_NO_PULL         5
 
 
 #define PM_GPIO_OUT_CMOS        0x00
diff --git a/platform/msm8952/acpuclock.c b/platform/msm8952/acpuclock.c
index ec37789..57e4d0c 100644
--- a/platform/msm8952/acpuclock.c
+++ b/platform/msm8952/acpuclock.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -321,11 +321,35 @@
 	}
 }
 
+void gcc_dsi_lp_clock_enable(uint32_t flags)
+{
+	int ret = 0;
+
+	if (flags & MMSS_DSI_CLKS_FLAG_DSI0) {
+		/* Configure ESC clock */
+		ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
+		if (ret) {
+			dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n",
+				ret);
+			ASSERT(0);
+		}
+	}
+
+	if (flags & MMSS_DSI_CLKS_FLAG_DSI1) {
+		/* Configure ESC clock */
+		ret = clk_get_set_enable("mdss_esc1_clk", 0, 1);
+		if (ret) {
+			dprintf(CRITICAL, "failed to set esc1_clk ret = %d\n",
+				ret);
+			ASSERT(0);
+		}
+	}
+}
+
 /* Configure all the branch clocks needed by the DSI controller */
-void gcc_dsi_clocks_enable(uint32_t flags, bool use_dsi1_pll, uint8_t pclk0_m,
+void gcc_dsi_hs_clocks_enable(uint32_t flags, bool use_dsi1_pll, uint8_t pclk0_m,
 		uint8_t pclk0_n, uint8_t pclk0_d)
 {
-	int ret;
 	int dsi0_cfg_rcgr, dsi1_cfg_rcgr = 0;
 
 	dsi0_cfg_rcgr = BIT(8); /* DSI0 can only be sourced from PLL0 */
@@ -364,13 +388,6 @@
 		/* Enable the branch clock */
 		writel(0x1, DSI_PIXEL0_CBCR);
 		branch_clk_halt_check(DSI_PIXEL0_CBCR);
-
-		/* Configure ESC clock */
-		ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
-		if (ret) {
-			dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret);
-			ASSERT(0);
-		}
 	}
 
 	if (flags & MMSS_DSI_CLKS_FLAG_DSI1) {
@@ -398,13 +415,6 @@
 		/* Enable the branch clock */
 		writel(0x1, DSI_PIXEL1_CBCR);
 		branch_clk_halt_check(DSI_PIXEL1_CBCR);
-
-		/* Configure ESC clock */
-		ret = clk_get_set_enable("mdss_esc1_clk", 0, 1);
-		if (ret) {
-			dprintf(CRITICAL, "failed to set esc1_clk ret = %d\n", ret);
-			ASSERT(0);
-		}
 	}
 }
 
diff --git a/platform/msm8952/include/platform/clock.h b/platform/msm8952/include/platform/clock.h
index c9e8cc7..e6734cb 100644
--- a/platform/msm8952/include/platform/clock.h
+++ b/platform/msm8952/include/platform/clock.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -95,7 +95,8 @@
 void mdss_bus_clocks_disable(void);
 void mdp_clock_enable(void);
 void mdp_clock_disable(void);
-void gcc_dsi_clocks_enable(uint32_t flags,  bool use_dsi1_pll, uint8_t pclk0_m,
+void gcc_dsi_hs_clocks_enable(uint32_t flags,  bool use_dsi1_pll, uint8_t pclk0_m,
 		uint8_t pclk0_n, uint8_t pclk0_d);
+void gcc_dsi_lp_clock_enable(uint32_t flags);
 void gcc_dsi_clocks_disable(uint32_t flags);
 #endif
diff --git a/platform/msm_shared/avb/VerifiedBoot.c b/platform/msm_shared/avb/VerifiedBoot.c
index 06da64f..f2fa372 100644
--- a/platform/msm_shared/avb/VerifiedBoot.c
+++ b/platform/msm_shared/avb/VerifiedBoot.c
@@ -154,7 +154,7 @@
 		if (current_active_slot == INVALID)
 			return 0;
 		current_slot_suffix = SUFFIX_SLOT(current_active_slot);
-		strncat(PartitionName, current_slot_suffix, MAX_GPT_NAME_SIZE - 1);
+		strlcat(PartitionName, current_slot_suffix, MAX_GPT_NAME_SIZE - 1);
 	}
 
 	Index = partition_get_index(PartitionName);
diff --git a/platform/msm_shared/include/mipi_dsi.h b/platform/msm_shared/include/mipi_dsi.h
index 1457877..f0dfbe1 100644
--- a/platform/msm_shared/include/mipi_dsi.h
+++ b/platform/msm_shared/include/mipi_dsi.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2015, 2018, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -149,6 +149,7 @@
 	DSI_PLL_TYPE_28NM,
 	DSI_PLL_TYPE_20NM,
 	DSI_PLL_TYPE_THULIUM,
+	DSI_PLL_TYPE_12NM,
 	DSI_PLL_TYPE_MAX,
 };
 
@@ -223,6 +224,11 @@
 	uint32_t postdiv;
 	uint32_t n1div;
 	uint32_t n2div;
+
+	/* pll 12nm */
+	uint32_t p_div_mux;
+	uint32_t gp_div_mux;
+	uint32_t divhf;
 };
 
 struct mipi_dsi_cmd {
@@ -268,6 +274,7 @@
 void mdss_dsi_phy_contention_detection(struct mipi_panel_info *mipi,
 				uint32_t phy_base);
 int mipi_dsi_phy_init(struct mipi_dsi_panel_config *pinfo);
+void mdss_dsi_lane_config(struct msm_panel_info *pinfo);
 
 int mdss_dsi_video_mode_config(struct msm_panel_info *pinfo,
 	uint16_t disp_width,
@@ -311,6 +318,8 @@
 void mdss_dsi_auto_pll_20nm_config(struct msm_panel_info *pinfo);
 void mdss_dsi_pll_20nm_sw_reset_st_machine(uint32_t pll_base);
 uint32_t mdss_dsi_pll_20nm_lock_status(uint32_t pll_base);
+void mdss_dsi_auto_pll_12nm_config(struct msm_panel_info *pinfo);
+bool mdss_dsi_auto_pll_12nm_enable(struct msm_panel_info *pinfo);
 void mdss_dsi_uniphy_pll_lock_detect_setting(uint32_t pll_base);
 void mdss_dsi_uniphy_pll_sw_reset(uint32_t pll_base);
 int mdss_dsi_post_on(struct msm_fb_panel_data *panel);
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index 56827f5..3b1d3df 100644
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -444,6 +444,7 @@
 	int (*early_config) (void *pdata);
 	int (*config) (void *pdata);
 	int (*rotate) (void);
+	void (*lane_config)(struct msm_panel_info *pinfo);
 
 	char autorefresh_enable;
 	uint32_t autorefresh_framenum;
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 68d784d..818155f 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2016, 2018, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -396,7 +396,9 @@
 		else
 			lane_swap_dsi1 = lane_swap;
 		writel(lane_swap_dsi1, mipi->sctl_base + LANE_SWAP_CTL);
-		writel(timing_ctl, mipi->sctl_base + TIMING_CTL);
+		if (mipi->mdss_dsi_phy_db->pll_type != DSI_PLL_TYPE_12NM)
+			writel_relaxed(timing_ctl,
+				mipi->sctl_base + TIMING_CTL);
 
 		if ((mipi->mode == DSI_CMD_MODE) &&
 				(readl(mipi->sctl_base) >= DSI_HW_REV_103)) {
@@ -424,7 +426,8 @@
 	       mipi->ctl_base + COMMAND_MODE_DMA_CTRL);
 
 	writel(lane_swap, mipi->ctl_base + LANE_SWAP_CTL);
-	writel(timing_ctl, mipi->ctl_base + TIMING_CTL);
+	if (mipi->mdss_dsi_phy_db->pll_type != DSI_PLL_TYPE_12NM)
+		writel_relaxed(timing_ctl, mipi->ctl_base + TIMING_CTL);
 
 	if ((mipi->mode == DSI_CMD_MODE) &&
 			(readl(mipi->ctl_base) >= DSI_HW_REV_103)) {
@@ -1086,3 +1089,23 @@
 #endif
 	return ret;
 }
+
+void mdss_dsi_lane_config(struct msm_panel_info *pinfo)
+{
+	uint8_t lane_enable = 0;
+
+	if (pinfo->mipi.data_lane0)
+		lane_enable |= (1 << 0);
+	if (pinfo->mipi.data_lane1)
+		lane_enable |= (1 << 1);
+	if (pinfo->mipi.data_lane2)
+		lane_enable |= (1 << 2);
+	if (pinfo->mipi.data_lane3)
+		lane_enable |= (1 << 3);
+
+	writel_relaxed((0 << 30 | 0 << 24 | 0 << 20 |
+		lane_enable << 4 | 0x105), pinfo->mipi.ctl_base + CTRL);
+	if (pinfo->mipi.dual_dsi)
+		writel_relaxed((0 << 30 | 0 << 24 | 0 << 20 | lane_enable << 4 |
+			0x105), pinfo->mipi.sctl_base + CTRL);
+}
diff --git a/platform/msm_shared/mipi_dsi_autopll_12nm.c b/platform/msm_shared/mipi_dsi_autopll_12nm.c
new file mode 100644
index 0000000..8170b33
--- /dev/null
+++ b/platform/msm_shared/mipi_dsi_autopll_12nm.c
@@ -0,0 +1,699 @@
+ /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
+  *
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are
+  * met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above
+  *       copyright notice, this list of conditions and the following
+  *       disclaimer in the documentation and/or other materials provided
+  *       with the distribution.
+  *     * Neither the name of The Linux Foundation nor the names of its
+  *       contributors may be used to endorse or promote products derived
+  *       from this software without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  */
+#include <debug.h>
+#include <bits.h>
+#include <reg.h>
+#include <err.h>
+#include <smem.h>
+#include <clock.h>
+#include <mipi_dsi.h>
+#include <platform/iomap.h>
+#include <qtimer.h>
+#include <arch/defines.h>
+
+#define VCO_REF_CLOCK_RATE 19200000
+
+#define DSIPHY_T_TA_GO_TIM_COUNT			0x014
+#define DSIPHY_T_TA_SURE_TIM_COUNT			0x018
+#define DSIPHY_PLL_POWERUP_CTRL				0x034
+#define DSIPHY_PLL_PROP_CHRG_PUMP_CTRL			0x038
+#define DSIPHY_PLL_INTEG_CHRG_PUMP_CTRL			0x03c
+#define DSIPHY_PLL_ANA_TST_LOCK_ST_OVR_CTRL		0x044
+#define DSIPHY_PLL_VCO_CTRL				0x048
+#define DSIPHY_PLL_GMP_CTRL_DIG_TST			0x04c
+#define DSIPHY_PLL_PHA_ERR_CTRL_0			0x050
+#define DSIPHY_PLL_LOCK_FILTER				0x054
+#define DSIPHY_PLL_UNLOCK_FILTER			0x058
+#define DSIPHY_PLL_INPUT_DIV_PLL_OVR			0x05c
+#define DSIPHY_PLL_LOOP_DIV_RATIO_0			0x060
+#define DSIPHY_PLL_INPUT_LOOP_DIV_RAT_CTRL		0x064
+#define DSIPHY_PLL_PRO_DLY_RELOCK			0x06c
+#define DSIPHY_PLL_CHAR_PUMP_BIAS_CTRL			0x070
+#define DSIPHY_PLL_LOCK_DET_MODE_SEL			0x074
+#define DSIPHY_PLL_ANA_PROG_CTRL			0x07c
+#define DSIPHY_HSTX_DRIV_INDATA_CTRL_CLKLANE		0x0c0
+#define DSIPHY_HSTX_DATAREV_CTRL_CLKLANE		0x0d4
+#define DSIPHY_HSTX_DRIV_INDATA_CTRL_LANE0		0x100
+#define DSIPHY_HS_FREQ_RAN_SEL				0x110
+#define DSIPHY_HSTX_READY_DLY_DATA_REV_CTRL_LANE0	0x114
+#define DSIPHY_HSTX_DRIV_INDATA_CTRL_LANE1		0x140
+#define DSIPHY_HSTX_READY_DLY_DATA_REV_CTRL_LANE1	0x154
+#define DSIPHY_HSTX_CLKLANE_REQSTATE_TIM_CTRL		0x180
+#define DSIPHY_HSTX_CLKLANE_HS0STATE_TIM_CTRL		0x188
+#define DSIPHY_HSTX_CLKLANE_TRALSTATE_TIM_CTRL		0x18c
+#define DSIPHY_HSTX_CLKLANE_EXITSTATE_TIM_CTRL		0x190
+#define DSIPHY_HSTX_CLKLANE_CLKPOSTSTATE_TIM_CTRL	0x194
+#define DSIPHY_HSTX_DATALANE_REQSTATE_TIM_CTRL		0x1c0
+#define DSIPHY_HSTX_DATALANE_HS0STATE_TIM_CTRL		0x1c8
+#define DSIPHY_HSTX_DATALANE_TRAILSTATE_TIM_CTRL	0x1cc
+#define DSIPHY_HSTX_DATALANE_EXITSTATE_TIM_CTRL		0x1d0
+#define DSIPHY_HSTX_DRIV_INDATA_CTRL_LANE2		0x200
+#define DSIPHY_HSTX_READY_DLY_DATA_REV_CTRL_LANE2	0x214
+#define DSIPHY_HSTX_READY_DLY_DATA_REV_CTRL_LANE3	0x254
+#define DSIPHY_HSTX_DRIV_INDATA_CTRL_LANE3		0x240
+#define DSIPHY_SLEWRATE_FSM_OVR_CTRL			0x280
+#define DSIPHY_SLEWRATE_DDL_LOOP_CTRL			0x28c
+#define DSIPHY_SLEWRATE_DDL_CYC_FRQ_ADJ_0		0x290
+#define DSIPHY_PLL_PHA_ERR_CTRL_1			0x2e4
+#define DSIPHY_PLL_LOOP_DIV_RATIO_1			0x2e8
+#define DSIPHY_SLEWRATE_DDL_CYC_FRQ_ADJ_1		0x328
+#define DSIPHY_SSC0					0x394
+#define DSIPHY_SSC1					0x398
+#define DSIPHY_SSC2					0x39c
+#define DSIPHY_SSC3					0x3a0
+#define DSIPHY_SSC4					0x3a4
+#define DSIPHY_SSC5					0x3a8
+#define DSIPHY_SSC6					0x3ac
+#define DSIPHY_SSC10					0x360
+#define DSIPHY_SSC11					0x364
+#define DSIPHY_SSC12					0x368
+#define DSIPHY_SSC13					0x36c
+#define DSIPHY_SSC14					0x370
+#define DSIPHY_SSC15					0x374
+#define DSIPHY_SSC7					0x3b0
+#define DSIPHY_SSC8					0x3b4
+#define DSIPHY_SSC9					0x3b8
+#define DSIPHY_STAT0					0x3e0
+#define DSIPHY_CTRL0					0x3e8
+#define DSIPHY_SYS_CTRL					0x3f0
+#define DSIPHY_PLL_CTRL					0x3f8
+#define DSIPHY_REQ_DLY					0x3fc
+
+struct dsi_pll_param {
+	uint32_t vco_freq;
+	uint32_t hsfreqrange;
+	uint32_t vco_cntrl;
+	uint32_t osc_freq_target;
+	uint32_t m_div;
+	uint32_t prop_cntrl;
+	uint32_t int_cntrl;
+	uint32_t gmp_cntrl;
+	uint32_t cpbias_cntrl;
+
+	/* mux and dividers */
+	uint32_t gp_div_mux;
+	uint32_t post_div_mux;
+	uint32_t pixel_divhf;
+	uint32_t fsm_ovr_ctrl;
+
+	/* SSC parameters */
+	uint32_t mpll_ssc_peak_i;
+	uint32_t mpll_stepsize_i;
+	uint32_t mpll_mint_i;
+	uint32_t mpll_frac_den;
+	uint32_t mpll_frac_quot_i;
+	uint32_t mpll_frac_rem;
+};
+
+static uint32_t __mdss_dsi_get_hsfreqrange(uint64_t target_freq)
+{
+	uint64_t bitclk_rate_mhz = ((target_freq * 2) / 1000000);
+
+	if (bitclk_rate_mhz >= 80 && bitclk_rate_mhz < 90)
+		return 0x00;
+	else if (bitclk_rate_mhz >= 90 && bitclk_rate_mhz < 100)
+		return 0x10;
+	else if (bitclk_rate_mhz >= 100 && bitclk_rate_mhz < 110)
+		return  0x20;
+	else if (bitclk_rate_mhz >= 110 && bitclk_rate_mhz < 120)
+		return  0x30;
+	else if (bitclk_rate_mhz >= 120 && bitclk_rate_mhz < 130)
+		return  0x01;
+	else if (bitclk_rate_mhz >= 130 && bitclk_rate_mhz < 140)
+		return  0x11;
+	else if (bitclk_rate_mhz >= 140 && bitclk_rate_mhz < 150)
+		return  0x21;
+	else if (bitclk_rate_mhz >= 150 && bitclk_rate_mhz < 160)
+		return  0x31;
+	else if (bitclk_rate_mhz >= 160 && bitclk_rate_mhz < 170)
+		return  0x02;
+	else if (bitclk_rate_mhz >= 170 && bitclk_rate_mhz < 180)
+		return  0x12;
+	else if (bitclk_rate_mhz >= 180 && bitclk_rate_mhz < 190)
+		return  0x22;
+	else if (bitclk_rate_mhz >= 190 && bitclk_rate_mhz < 205)
+		return  0x32;
+	else if (bitclk_rate_mhz >= 205 && bitclk_rate_mhz < 220)
+		return  0x03;
+	else if (bitclk_rate_mhz >= 220 && bitclk_rate_mhz < 235)
+		return  0x13;
+	else if (bitclk_rate_mhz >= 235 && bitclk_rate_mhz < 250)
+		return  0x23;
+	else if (bitclk_rate_mhz >= 250 && bitclk_rate_mhz < 275)
+		return  0x33;
+	else if (bitclk_rate_mhz >= 275 && bitclk_rate_mhz < 300)
+		return  0x04;
+	else if (bitclk_rate_mhz >= 300 && bitclk_rate_mhz < 325)
+		return  0x14;
+	else if (bitclk_rate_mhz >= 325 && bitclk_rate_mhz < 350)
+		return  0x25;
+	else if (bitclk_rate_mhz >= 350 && bitclk_rate_mhz < 400)
+		return  0x35;
+	else if (bitclk_rate_mhz >= 400 && bitclk_rate_mhz < 450)
+		return  0x05;
+	else if (bitclk_rate_mhz >= 450 && bitclk_rate_mhz < 500)
+		return  0x16;
+	else if (bitclk_rate_mhz >= 500 && bitclk_rate_mhz < 550)
+		return  0x26;
+	else if (bitclk_rate_mhz >= 550 && bitclk_rate_mhz < 600)
+		return  0x37;
+	else if (bitclk_rate_mhz >= 600 && bitclk_rate_mhz < 650)
+		return  0x07;
+	else if (bitclk_rate_mhz >= 650 && bitclk_rate_mhz < 700)
+		return  0x18;
+	else if (bitclk_rate_mhz >= 700 && bitclk_rate_mhz < 750)
+		return  0x28;
+	else if (bitclk_rate_mhz >= 750 && bitclk_rate_mhz < 800)
+		return  0x39;
+	else if (bitclk_rate_mhz >= 800 && bitclk_rate_mhz < 850)
+		return  0x09;
+	else if (bitclk_rate_mhz >= 850 && bitclk_rate_mhz < 900)
+		return  0x19;
+	else if (bitclk_rate_mhz >= 900 && bitclk_rate_mhz < 950)
+		return  0x29;
+	else if (bitclk_rate_mhz >= 950 && bitclk_rate_mhz < 1000)
+		return  0x3a;
+	else if (bitclk_rate_mhz >= 1000 && bitclk_rate_mhz < 1050)
+		return  0x0a;
+	else if (bitclk_rate_mhz >= 1050 && bitclk_rate_mhz < 1100)
+		return  0x1a;
+	else if (bitclk_rate_mhz >= 1100 && bitclk_rate_mhz < 1150)
+		return  0x2a;
+	else if (bitclk_rate_mhz >= 1150 && bitclk_rate_mhz < 1200)
+		return  0x3b;
+	else if (bitclk_rate_mhz >= 1200 && bitclk_rate_mhz < 1250)
+		return  0x0b;
+	else if (bitclk_rate_mhz >= 1250 && bitclk_rate_mhz < 1300)
+		return  0x1b;
+	else if (bitclk_rate_mhz >= 1300 && bitclk_rate_mhz < 1350)
+		return  0x2b;
+	else if (bitclk_rate_mhz >= 1350 && bitclk_rate_mhz < 1400)
+		return  0x3c;
+	else if (bitclk_rate_mhz >= 1400 && bitclk_rate_mhz < 1450)
+		return  0x0c;
+	else if (bitclk_rate_mhz >= 1450 && bitclk_rate_mhz < 1500)
+		return  0x1c;
+	else if (bitclk_rate_mhz >= 1500 && bitclk_rate_mhz < 1550)
+		return  0x2c;
+	else if (bitclk_rate_mhz >= 1550 && bitclk_rate_mhz < 1600)
+		return  0x3d;
+	else if (bitclk_rate_mhz >= 1600 && bitclk_rate_mhz < 1650)
+		return  0x0d;
+	else if (bitclk_rate_mhz >= 1650 && bitclk_rate_mhz < 1700)
+		return  0x1d;
+	else if (bitclk_rate_mhz >= 1700 && bitclk_rate_mhz < 1750)
+		return  0x2e;
+	else if (bitclk_rate_mhz >= 1750 && bitclk_rate_mhz < 1800)
+		return  0x3e;
+	else if (bitclk_rate_mhz >= 1800 && bitclk_rate_mhz < 1850)
+		return  0x0e;
+	else if (bitclk_rate_mhz >= 1850 && bitclk_rate_mhz < 1900)
+		return  0x1e;
+	else if (bitclk_rate_mhz >= 1900 && bitclk_rate_mhz < 1950)
+		return  0x2f;
+	else if (bitclk_rate_mhz >= 1950 && bitclk_rate_mhz < 2000)
+		return  0x3f;
+	else if (bitclk_rate_mhz >= 2000 && bitclk_rate_mhz < 2050)
+		return  0x0f;
+	else if (bitclk_rate_mhz >= 2050 && bitclk_rate_mhz < 2100)
+		return  0x40;
+	else if (bitclk_rate_mhz >= 2100 && bitclk_rate_mhz < 2150)
+		return  0x41;
+	else if (bitclk_rate_mhz >= 2150 && bitclk_rate_mhz < 2200)
+		return  0x42;
+	else if (bitclk_rate_mhz >= 2200 && bitclk_rate_mhz < 2250)
+		return  0x43;
+	else if (bitclk_rate_mhz >= 2250 && bitclk_rate_mhz < 2300)
+		return  0x44;
+	else if (bitclk_rate_mhz >= 2300 && bitclk_rate_mhz < 2350)
+		return  0x45;
+	else if (bitclk_rate_mhz >= 2350 && bitclk_rate_mhz < 2400)
+		return  0x46;
+	else if (bitclk_rate_mhz >= 2400 && bitclk_rate_mhz < 2450)
+		return  0x47;
+	else if (bitclk_rate_mhz >= 2450 && bitclk_rate_mhz < 2500)
+		return  0x48;
+	else
+		return  0x49;
+}
+
+static void __mdss_dsi_get_pll_vco_cntrl(uint64_t target_freq,
+	uint32_t post_div_mux, uint32_t *vco_cntrl, uint32_t *cpbias_cntrl)
+{
+	uint64_t target_freq_mhz = (target_freq / 1000000);
+	uint32_t p_div = BIT(post_div_mux);
+
+	if (p_div == 1) {
+		*vco_cntrl = 0x00;
+		*cpbias_cntrl = 0;
+	} else if (p_div == 2) {
+		*vco_cntrl = 0x30;
+		*cpbias_cntrl = 1;
+	} else if (p_div == 4) {
+		*vco_cntrl = 0x10;
+		*cpbias_cntrl = 0;
+	} else if (p_div == 8) {
+		*vco_cntrl = 0x20;
+		*cpbias_cntrl = 0;
+	} else if (p_div == 16) {
+		*vco_cntrl = 0x30;
+		*cpbias_cntrl = 0;
+	} else {
+		*vco_cntrl = 0x00;
+		*cpbias_cntrl = 1;
+	}
+
+	if (target_freq_mhz <= 1250 && target_freq_mhz >= 1092)
+		*vco_cntrl = *vco_cntrl | 2;
+	else if (target_freq_mhz < 1092 && target_freq_mhz >= 950)
+		*vco_cntrl =  *vco_cntrl | 3;
+	else if (target_freq_mhz < 950 && target_freq_mhz >= 712)
+		*vco_cntrl = *vco_cntrl | 1;
+	else if (target_freq_mhz < 712 && target_freq_mhz >= 546)
+		*vco_cntrl =  *vco_cntrl | 2;
+	else if (target_freq_mhz < 546 && target_freq_mhz >= 475)
+		*vco_cntrl = *vco_cntrl | 3;
+	else if (target_freq_mhz < 475 && target_freq_mhz >= 356)
+		*vco_cntrl =  *vco_cntrl | 1;
+	else if (target_freq_mhz < 356 && target_freq_mhz >= 273)
+		*vco_cntrl = *vco_cntrl | 2;
+	else if (target_freq_mhz < 273 && target_freq_mhz >= 237)
+		*vco_cntrl =  *vco_cntrl | 3;
+	else if (target_freq_mhz < 237 && target_freq_mhz >= 178)
+		*vco_cntrl = *vco_cntrl | 1;
+	else if (target_freq_mhz < 178 && target_freq_mhz >= 136)
+		*vco_cntrl =  *vco_cntrl | 2;
+	else if (target_freq_mhz < 136 && target_freq_mhz >= 118)
+		*vco_cntrl = *vco_cntrl | 3;
+	else if (target_freq_mhz < 118 && target_freq_mhz >= 89)
+		*vco_cntrl =  *vco_cntrl | 1;
+	else if (target_freq_mhz < 89 && target_freq_mhz >= 68)
+		*vco_cntrl = *vco_cntrl | 2;
+	else if (target_freq_mhz < 68 && target_freq_mhz >= 57)
+		*vco_cntrl =  *vco_cntrl | 3;
+	else if (target_freq_mhz < 57 && target_freq_mhz >= 44)
+		*vco_cntrl = *vco_cntrl | 1;
+	else
+		*vco_cntrl =  *vco_cntrl | 2;
+}
+
+static uint32_t __mdss_dsi_get_osc_freq_target(uint64_t target_freq)
+{
+	uint64_t target_freq_mhz = (target_freq / 1000000);
+
+	if (target_freq_mhz <= 1000)
+		return 1315;
+	else if (target_freq_mhz > 1000 && target_freq_mhz <= 1500)
+		return 1839;
+	else
+		return 0;
+}
+
+static uint64_t __mdss_dsi_pll_get_m_div(uint64_t vco_rate)
+{
+	return ((vco_rate * 4) / VCO_REF_CLOCK_RATE);
+}
+
+static uint32_t __mdss_dsi_get_fsm_ovr_ctrl(uint64_t target_freq)
+{
+	uint64_t bitclk_rate_mhz = ((target_freq * 2) / 1000000);
+
+	if (bitclk_rate_mhz > 1500 && bitclk_rate_mhz <= 2500)
+		return 0;
+	else
+		return BIT(6);
+}
+
+static void mdss_dsi_pll_12nm_calc_reg(struct dsi_pll_param *param)
+{
+	uint64_t target_freq = 0;
+
+	target_freq = (param->vco_freq / BIT(param->post_div_mux));
+
+	param->hsfreqrange = __mdss_dsi_get_hsfreqrange(target_freq);
+	__mdss_dsi_get_pll_vco_cntrl(target_freq, param->post_div_mux,
+		&param->vco_cntrl, &param->cpbias_cntrl);
+	param->osc_freq_target = __mdss_dsi_get_osc_freq_target(target_freq);
+	param->m_div = (uint32_t) __mdss_dsi_pll_get_m_div(param->vco_freq);
+	param->fsm_ovr_ctrl = __mdss_dsi_get_fsm_ovr_ctrl(target_freq);
+	param->prop_cntrl = 0x05;
+	param->int_cntrl = 0x00;
+	param->gmp_cntrl = 0x1;
+}
+
+static uint32_t __mdss_dsi_get_multi_intX100(uint64_t vco_rate, uint32_t *rem)
+{
+	uint32_t reminder = 0;
+	uint64_t temp = 0;
+	const uint32_t quarterX100 = 25;
+
+	temp = vco_rate / VCO_REF_CLOCK_RATE;
+	temp *= 100;
+	reminder = vco_rate % VCO_REF_CLOCK_RATE;
+
+	/*
+	 * Multiplication integer needs to be floored in steps of 0.25
+	 * Hence multi_intX100 needs to be rounded off in steps of 25
+	 */
+	if (reminder < (VCO_REF_CLOCK_RATE / 4)) {
+		*rem = reminder;
+		return temp;
+	} else if (reminder >= (VCO_REF_CLOCK_RATE / 4) &&
+		reminder < (VCO_REF_CLOCK_RATE / 2)) {
+		*rem = (reminder - (VCO_REF_CLOCK_RATE / 4));
+		return (temp + quarterX100);
+	} else if (reminder >= (VCO_REF_CLOCK_RATE / 2) &&
+		reminder < ((3 * VCO_REF_CLOCK_RATE) / 4)) {
+		*rem = (reminder - (VCO_REF_CLOCK_RATE / 2));
+		return (temp + (quarterX100 * 2));
+	}
+
+	*rem = (reminder - ((3 * VCO_REF_CLOCK_RATE) / 4));
+	return (temp + (quarterX100 * 3));
+}
+
+static uint32_t __calc_gcd(uint32_t num1, uint32_t num2)
+{
+	if (num2 != 0)
+		return __calc_gcd(num2, (num1 % num2));
+	else
+		return num1;
+}
+
+static void mdss_dsi_pll_12nm_calc_ssc(struct mdss_dsi_pll_config *pd,
+	struct dsi_pll_param *param)
+{
+	uint64_t multi_intX100 = 0, temp = 0;
+	uint32_t temp_rem1 = 0, temp_rem2 = 0;
+	const uint64_t power_2_17 = 131072, power_2_10 = 1024;
+
+	multi_intX100 = __mdss_dsi_get_multi_intX100(param->vco_freq,
+		&temp_rem1);
+
+	/* Calculation for mpll_ssc_peak_i */
+	temp = (multi_intX100 * pd->ssc_ppm * power_2_17);
+	temp = (temp / 100); /* 100 div for multi_intX100 */
+	param->mpll_ssc_peak_i =
+		(uint32_t) (temp / 1000000); /*10^6 for SSC PPM */
+
+	/* Calculation for mpll_stepsize_i */
+	param->mpll_stepsize_i = (uint32_t) ((param->mpll_ssc_peak_i *
+		pd->ssc_freq * power_2_10) / VCO_REF_CLOCK_RATE);
+
+	/* Calculation for mpll_mint_i */
+	param->mpll_mint_i = (uint32_t) (((multi_intX100 * 4) / 100) - 32);
+
+	/* Calculation for mpll_frac_den */
+	param->mpll_frac_den = (uint32_t) (VCO_REF_CLOCK_RATE /
+		__calc_gcd(param->vco_freq, VCO_REF_CLOCK_RATE));
+
+	/* Calculation for mpll_frac_quot_i */
+	temp = (temp_rem1 * power_2_17);
+	param->mpll_frac_quot_i = (uint32_t) (temp / VCO_REF_CLOCK_RATE);
+	temp_rem2 = temp % VCO_REF_CLOCK_RATE;
+
+	/* Calculation for mpll_frac_rem */
+	param->mpll_frac_rem = (uint32_t) (((uint64_t) temp_rem2 *
+		param->mpll_frac_den) / VCO_REF_CLOCK_RATE);
+
+	dprintf(SPEW, "mpll_ssc_peak_i=%d mpll_stepsize_i=%d mpll_mint_i=%d\n",
+		param->mpll_ssc_peak_i, param->mpll_stepsize_i,
+		param->mpll_mint_i);
+	dprintf(SPEW, "mpll_frac_den=%d mpll_frac_quot_i=%d mpll_frac_rem=%d\n",
+		param->mpll_frac_den, param->mpll_frac_quot_i,
+		param->mpll_frac_rem);
+}
+
+static void pll_db_commit_12nm_ssc(struct dsi_pll_param *param,
+					uint32_t phy_base)
+{
+	uint32_t data = 0;
+
+	writel_relaxed(0x27, phy_base + DSIPHY_SSC0);
+
+	data = (param->mpll_mint_i & 0xff);
+	writel_relaxed(data, phy_base + DSIPHY_SSC7);
+
+	data = ((param->mpll_mint_i & 0xff00) >> 8);
+	writel_relaxed(data, phy_base + DSIPHY_SSC8);
+
+	data = (param->mpll_ssc_peak_i & 0xff);
+	writel_relaxed(data, phy_base + DSIPHY_SSC1);
+
+	data = ((param->mpll_ssc_peak_i & 0xff00) >> 8);
+	writel_relaxed(data, phy_base + DSIPHY_SSC2);
+
+	data = ((param->mpll_ssc_peak_i & 0xf0000) >> 16);
+	writel_relaxed(data, phy_base + DSIPHY_SSC3);
+
+	data = (param->mpll_stepsize_i & 0xff);
+	writel_relaxed(data, phy_base + DSIPHY_SSC4);
+
+	data = ((param->mpll_stepsize_i & 0xff00) >> 8);
+	writel_relaxed(data, phy_base + DSIPHY_SSC5);
+
+	data = ((param->mpll_stepsize_i & 0x1f0000) >> 16);
+	writel_relaxed(data, phy_base + DSIPHY_SSC6);
+
+	data = (param->mpll_frac_quot_i & 0xff);
+	writel_relaxed(data, phy_base + DSIPHY_SSC10);
+
+	data = ((param->mpll_frac_quot_i & 0xff00) >> 8);
+	writel_relaxed(data, phy_base + DSIPHY_SSC11);
+
+	data = (param->mpll_frac_rem & 0xff);
+	writel_relaxed(data, phy_base + DSIPHY_SSC12);
+
+	data = ((param->mpll_frac_rem & 0xff00) >> 8);
+	writel_relaxed(data, phy_base + DSIPHY_SSC13);
+
+	data = (param->mpll_frac_den & 0xff);
+	writel_relaxed(data, phy_base + DSIPHY_SSC14);
+
+	data = ((param->mpll_frac_den & 0xff00) >> 8);
+	writel_relaxed(data, phy_base + DSIPHY_SSC15);
+}
+
+static void pll_db_commit_12nm(struct dsi_pll_param *param,
+	uint32_t phy_base, bool ssc_en)
+{
+	uint32_t data = 0;
+
+	writel_relaxed(0x01, phy_base + DSIPHY_CTRL0);
+	writel_relaxed(0x05, phy_base + DSIPHY_PLL_CTRL);
+	writel_relaxed(0x01, phy_base + DSIPHY_SLEWRATE_DDL_LOOP_CTRL);
+
+	data = ((param->hsfreqrange & 0x7f) | BIT(7));
+	writel_relaxed(data, phy_base + DSIPHY_HS_FREQ_RAN_SEL);
+
+	data = ((param->vco_cntrl & 0x3f) | BIT(6));
+	writel_relaxed(data, phy_base + DSIPHY_PLL_VCO_CTRL);
+
+	data = (param->osc_freq_target & 0x7f);
+	writel_relaxed(data, phy_base + DSIPHY_SLEWRATE_DDL_CYC_FRQ_ADJ_0);
+
+	data = ((param->osc_freq_target & 0xf80) >> 7);
+	writel_relaxed(data, phy_base + DSIPHY_SLEWRATE_DDL_CYC_FRQ_ADJ_1);
+	writel_relaxed(0x30, phy_base + DSIPHY_PLL_INPUT_LOOP_DIV_RAT_CTRL);
+
+	data = (param->m_div & 0x3f);
+	writel_relaxed(data, phy_base + DSIPHY_PLL_LOOP_DIV_RATIO_0);
+
+	data = ((param->m_div & 0xfc0) >> 6);
+	writel_relaxed(data, phy_base + DSIPHY_PLL_LOOP_DIV_RATIO_1);
+	writel_relaxed(0x60, phy_base + DSIPHY_PLL_INPUT_DIV_PLL_OVR);
+
+	data = (param->prop_cntrl & 0x3f);
+	writel_relaxed(data, phy_base + DSIPHY_PLL_PROP_CHRG_PUMP_CTRL);
+
+	data = (param->int_cntrl & 0x3f);
+	writel_relaxed(data, phy_base + DSIPHY_PLL_INTEG_CHRG_PUMP_CTRL);
+
+	data = ((param->gmp_cntrl & 0x3) << 4);
+	writel_relaxed(data, phy_base + DSIPHY_PLL_GMP_CTRL_DIG_TST);
+
+	data = ((param->cpbias_cntrl & 0x1) << 6) | BIT(4);
+	writel_relaxed(data, phy_base + DSIPHY_PLL_CHAR_PUMP_BIAS_CTRL);
+
+	data = ((param->gp_div_mux & 0x7) << 5) | 0x5;
+	writel_relaxed(data, phy_base + DSIPHY_PLL_CTRL);
+
+	data = (param->pixel_divhf & 0x7f);
+	writel_relaxed(data, phy_base + DSIPHY_SSC9);
+
+	writel_relaxed(0x03, phy_base + DSIPHY_PLL_ANA_PROG_CTRL);
+	writel_relaxed(0x50, phy_base + DSIPHY_PLL_ANA_TST_LOCK_ST_OVR_CTRL);
+	writel_relaxed(param->fsm_ovr_ctrl,
+		phy_base + DSIPHY_SLEWRATE_FSM_OVR_CTRL);
+	writel_relaxed(0x01, phy_base + DSIPHY_PLL_PHA_ERR_CTRL_0);
+	writel_relaxed(0x00, phy_base + DSIPHY_PLL_PHA_ERR_CTRL_1);
+	writel_relaxed(0xff, phy_base + DSIPHY_PLL_LOCK_FILTER);
+	writel_relaxed(0x03, phy_base + DSIPHY_PLL_UNLOCK_FILTER);
+	writel_relaxed(0x0c, phy_base + DSIPHY_PLL_PRO_DLY_RELOCK);
+	writel_relaxed(0x02, phy_base + DSIPHY_PLL_LOCK_DET_MODE_SEL);
+
+	if (ssc_en)
+		pll_db_commit_12nm_ssc(param, phy_base);
+
+	dmb(); /* make sure register committed */
+}
+
+static void mdss_dsi_phy_12nm_init(struct msm_panel_info *pinfo,
+	uint32_t phy_base)
+{
+	uint32_t *timing = pinfo->mipi.mdss_dsi_phy_db->timing;
+
+	/* Shutdown PHY initially */
+	writel_relaxed(0x09, phy_base + DSIPHY_SYS_CTRL);
+	/* CTRL0: CFG_CLK_EN */
+	writel_relaxed(0x1, phy_base + DSIPHY_CTRL0);
+
+	/* DSI PHY clock lane timings */
+	writel_relaxed((timing[0] | BIT(7)),
+		phy_base + DSIPHY_HSTX_CLKLANE_HS0STATE_TIM_CTRL);
+	writel_relaxed((timing[1] | BIT(6)),
+		phy_base + DSIPHY_HSTX_CLKLANE_TRALSTATE_TIM_CTRL);
+	writel_relaxed((timing[2] | BIT(6)),
+		phy_base + DSIPHY_HSTX_CLKLANE_CLKPOSTSTATE_TIM_CTRL);
+	writel_relaxed(timing[3],
+		phy_base + DSIPHY_HSTX_CLKLANE_REQSTATE_TIM_CTRL);
+	writel_relaxed((timing[7] | BIT(6) | BIT(7)),
+		phy_base + DSIPHY_HSTX_CLKLANE_EXITSTATE_TIM_CTRL);
+
+	/* DSI PHY data lane timings */
+	writel_relaxed((timing[4] | BIT(7)),
+		phy_base + DSIPHY_HSTX_DATALANE_HS0STATE_TIM_CTRL);
+	writel_relaxed((timing[5] | BIT(6)),
+		phy_base + DSIPHY_HSTX_DATALANE_TRAILSTATE_TIM_CTRL);
+	writel_relaxed(timing[6],
+		phy_base + DSIPHY_HSTX_DATALANE_REQSTATE_TIM_CTRL);
+	writel_relaxed((timing[7] | BIT(6) | BIT(7)),
+		phy_base + DSIPHY_HSTX_DATALANE_EXITSTATE_TIM_CTRL);
+
+	writel_relaxed(0x03, phy_base + DSIPHY_T_TA_GO_TIM_COUNT);
+	writel_relaxed(0x01, phy_base + DSIPHY_T_TA_SURE_TIM_COUNT);
+	writel_relaxed(0x85, phy_base + DSIPHY_REQ_DLY);
+
+	/* DSI lane control registers */
+	writel_relaxed(0x00, phy_base +
+		DSIPHY_HSTX_READY_DLY_DATA_REV_CTRL_LANE0);
+	writel_relaxed(0x00, phy_base +
+		DSIPHY_HSTX_READY_DLY_DATA_REV_CTRL_LANE1);
+	writel_relaxed(0x00, phy_base +
+		DSIPHY_HSTX_READY_DLY_DATA_REV_CTRL_LANE2);
+	writel_relaxed(0x00, phy_base +
+		DSIPHY_HSTX_READY_DLY_DATA_REV_CTRL_LANE3);
+	writel_relaxed(0x00, phy_base +
+		DSIPHY_HSTX_DATAREV_CTRL_CLKLANE);
+	dmb(); /* make sure DSI PHY registers are programmed */
+}
+
+void mdss_dsi_auto_pll_12nm_config(struct msm_panel_info *pinfo)
+{
+	struct mdss_dsi_pll_config *pd = pinfo->mipi.dsi_pll_config;
+	uint32_t phy_base = pinfo->mipi.phy_base;
+	uint32_t sphy_base = pinfo->mipi.sphy_base;
+	struct dsi_pll_param param = {0};
+
+	param.vco_freq = pd->vco_clock;
+	param.post_div_mux = pd->p_div_mux;
+	param.gp_div_mux = pd->gp_div_mux;
+	param.pixel_divhf = pd->divhf;
+
+	mdss_dsi_phy_12nm_init(pinfo, phy_base);
+	if (pinfo->mipi.dual_dsi)
+		mdss_dsi_phy_12nm_init(pinfo, sphy_base);
+
+	mdss_dsi_pll_12nm_calc_reg(&param);
+	if (pd->ssc_en)
+		mdss_dsi_pll_12nm_calc_ssc(pd, &param);
+	pll_db_commit_12nm(&param, phy_base, pd->ssc_en);
+}
+
+static uint32_t is_pll_locked_12nm(uint32_t phy_base)
+{
+	uint32_t cnt, status;
+
+	/* check pll lock */
+	for (cnt = 0; cnt < 50; cnt++) {
+		status = readl_relaxed(phy_base + DSIPHY_STAT0);
+		dprintf(SPEW, "%s: phy_base=%x cnt=%d status=%x\n",
+				__func__, phy_base, cnt, status);
+		status &= BIT(1);
+		if (status)
+			break;
+		udelay(500);
+	}
+
+	return status;
+}
+
+static void mdss_dsi_12nm_phy_hstx_drv_enable(uint32_t phy_base)
+{
+	uint32_t data = BIT(2) | BIT(3);
+
+	writel_relaxed(data, phy_base + DSIPHY_HSTX_DRIV_INDATA_CTRL_CLKLANE);
+	writel_relaxed(data, phy_base + DSIPHY_HSTX_DRIV_INDATA_CTRL_LANE0);
+	writel_relaxed(data, phy_base + DSIPHY_HSTX_DRIV_INDATA_CTRL_LANE1);
+	writel_relaxed(data, phy_base + DSIPHY_HSTX_DRIV_INDATA_CTRL_LANE2);
+	writel_relaxed(data, phy_base + DSIPHY_HSTX_DRIV_INDATA_CTRL_LANE3);
+	dmb(); /* make sure DSI PHY registers are programmed */
+}
+
+bool mdss_dsi_auto_pll_12nm_enable(struct msm_panel_info *pinfo)
+{
+	struct mdss_dsi_pll_config *pd = pinfo->mipi.dsi_pll_config;
+	uint32_t phy_base = pinfo->mipi.phy_base;
+	uint32_t sphy_base = pinfo->mipi.sphy_base;
+
+	writel_relaxed(0x49, phy_base + DSIPHY_SYS_CTRL);
+	dmb(); /* make sure register committed */
+	udelay(5); /* h/w recommended delay */
+	writel_relaxed(0xc9, phy_base + DSIPHY_SYS_CTRL);
+	dmb(); /* make sure register committed */
+	udelay(50); /* h/w recommended delay */
+
+	if (!is_pll_locked_12nm(phy_base)) {
+		dprintf(SPEW, "DSI PLL lock failed!\n");
+		return false;
+	}
+
+	dprintf(SPEW, "DSI PLL Locked!\n");
+
+	/* Enable DSI PLL output to DSI controller */
+	if (pd->ssc_en)
+		writel_relaxed(0x67, phy_base + DSIPHY_SSC0);
+	else
+		writel_relaxed(0x40, phy_base + DSIPHY_SSC0);
+
+	mdss_dsi_12nm_phy_hstx_drv_enable(phy_base);
+	if (pinfo->mipi.dual_dsi)
+		mdss_dsi_12nm_phy_hstx_drv_enable(sphy_base);
+	return true;
+}
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index 1321e9f..80a85bc 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2015, 2018, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -438,6 +438,7 @@
         struct mdss_dsi_phy_ctrl *pd;
 
 	if ((mipi->mdss_dsi_phy_db->pll_type == DSI_PLL_TYPE_THULIUM) ||
+		(mipi->mdss_dsi_phy_db->pll_type == DSI_PLL_TYPE_12NM) ||
 		(mdp_get_revision() == MDP_REV_304))
                 return;
 
@@ -495,6 +496,7 @@
 					mipi->sphy_base, mipi->reg_base);
 		break;
 	case DSI_PLL_TYPE_THULIUM:
+	case DSI_PLL_TYPE_12NM:
 		dprintf(SPEW, "phy is configured with PLL driver\n");
 		break;
 	case DSI_PLL_TYPE_28NM:
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index 82c7d88..3f0f003 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -636,7 +636,8 @@
 			$(LOCAL_DIR)/mipi_dsi.o \
 			$(LOCAL_DIR)/mipi_dsc.o \
 			$(LOCAL_DIR)/mipi_dsi_phy.o \
-			$(LOCAL_DIR)/mipi_dsi_autopll.o
+			$(LOCAL_DIR)/mipi_dsi_autopll.o \
+			$(LOCAL_DIR)/mipi_dsi_autopll_12nm.o
 endif
 
 ifeq ($(PLATFORM),msm8953)
diff --git a/target/msm8952/oem_panel.c b/target/msm8952/oem_panel.c
index 19369f8..01bccfd 100644
--- a/target/msm8952/oem_panel.c
+++ b/target/msm8952/oem_panel.c
@@ -63,6 +63,10 @@
 #include "include/panel_truly_wuxga_video.h"
 #include "include/panel_truly_720p_cmd.h"
 #include "include/panel_lead_fl10802_fwvga_video.h"
+#include "include/panel_hx8399c_fhd_pluse_video.h"
+#include "include/panel_hx8399c_hd_plus_video.h"
+#include "include/panel_nt35695b_truly_fhd_video.h"
+#include "include/panel_nt35695b_truly_fhd_cmd.h"
 
 /*---------------------------------------------------------------------------*/
 /* static panel selection variable                                           */
@@ -86,6 +90,10 @@
 	TRULY_WUXGA_VIDEO_PANEL,
 	TRULY_720P_CMD_PANEL,
 	LEAD_FL10802_FWVGA_VIDEO_PANEL,
+	HX8399C_FHD_PLUSE_VIDEO_PANEL,
+	HX8399C_HD_PLUS_VIDEO_PANEL,
+	NT35695B_TRULY_FHD_VIDEO_PANEL,
+	NT35695B_TRULY_FHD_CMD_PANEL,
 	UNKNOWN_PANEL
 };
 
@@ -116,6 +124,10 @@
 	{"truly_wuxga_video", TRULY_WUXGA_VIDEO_PANEL},
 	{"truly_720p_cmd", TRULY_720P_CMD_PANEL},
 	{"lead_fl10802_fwvga_video", LEAD_FL10802_FWVGA_VIDEO_PANEL},
+	{"hx8399c_fhd_plus_video", HX8399C_FHD_PLUSE_VIDEO_PANEL},
+	{"hx8399c_hd_plus_video", HX8399C_HD_PLUS_VIDEO_PANEL},
+	{"nt35695b_truly_fhd_video", NT35695B_TRULY_FHD_VIDEO_PANEL},
+	{"nt35695b_truly_fhd_cmd", NT35695B_TRULY_FHD_CMD_PANEL},
 };
 
 static uint32_t panel_id;
@@ -710,6 +722,145 @@
 		pinfo->mipi.signature = LEAD_FL10802_FWVGA_VIDEO_SIGNATURE;
 		pinfo->mipi.cmds_post_tg = 1;
 		break;
+	case HX8399C_FHD_PLUSE_VIDEO_PANEL:
+		panelstruct->paneldata    = &hx8399c_fhd_pluse_video_panel_data;
+		panelstruct->panelres     = &hx8399c_fhd_pluse_video_panel_res;
+		panelstruct->color        = &hx8399c_fhd_pluse_video_color;
+		panelstruct->videopanel   =
+				&hx8399c_fhd_pluse_video_video_panel;
+		panelstruct->commandpanel =
+				&hx8399c_fhd_pluse_video_command_panel;
+		panelstruct->state        = &hx8399c_fhd_pluse_video_state;
+		panelstruct->laneconfig   =
+				&hx8399c_fhd_pluse_video_lane_config;
+		panelstruct->paneltiminginfo
+				= &hx8399c_fhd_pluse_video_timing_info;
+		panelstruct->panelresetseq
+				= &hx8399c_fhd_pluse_video_panel_reset_seq;
+		panelstruct->backlightinfo = &hx8399c_fhd_pluse_video_backlight;
+		pinfo->labibb = &hx8399c_fhd_pluse_video_labibb;
+		pinfo->mipi.panel_on_cmds
+				= hx8399c_fhd_pluse_video_on_command;
+		pinfo->mipi.num_of_panel_on_cmds
+				= HX8399C_FHD_PLUSE_VIDEO_ON_COMMAND;
+		pinfo->mipi.panel_off_cmds
+				= hx8399c_fhd_pluse_video_off_command;
+		pinfo->mipi.num_of_panel_off_cmds
+				= HX8399C_FHD_PLUSE_VIDEO_OFF_COMMAND;
+		if (phy_db->pll_type == DSI_PLL_TYPE_12NM)
+			memcpy(phy_db->timing,
+				hx8399c_fhd_pluse_video_12nm_timings,
+				TIMING_SIZE_12NM);
+		else
+			memcpy(phy_db->timing, hx8399c_fhd_pluse_video_timings,
+				TIMING_SIZE);
+		pinfo->mipi.signature    = HX8399C_FHD_PLUSE_VIDEO_SIGNATURE;
+		break;
+	case HX8399C_HD_PLUS_VIDEO_PANEL:
+		panelstruct->paneldata    = &hx8399c_hd_plus_video_panel_data;
+		panelstruct->panelres     = &hx8399c_hd_plus_video_panel_res;
+		panelstruct->color        = &hx8399c_hd_plus_video_color;
+		panelstruct->videopanel   =
+				&hx8399c_hd_plus_video_video_panel;
+		panelstruct->commandpanel =
+				&hx8399c_hd_plus_video_command_panel;
+		panelstruct->state        = &hx8399c_hd_plus_video_state;
+		panelstruct->laneconfig   =
+				&hx8399c_hd_plus_video_lane_config;
+		panelstruct->paneltiminginfo
+				= &hx8399c_hd_plus_video_timing_info;
+		panelstruct->panelresetseq
+				= &hx8399c_hd_plus_video_panel_reset_seq;
+		panelstruct->backlightinfo = &hx8399c_hd_plus_video_backlight;
+		pinfo->labibb = &hx8399c_hd_plus_video_labibb;
+		pinfo->mipi.panel_on_cmds
+				= hx8399c_hd_plus_video_on_command;
+		pinfo->mipi.num_of_panel_on_cmds
+				= HX8399C_HD_PLUS_VIDEO_ON_COMMAND;
+		pinfo->mipi.panel_off_cmds
+				= hx8399c_hd_plus_video_off_command;
+		pinfo->mipi.num_of_panel_off_cmds
+				= HX8399C_HD_PLUS_VIDEO_OFF_COMMAND;
+		if (phy_db->pll_type == DSI_PLL_TYPE_12NM)
+			memcpy(phy_db->timing,
+				hx8399c_hd_plus_video_12nm_timings,
+				TIMING_SIZE_12NM);
+		else
+			memcpy(phy_db->timing, hx8399c_hd_plus_video_timings,
+				TIMING_SIZE);
+		pinfo->mipi.signature    = HX8399C_HD_PLUS_VIDEO_SIGNATURE;
+		pinfo->mipi.tx_eot_append = true;
+		break;
+	case NT35695B_TRULY_FHD_VIDEO_PANEL:
+		panelstruct->paneldata    = &nt35695b_truly_fhd_video_panel_data;
+		panelstruct->panelres     = &nt35695b_truly_fhd_video_panel_res;
+		panelstruct->color        = &nt35695b_truly_fhd_video_color;
+		panelstruct->videopanel   =
+				&nt35695b_truly_fhd_video_video_panel;
+		panelstruct->commandpanel =
+				&nt35695b_truly_fhd_video_command_panel;
+		panelstruct->state        = &nt35695b_truly_fhd_video_state;
+		panelstruct->laneconfig   =
+				&nt35695b_truly_fhd_video_lane_config;
+		panelstruct->paneltiminginfo
+				= &nt35695b_truly_fhd_video_timing_info;
+		panelstruct->panelresetseq
+				= &nt35695b_truly_fhd_video_panel_reset_seq;
+		panelstruct->backlightinfo = &nt35695b_truly_fhd_video_backlight;
+		pinfo->labibb = &nt35695b_truly_fhd_video_labibb;
+		pinfo->mipi.panel_on_cmds
+				= nt35695b_truly_fhd_video_on_command;
+		pinfo->mipi.num_of_panel_on_cmds
+				= NT35695B_TRULY_FHD_VIDEO_ON_COMMAND;
+		pinfo->mipi.panel_off_cmds
+				= nt35695b_truly_fhd_video_off_command;
+		pinfo->mipi.num_of_panel_off_cmds
+				= NT35695B_TRULY_FHD_VIDEO_OFF_COMMAND;
+		if (phy_db->pll_type == DSI_PLL_TYPE_12NM)
+			memcpy(phy_db->timing,
+				nt35695b_truly_fhd_video_12nm_timings,
+				TIMING_SIZE_12NM);
+		else
+			memcpy(phy_db->timing, nt35695b_truly_fhd_video_timings,
+				TIMING_SIZE);
+		pinfo->mipi.signature    = NT35695B_TRULY_FHD_VIDEO_SIGNATURE;
+		pinfo->mipi.tx_eot_append = true;
+		break;
+	case NT35695B_TRULY_FHD_CMD_PANEL:
+		panelstruct->paneldata    = &nt35695b_truly_fhd_cmd_panel_data;
+		panelstruct->panelres     = &nt35695b_truly_fhd_cmd_panel_res;
+		panelstruct->color        = &nt35695b_truly_fhd_cmd_color;
+		panelstruct->videopanel   =
+				&nt35695b_truly_fhd_cmd_video_panel;
+		panelstruct->commandpanel =
+				&nt35695b_truly_fhd_cmd_command_panel;
+		panelstruct->state        = &nt35695b_truly_fhd_cmd_state;
+		panelstruct->laneconfig   =
+				&nt35695b_truly_fhd_cmd_lane_config;
+		panelstruct->paneltiminginfo
+				= &nt35695b_truly_fhd_cmd_timing_info;
+		panelstruct->panelresetseq
+				= &nt35695b_truly_fhd_cmd_panel_reset_seq;
+		panelstruct->backlightinfo = &nt35695b_truly_fhd_cmd_backlight;
+		pinfo->labibb = &nt35695b_truly_fhd_cmd_labibb;
+		pinfo->mipi.panel_on_cmds
+				= nt35695b_truly_fhd_cmd_on_command;
+		pinfo->mipi.num_of_panel_on_cmds
+				= NT35695B_TRULY_FHD_CMD_ON_COMMAND;
+		pinfo->mipi.panel_off_cmds
+				= nt35695b_truly_fhd_cmd_off_command;
+		pinfo->mipi.num_of_panel_off_cmds
+				= NT35695B_TRULY_FHD_CMD_OFF_COMMAND;
+		if (phy_db->pll_type == DSI_PLL_TYPE_12NM)
+			memcpy(phy_db->timing,
+				nt35695b_truly_fhd_cmd_12nm_timings,
+				TIMING_SIZE_12NM);
+		else
+			memcpy(phy_db->timing, nt35695b_truly_fhd_cmd_timings,
+				TIMING_SIZE);
+		pinfo->mipi.signature    = NT35695B_TRULY_FHD_CMD_SIGNATURE;
+		pinfo->mipi.tx_eot_append = true;
+		break;
 	case UNKNOWN_PANEL:
 	default:
 		memset(panelstruct, 0, sizeof(struct panel_struct));
@@ -770,8 +921,12 @@
 	case HW_PLATFORM_MTP:
 		if (platform_is_msm8956())
 			panel_id = NT35597_WQXGA_DUALDSI_VIDEO_PANEL;
-        else if (platform_is_msm8917())
+		else if (platform_is_msm8917())
 			panel_id = TRULY_720P_VIDEO_PANEL;
+		else if (platform_is_sdm439())
+			panel_id = HX8399C_FHD_PLUSE_VIDEO_PANEL;
+		else if (platform_is_sdm429())
+			panel_id = HX8399C_HD_PLUS_VIDEO_PANEL;
 		else
 			panel_id = TRULY_1080P_VIDEO_PANEL;
 		break;
@@ -779,8 +934,12 @@
 	case HW_PLATFORM_RCM:
 		if (platform_is_msm8956())
 			panel_id = NT35597_WQXGA_DUALDSI_VIDEO_PANEL;
-        else if (platform_is_msm8917())
+		else if (platform_is_msm8917())
 			panel_id = TRULY_720P_VIDEO_PANEL;
+		else if (platform_is_sdm439())
+			panel_id = HX8399C_FHD_PLUSE_VIDEO_PANEL;
+		else if (platform_is_sdm429())
+			panel_id = HX8399C_HD_PLUS_VIDEO_PANEL;
 		else
 			panel_id = TRULY_1080P_VIDEO_PANEL;
 		break;
@@ -849,12 +1008,19 @@
 	 * Update all data structures after 'panel_init' label. Only panel
 	 * selection is supposed to happen before that.
 	 */
+	if (platform_is_sdm439() || platform_is_sdm429()) {
+		phy_db->pll_type = DSI_PLL_TYPE_12NM;
+		pinfo->lane_config = mdss_dsi_lane_config;
+		goto end;
+	}
+
 	if (platform_is_msm8956())
 		memcpy(panel_regulator_settings,
 			dcdc_regulator_settings_hpm, REGULATOR_SIZE);
 	else
 		memcpy(panel_regulator_settings,
 			dcdc_regulator_settings_lpm, REGULATOR_SIZE);
+end:
 	pinfo->pipe_type = MDSS_MDP_PIPE_TYPE_RGB;
 	return init_panel_data(panelstruct, pinfo, phy_db);
 }
diff --git a/target/msm8952/regulator.c b/target/msm8952/regulator.c
index 74b6fe0..ee08d30 100644
--- a/target/msm8952/regulator.c
+++ b/target/msm8952/regulator.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -68,6 +68,22 @@
 	},
 };
 
+static uint32_t ldo5[][11] = {
+	{
+		LDOA_RES_TYPE, 5,
+		KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
+		KEY_MICRO_VOLT, 4, 0,
+		KEY_CURRENT, 4, 0,
+	},
+
+	{
+		LDOA_RES_TYPE, 5,
+		KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
+		KEY_MICRO_VOLT, 4, 1800000,
+		KEY_CURRENT, 4, 150,
+	},
+};
+
 static uint32_t ldo6[][11]=
 {
 	{
@@ -105,14 +121,15 @@
 
 void regulator_enable(uint32_t enable)
 {
-	if(platform_is_msm8956())
-	{
+	if (platform_is_msm8956()) {
 		if (enable & REG_LDO1)
 			rpm_send_data(&ldo1[GENERIC_ENABLE][0], 36, RPM_REQUEST_TYPE);
 
-	}
-	else
-	{
+	} else if (platform_is_sdm439() || platform_is_sdm429()) {
+		if (enable & REG_LDO5)
+			rpm_send_data(&ldo5[GENERIC_ENABLE][0],
+				36, RPM_REQUEST_TYPE);
+	} else {
 		if (enable & REG_LDO2)
 			rpm_send_data(&ldo2[GENERIC_ENABLE][0], 36, RPM_REQUEST_TYPE);
 	}
@@ -126,14 +143,15 @@
 
 void regulator_disable(uint32_t enable)
 {
-	if(platform_is_msm8956())
-	{
+	if (platform_is_msm8956()) {
 		if (enable & REG_LDO1)
 			rpm_send_data(&ldo1[GENERIC_DISABLE][0], 36, RPM_REQUEST_TYPE);
 
-	}
-	else
-	{
+	} else if (platform_is_sdm439() || platform_is_sdm429()) {
+		if (enable & REG_LDO5)
+			rpm_send_data(&ldo5[GENERIC_DISABLE][0],
+				36, RPM_REQUEST_TYPE);
+	} else {
 		if (enable & REG_LDO2)
 			rpm_send_data(&ldo2[GENERIC_DISABLE][0], 36, RPM_REQUEST_TYPE);
 	}
diff --git a/target/msm8952/target_display.c b/target/msm8952/target_display.c
index 68f15f9..05e807e 100644
--- a/target/msm8952/target_display.c
+++ b/target/msm8952/target_display.c
@@ -82,6 +82,10 @@
   "msmgpio", 107, 3, 1, 0, 1
 };
 
+static struct gpio_pin bkl_en_gpio = {
+"pm8953", 4, 3, 1, 0, 1
+};
+
 #define VCO_DELAY_USEC 1000
 #define GPIO_STATE_LOW 0
 #define GPIO_STATE_HIGH 2
@@ -91,7 +95,9 @@
 #define DSI0_BASE_ADJUST -0x4000
 #define DSI0_PHY_BASE_ADJUST -0x4100
 #define DSI0_PHY_PLL_BASE_ADJUST -0x3900
+#define DSI0_12NM_PHY_PLL_BASE_ADJUST -0x3F00
 #define DSI0_PHY_REGULATOR_BASE_ADJUST -0x3C00
+#define DSI1_12NM_PHY_PLL_BASE_ADJUST -0x600
 
 static void mdss_dsi_uniphy_pll_sw_reset_8952(uint32_t pll_base)
 {
@@ -350,6 +356,11 @@
 		pll_data->is_center_spread = false;
 		pll_data->ssc_freq = 30000;
 		pll_data->ssc_ppm = 5000;
+	} else if (platform_is_sdm439() || platform_is_sdm429()) {
+		pll_data->ssc_en = true;
+		pll_data->is_center_spread = false;
+		pll_data->ssc_freq = 31500;
+		pll_data->ssc_ppm = 5000;
 	}
 
 	if (enable) {
@@ -367,10 +378,27 @@
 			return ret;
 		}
 
-		ret = mdss_dsi_pll_config(pinfo->mipi.pll_base,
-			pinfo->mipi.ctl_base, pll_data);
-		if (!ret)
-			dprintf(CRITICAL, "Not able to enable master pll\n");
+		gcc_dsi_lp_clock_enable(flags);
+
+		if (platform_is_sdm439() || platform_is_sdm429()) {
+			mdss_dsi_auto_pll_12nm_config(pinfo);
+
+			/*
+			 * enable clock/data lane in DSI controller
+			 * before enabling DSI PLL for 12nm PHY
+			 */
+			if (pinfo->lane_config)
+				pinfo->lane_config(pinfo);
+
+			ret = mdss_dsi_auto_pll_12nm_enable(pinfo);
+			if (!ret)
+				dprintf(CRITICAL, "unable to ON 12nm PLL\n");
+		} else {
+			ret = mdss_dsi_pll_config(pinfo->mipi.pll_base,
+				pinfo->mipi.ctl_base, pll_data);
+			if (!ret)
+				dprintf(CRITICAL, "unable to ON master pll\n");
+		}
 
 		if (platform_is_msm8956() && pinfo->mipi.dual_dsi &&
 			!platform_is_msm8976_v_1_1()) {
@@ -380,7 +408,7 @@
 				dprintf(CRITICAL, "Not able to enable second pll\n");
 		}
 
-		gcc_dsi_clocks_enable(flags, pinfo->mipi.use_dsi1_pll,
+		gcc_dsi_hs_clocks_enable(flags, pinfo->mipi.use_dsi1_pll,
 			pll_data->pclk_m, pll_data->pclk_n, pll_data->pclk_d);
 	} else if(!target_cont_splash_screen()) {
 		gcc_dsi_clocks_disable(flags);
@@ -410,6 +438,8 @@
 		reset_gpio.pin_id = 60;
 		bkl_gpio.pin_id = 98;
 		pinfo->mipi.use_enable_gpio = 0;
+	} else if (platform_is_sdm439() || platform_is_sdm429()) {
+		reset_gpio.pin_id = 60;
 	} else if ((hw_id == HW_PLATFORM_QRD) &&
 		   (hw_subtype == HW_PLATFORM_SUBTYPE_POLARIS)) {
 		enable_gpio.pin_id = 19;
@@ -425,11 +455,28 @@
 			gpio_set_dir(enable_gpio.pin_id, 2);
 		}
 
-		gpio_tlmm_config(bkl_gpio.pin_id, 0,
+		if (platform_is_sdm439() || platform_is_sdm429()) {
+			/* enable PM GPIO-4 for backlight enable */
+			struct pm8x41_gpio gpio_param = {
+			.direction = PM_GPIO_DIR_OUT,
+			.function = PM_GPIO_FUNC_HIGH,
+			.vin_sel = 0,   /* VIN_0 */
+			.pull = PM_GPIO_NO_PULL,
+			.output_buffer = PM_GPIO_OUT_CMOS,
+			.out_strength = PM_GPIO_OUT_DRIVE_HIGH,
+			};
+
+			dprintf(SPEW, "%s: gpio=%d enable=%d\n", __func__,
+				bkl_en_gpio.pin_id, enable);
+
+			pm8x41_gpio_config(bkl_en_gpio.pin_id, &gpio_param);
+		} else {
+			gpio_tlmm_config(bkl_gpio.pin_id, 0,
 				bkl_gpio.pin_direction, bkl_gpio.pin_pull,
 				bkl_gpio.pin_strength, bkl_gpio.pin_state);
 
-		gpio_set_dir(bkl_gpio.pin_id, 2);
+			gpio_set_dir(bkl_gpio.pin_id, 2);
+		}
 
 		gpio_tlmm_config(reset_gpio.pin_id, 0,
 				reset_gpio.pin_direction, reset_gpio.pin_pull,
@@ -554,7 +601,16 @@
 
 int target_display_get_base_offset(uint32_t base)
 {
-	if(platform_is_msm8956() || platform_is_msm8937() ||
+	if (platform_is_sdm439() || platform_is_sdm429()) {
+		if (base == MIPI_DSI0_BASE)
+			return DSI0_BASE_ADJUST;
+		else if (base == DSI0_PHY_BASE)
+			return DSI0_PHY_BASE_ADJUST;
+		else if (base == DSI0_PLL_BASE)
+			return DSI0_12NM_PHY_PLL_BASE_ADJUST;
+		else if (base == DSI1_PLL_BASE)
+			return DSI1_12NM_PHY_PLL_BASE_ADJUST;
+	} else if (platform_is_msm8956() || platform_is_msm8937() ||
 			platform_is_msm8917()) {
 		if (base == MIPI_DSI0_BASE)
 			return DSI0_BASE_ADJUST;
@@ -576,6 +632,8 @@
 
 	if (platform_is_msm8956())
 		ldo_num |= REG_LDO1;
+	else if (platform_is_sdm439() || platform_is_sdm429())
+		ldo_num |= REG_LDO5; /* LDO23 is enable by default */
 	else
 		ldo_num |= REG_LDO2;
 
@@ -600,7 +658,7 @@
 		}
 	} else {
 		/*
-		 * LDO1, LDO2 and LDO6 are shared with other subsystems.
+		 * LDO1, LDO2, LDO5 and LDO6 are shared with other subsystems.
 		 * Do not disable them.
 		 */
 		regulator_disable(REG_LDO17);