diff --git a/app/aboot/mdtp.c b/app/aboot/mdtp.c
index 578f4de..8ed312b 100644
--- a/app/aboot/mdtp.c
+++ b/app/aboot/mdtp.c
@@ -752,6 +752,7 @@
 static int mdtp_tzbsp_dec_verify_DIP(DIP_t *enc_dip, DIP_t *dec_dip, uint32_t *verified)
 {
 	unsigned char hash[HASH_LEN];
+	unsigned char buf[HASH_LEN], digest[HASH_LEN];
 	SHA256_CTX sha256_ctx;
 	int ret;
 
@@ -762,6 +763,9 @@
 	arch_clean_invalidate_cache_range((addr_t)enc_dip, sizeof(DIP_t));
 	arch_invalidate_cache_range((addr_t)dec_dip, sizeof(DIP_t));
 
+	/* workaround: Dummy call to hash_find prevents a boot loop when using the CE from TZ */
+	hash_find(buf, HASH_LEN, digest, CRYPTO_AUTH_ALG_SHA1);
+
 	ret = mdtp_cipher_dip_cmd((uint8_t*)enc_dip, sizeof(DIP_t),
 								(uint8_t*)dec_dip, sizeof(DIP_t),
 								DIP_DECRYPT);
@@ -795,6 +799,7 @@
 /* Encrypt a given DIP and calculate its integrity information */
 static int mdtp_tzbsp_enc_hash_DIP(DIP_t *dec_dip, DIP_t *enc_dip)
 {
+	unsigned char buf[HASH_LEN], digest[HASH_LEN];
 	SHA256_CTX sha256_ctx;
 	int ret;
 
@@ -808,6 +813,9 @@
 	arch_clean_invalidate_cache_range((addr_t)dec_dip, sizeof(DIP_t));
 	arch_invalidate_cache_range((addr_t)enc_dip, sizeof(DIP_t));
 
+	/* workaround: Dummy call to hash_find prevents a boot loop when using the CE from TZ */
+	hash_find(buf, HASH_LEN, digest, CRYPTO_AUTH_ALG_SHA1);
+
 	ret = mdtp_cipher_dip_cmd((uint8_t*)dec_dip, sizeof(DIP_t),
 								(uint8_t*)enc_dip, sizeof(DIP_t),
 								DIP_ENCRYPT);
diff --git a/app/mmutest/mmu_test.c b/app/mmutest/mmu_test.c
index 216e73b..849a9e6 100644
--- a/app/mmutest/mmu_test.c
+++ b/app/mmutest/mmu_test.c
@@ -31,33 +31,62 @@
 #include <arch/arm/mmu.h>
 #include <mmu.h>
 #include <string.h>
+#include <smem.h>
 
 /* COMMON memory - cacheable, write through */
 #define COMMON_MEMORY       (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
                            MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
 
 #define MB (1024 * 1024)
-static mmu_section_t ramdump_mmu_section_table[] =
+static mmu_section_t ramdump_mmu_section_table_4gb[] =
 {
   /*        Physical addr,    Virtual addr,     Mapping type ,              Size (in MB),            Flags */
 	{    0xC0000000,        0xC0000000,       MMU_L2_NS_SECTION_MAPPING,  512,            COMMON_MEMORY},
 	{    0x100000000,       0xC0000000,       MMU_L2_NS_SECTION_MAPPING,  1024,            COMMON_MEMORY},
+	/* This entry is 484 MB because the hyp uses last 28MB for page tables */
 	{    0x140000000,       0xC0000000,       MMU_L2_NS_SECTION_MAPPING,  484,            COMMON_MEMORY},
 };
 
-uint32_t vaddr[] = {0xc2300000, 0xcd000000, 0xde000000};
-uint64_t paddr[] = {0xc2300000, 0x10d000000, 0x15e000000};
+static mmu_section_t ramdump_mmu_section_table_3gb[] =
+{
+  /*        Physical addr,    Virtual addr,     Mapping type ,              Size (in MB),            Flags */
+	{    0x20000000,        0x20000000,       MMU_L2_NS_SECTION_MAPPING,  512,            COMMON_MEMORY},
+	{    0xC0000000,        0xC0000000,       MMU_L2_NS_SECTION_MAPPING,  484,            COMMON_MEMORY},
+};
+uint32_t vaddr_4gb[] = {0xc2300000, 0xcd000000, 0xde000000};
+uint64_t paddr_4gb[] = {0xc2300000, 0x10d000000, 0x15e000000};
+
+uint32_t vaddr_3gb[] = {0x23000000, 0xcd000000, 0xde000000};
+uint64_t paddr_3gb[] = {0x23000000, 0xcd000000, 0xde000000};
 
 void ramdump_table_map()
 {
 	uint32_t i, j;
-	uint32_t table_sz = ARRAY_SIZE(ramdump_mmu_section_table);
+	uint32_t table_sz = 0;
 	char *ptr = NULL;
 	bool pass_access = true;
 	bool pass_conversion = true;
 	uint64_t paddr_v;
 	uint32_t vaddr_v;
+	uint32_t *vaddr = NULL;
+	uint64_t *paddr = NULL;
+	mmu_section_t *ramdump_mmu_section_table = NULL;
 
+
+	if (smem_get_ddr_size() == MEM_4GB)
+	{
+		vaddr = vaddr_4gb;
+		paddr = paddr_4gb;
+		ramdump_mmu_section_table = ramdump_mmu_section_table_4gb;
+		table_sz = ARRAY_SIZE(ramdump_mmu_section_table_4gb);
+	}
+	else if (smem_get_ddr_size() == MEM_3GB)
+	{
+		vaddr = vaddr_3gb;
+		paddr = paddr_3gb;
+		ramdump_mmu_section_table = ramdump_mmu_section_table_3gb;
+		table_sz = ARRAY_SIZE(ramdump_mmu_section_table_3gb);
+	}
 	for (i = 0 ; i < table_sz; i++)
 	{
 		arm_mmu_map_entry(&ramdump_mmu_section_table[i]);
@@ -69,22 +98,22 @@
 			pass_conversion = false;
 		ptr = (char *)(uintptr_t)ramdump_mmu_section_table[i].vaddress;
 
-		for (j = 0 ; j < (ramdump_mmu_section_table[i].size * MB)/5; j++)
+		for (j = 0 ; j < (ramdump_mmu_section_table[i].size * MB)/6; j++)
 		{
-			strcpy(ptr, "hello");
-			ptr+=5;
+			strlcpy(ptr, "hello", 6);
+			ptr+=6;
 		}
 
 		ptr = (char *)(uintptr_t)ramdump_mmu_section_table[i].vaddress;
 
-		for (j = 0 ; j < (ramdump_mmu_section_table[i].size * MB)/5; j++)
+		for (j = 0 ; j < (ramdump_mmu_section_table[i].size * MB)/6; j++)
 		{
 			if (memcmp((void *)ptr, "hello", 5))
 			{
 				pass_access = false;
 				break;
 			}
-			ptr+=5;
+			ptr+=6;
 		}
 		if (pass_access)
 			dprintf(CRITICAL, "LAPE TEST PASS for addr: 0x%llx\n", ramdump_mmu_section_table[i].paddress);
diff --git a/dev/gcdb/display/gcdb_autopll.c b/dev/gcdb/display/gcdb_autopll.c
index c37fad3..1d2db47 100755
--- a/dev/gcdb/display/gcdb_autopll.c
+++ b/dev/gcdb/display/gcdb_autopll.c
@@ -41,12 +41,18 @@
 {
 	uint32_t h_period = 0, v_period = 0;
 	uint32_t width = pinfo->xres;
+	struct dsc_desc *dsc = NULL;
 
 	if (pinfo->mipi.dual_dsi)
 		width /= 2;
 
-	if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio)
-		width /= pinfo->fbc.comp_ratio;
+	if (pinfo->compression_mode == COMPRESSION_DSC) {
+		dsc = &pinfo->dsc;
+		width = dsc->pclk_per_line;
+	} else if (pinfo->compression_mode == COMPRESSION_FBC) {
+		if (pinfo->fbc.comp_ratio)
+			width /= pinfo->fbc.comp_ratio;
+	}
 
 	h_period = width + pinfo->lcdc.h_back_porch +
 		pinfo->lcdc.h_front_porch + pinfo->lcdc.h_pulse_width +
diff --git a/dev/gcdb/display/include/panel.h b/dev/gcdb/display/include/panel.h
index f75850c..c9aee8b 100755
--- a/dev/gcdb/display/include/panel.h
+++ b/dev/gcdb/display/include/panel.h
@@ -207,4 +207,19 @@
 	uint32_t max_pred_err;
 };
 
+struct dsc_parameters {
+	uint32_t major;
+	uint32_t minor;
+	uint32_t pps_id;
+	uint32_t slice_height;
+	uint32_t slice_width;
+	uint32_t bpp;		/* target bpp */
+	uint32_t bpc;		/* target bpc, byte per component */
+	uint32_t slice_per_pkt;
+	uint32_t block_prediction;
+	uint32_t ich_reset_override;
+	uint32_t ich_reset_value;
+	uint32_t data_path_mode;
+};
+
 #endif /*_PANEL_H_ */
diff --git a/dev/gcdb/display/include/panel_adv7533_1080p60.h b/dev/gcdb/display/include/panel_adv7533_1080p60.h
index ceba5ce..b5504c1 100755
--- a/dev/gcdb/display/include/panel_adv7533_1080p60.h
+++ b/dev/gcdb/display/include/panel_adv7533_1080p60.h
@@ -37,7 +37,7 @@
 /* Panel configuration                                                       */
 /*---------------------------------------------------------------------------*/
 static struct panel_config adv7533_1080p_video_panel_data = {
-	"qcom,mdss_dsi_adv7533_1080p60_video", "dsi:0:", "qcom,mdss-dsi-panel",
+	"qcom,mdss_dsi_adv7533_1080p", "dsi:0:", "qcom,mdss-dsi-panel",
 	10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
 };
 
diff --git a/dev/gcdb/display/include/panel_adv7533_720p60.h b/dev/gcdb/display/include/panel_adv7533_720p60.h
index c56971f..568bf63 100644
--- a/dev/gcdb/display/include/panel_adv7533_720p60.h
+++ b/dev/gcdb/display/include/panel_adv7533_720p60.h
@@ -38,7 +38,7 @@
 /* Panel configuration                                                       */
 /*---------------------------------------------------------------------------*/
 static struct panel_config adv7533_720p_video_panel_data = {
-	"qcom,mdss_dsi_adv7533_720p60_video", "dsi:0:", "qcom,mdss-dsi-panel",
+	"qcom,mdss_dsi_adv7533_720p", "dsi:0:", "qcom,mdss-dsi-panel",
 	10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
 };
 
diff --git a/dev/gcdb/display/include/panel_nt35597_wqxga_dsc_cmd.h b/dev/gcdb/display/include/panel_nt35597_wqxga_dsc_cmd.h
new file mode 100644
index 0000000..6c7df16
--- /dev/null
+++ b/dev/gcdb/display/include/panel_nt35597_wqxga_dsc_cmd.h
@@ -0,0 +1,339 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  * Neither the name of The Linux Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PANEL_NT35597_WQXGA_DSC_CMD_H_
+#define _PANEL_NT35597_WQXGA_DSC_CMD_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files                                                              */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration                                                       */
+/*---------------------------------------------------------------------------*/
+static struct panel_config nt35597_wqxga_dsc_cmd_panel_data = {
+	"qcom,mdss_dsi_nt35597_dsc_wqxga_cmd", "dsi:1:", "qcom,mdss-dsi-panel",
+	10, 1, "DISPLAY_2", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 32, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution                                                          */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution nt35597_wqxga_dsc_cmd_panel_res = {
+	1440, 2560, 100, 32, 16, 0, 8, 7, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information                                                   */
+/*---------------------------------------------------------------------------*/
+static struct color_info nt35597_wqxga_dsc_cmd_color = {
+	24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information                                          */
+/*---------------------------------------------------------------------------*/
+static char nt35597_wqxga_dsc_cmd_on_cmd0[] = {
+	0xff, 0x10, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd1[] = {
+	0xfb, 0x01, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd2[] = {
+	0xba, 0x03, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd3[] = {
+	0xe5, 0x01, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd4[] = {
+	0xb0, 0x03, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd5[] = {
+	0xff, 0x28, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd6[] = {
+	0x7a, 0x02, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd7[] = {
+	0xfb, 0x01, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd8[] = {
+	0xff, 0x10, 0x15, 0x80
+};
+
+#ifdef USE_MANUFACTUR_DSC_CMD
+static char nt35597_wqxga_dsc_cmd_on_cmd9[] = {
+	0x11, 0x00, 0x39, 0xC0,
+	0xC1, 0x09, 0x20, 0x00,
+	0x10, 0x02, 0x00, 0x02,
+	0x68, 0x01, 0xBB, 0x00,
+	0x0A, 0x06, 0x67, 0x04,
+	0xC5, 0xff, 0xff, 0xff,
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd10[] = {
+	0x03, 0x00, 0x39, 0xC0,
+	0xc2, 0x10, 0xf0, 0xff,
+};
+#endif
+
+
+static char nt35597_wqxga_dsc_cmd_on_cmd11[] = {
+	0xfb, 0x01, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd12[] = {
+	0xc0, 0x03, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd13[] = {
+	0xbb, 0x10, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd14[] = {
+	0x35, 0x00, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd15[] = {
+	0xff, 0xe0, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd16[] = {
+	0xfb, 0x01, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd17[] = {
+	0x6b, 0x3d, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd18[] = {
+	0x6c, 0x3d, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd19[] = {
+	0x6d, 0x3d, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd20[] = {
+	0x6e, 0x3d, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd21[] = {
+	0x6f, 0x3d, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd22[] = {
+	0x35, 0x02, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd23[] = {
+	0x36, 0x72, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd24[] = {
+	0x37, 0x10, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd25[] = {
+	0x08, 0xc0, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd26[] = {
+	0xff, 0x24, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd27[] = {
+	0xfb, 0x01, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd28[] = {
+	0xc6, 0x06, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd29[] = {
+	0xff, 0x10, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd30[] = {
+	0x11, 0x00, 0x05, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd31[] = {
+	0x29, 0x00, 0x05, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_on_cmd32[] = {
+	0x01, 0x00, 0x07, 0x80
+};
+
+static struct mipi_dsi_cmd nt35597_wqxga_dsc_cmd_on_command[] = {
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd0, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd1, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd2, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd3, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd4, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd5, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd6, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd7, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd8, 0x10},
+#ifdef USE_MANUFACTUR_DSC_CMD
+	{0x18, nt35597_wqxga_dsc_cmd_on_cmd9, 0x10},
+	{0x8, nt35597_wqxga_dsc_cmd_on_cmd10, 0x10},
+#endif
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd11, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd12, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd13, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd14, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd15, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd16, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd17, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd18, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd19, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd20, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd21, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd22, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd23, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd24, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd25, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd26, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd27, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd28, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd29, 0x10},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd30, 0x78},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd31, 0x78},
+	{0x4, nt35597_wqxga_dsc_cmd_on_cmd32, 0x10},
+};
+
+#ifdef USE_MANUFACTUR_DSC_CMD
+#define NT35597_WQXGA_DSC_CMD_ON_COMMAND 33
+#else
+#define NT35597_WQXGA_DSC_CMD_ON_COMMAND 31
+#endif
+
+
+static char nt35597_wqxga_dsc_cmd_off_cmd0[] = {
+	0x28, 0x00, 0x05, 0x80
+};
+
+static char nt35597_wqxga_dsc_cmd_off_cmd1[] = {
+	0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd nt35597_wqxga_dsc_cmd_off_command[] = {
+	{0x4, nt35597_wqxga_dsc_cmd_off_cmd0, 0x32},
+	{0x4, nt35597_wqxga_dsc_cmd_off_cmd1, 0x78}
+};
+
+#define NT35597_WQXGA_DSC_CMD_OFF_COMMAND 2
+
+static struct command_state nt35597_wqxga_dsc_cmd_state = {
+	0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information                                            */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info nt35597_wqxga_dsc_cmd_command_panel = {
+	1, 1, 1, 0, 0, 0x2c, 0, 0, 0, 1, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information                                              */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info nt35597_wqxga_dsc_cmd_video_panel = {
+	0, 0, 0, 0, 1, 1, 1, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration                                                        */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration nt35597_wqxga_dsc_cmd_lane_config = {
+	4, 0, 1, 1, 1, 1, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing                                                              */
+/*---------------------------------------------------------------------------*/
+static const uint32_t nt35597_wqxga_dsc_cmd_timings[] = {
+	0xe2, 0x36, 0x24, 0x00, 0x66, 0x6a, 0x28, 0x38,  0x2a, 0x03, 0x04, 0x00
+};
+
+static const uint32_t nt35597_wqxga_dsc_thulium_cmd_timings[] = {
+	0x20, 0x1d, 0x05, 0x07, 0x03, 0x03, 0x4, 0xa0,
+	0x20, 0x1d, 0x05, 0x07, 0x03, 0x03, 0x4, 0xa0,
+	0x20, 0x1d, 0x05, 0x07, 0x03, 0x03, 0x4, 0xa0,
+	0x20, 0x1d, 0x05, 0x07, 0x03, 0x03, 0x4, 0xa0,
+	0x20, 0x12, 0x05, 0x06, 0x03, 0x13, 0x4, 0xa0,
+};
+
+static struct panel_timing nt35597_wqxga_dsc_cmd_timing_info = {
+	0x0, 0x04, 0x0b, 0x24
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence                                                      */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence nt35597_wqxga_dsc_cmd_reset_seq = {
+	{1, 0, 1, }, {20, 20, 50, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting                                                         */
+/*---------------------------------------------------------------------------*/
+static struct backlight nt35597_wqxga_dsc_cmd_backlight = {
+	1, 1, 4095, 100, 1, "PMIC_8941"		/* BL_WLED */
+};
+
+static struct labibb_desc nt35597_wqxga_dsc_cmd_labibb = {
+	0, 1, 5500000, 5500000, 5500000, 5500000, 3, 3, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Dynamic fps supported frequencies by panel                                */
+/*---------------------------------------------------------------------------*/
+static const struct dfps_panel_info nt35597_wqxga_dsc_cmd_dfps = {
+	1, 8, {53, 54, 55, 56, 57, 58, 59, 60}
+};
+
+/*---------------------------------------------------------------------------*/
+/* DSC									     */
+/*---------------------------------------------------------------------------*/
+static const struct dsc_parameters nt35597_wqxga_dsc_cmd_paras = {
+	1, 0, 0, 16, 720, 8, 8, 2, 1, 0, 0, 0
+};
+
+#endif
diff --git a/dev/gcdb/display/include/panel_nt35597_wqxga_dsc_video.h b/dev/gcdb/display/include/panel_nt35597_wqxga_dsc_video.h
new file mode 100644
index 0000000..c699219
--- /dev/null
+++ b/dev/gcdb/display/include/panel_nt35597_wqxga_dsc_video.h
@@ -0,0 +1,322 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  * Neither the name of The Linux Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PANEL_NT35597_WQXGA_DSC_VIDEO_H_
+#define _PANEL_NT35597_WQXGA_DSC_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files                                                              */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration                                                       */
+/*---------------------------------------------------------------------------*/
+static struct panel_config nt35597_wqxga_dsc_video_panel_data = {
+	"qcom,mdss_dsi_nt35597_dsc_wqxga_video", "dsi:1:", "qcom,mdss-dsi-panel",
+	10, 0, "DISPLAY_2", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 32, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution                                                          */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution nt35597_wqxga_dsc_video_panel_res = {
+	1440, 2560, 100, 32, 16, 0, 8, 7, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information                                                   */
+/*---------------------------------------------------------------------------*/
+static struct color_info nt35597_wqxga_dsc_video_color = {
+	24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information                                          */
+/*---------------------------------------------------------------------------*/
+static char nt35597_wqxga_dsc_video_on_cmd0[] = {
+	0xff, 0x10, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd1[] = {
+	0xfb, 0x01, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd2[] = {
+	0xba, 0x03, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd3[] = {
+	0xe5, 0x01, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd4[] = {
+	0xb0, 0x03, 0x15, 0x80
+};
+
+
+static char nt35597_wqxga_dsc_video_on_cmd5[] = {
+	0x06, 0x00, 0x39, 0xC0,
+	0x3B, 0x03, 0x08, 0x08,
+	0x2e, 0x64, 0xff, 0xff,
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd6[] = {
+	0xff, 0x28, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd7[] = {
+	0x7a, 0x02, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd8[] = {
+	0xfb, 0x01, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd9[] = {
+	0xff, 0x10, 0x15, 0x80
+};
+
+#ifdef USE_MANUFACTUR_DSC_CMD
+static char nt35597_wqxga_dsc_video_on_cmd10[] = {
+	0x11, 0x00, 0x39, 0xC0,
+	0xC1, 0x09, 0x20, 0x00,
+	0x10, 0x02, 0x00, 0x02,
+	0x68, 0x01, 0xBB, 0x00,
+	0x0A, 0x06, 0x67, 0x04,
+	0xC5, 0xff, 0xff, 0xff,
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd11[] = {
+	0x03, 0x00, 0x39, 0xC0,
+	0xc2, 0x10, 0xf0, 0xff,
+};
+#endif
+
+static char nt35597_wqxga_dsc_video_on_cmd12[] = {
+	0xfb, 0x01, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd13[] = {
+	0xc0, 0x03, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd14[] = {
+	0xbb, 0x03, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd15[] = {
+	0xff, 0xe0, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd16[] = {
+	0xfb, 0x01, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd17[] = {
+	0x6b, 0x3d, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd18[] = {
+	0x6c, 0x3d, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd19[] = {
+	0x6d, 0x3d, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd20[] = {
+	0x6e, 0x3d, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd21[] = {
+	0x6f, 0x3d, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd22[] = {
+	0x35, 0x02, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd23[] = {
+	0x36, 0x72, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd24[] = {
+	0x37, 0x10, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd25[] = {
+	0x08, 0xc0, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd26[] = {
+	0xff, 0x10, 0x15, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd27[] = {
+	0x11, 0x00, 0x05, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd28[] = {
+	0x29, 0x00, 0x05, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_on_cmd29[] = {
+	0x01, 0x00, 0x07, 0x80
+};
+
+static struct mipi_dsi_cmd nt35597_wqxga_dsc_video_on_command[] = {
+	{0x4, nt35597_wqxga_dsc_video_on_cmd0, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd1, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd2, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd3, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd4, 0x10},
+	{0xc, nt35597_wqxga_dsc_video_on_cmd5, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd6, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd7, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd8, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd9, 0x10},
+#ifdef USE_MANUFACTUR_DSC_CMD
+	{0x18, nt35597_wqxga_dsc_video_on_cmd10, 0x10},
+	{0x8, nt35597_wqxga_dsc_video_on_cmd11, 0x10},
+#endif
+	{0x4, nt35597_wqxga_dsc_video_on_cmd12, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd13, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd14, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd15, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd16, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd17, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd18, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd19, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd20, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd21, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd22, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd23, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd24, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd25, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd26, 0x10},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd27, 0x100},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd28, 0x100},
+	{0x4, nt35597_wqxga_dsc_video_on_cmd29, 0x10},
+};
+
+#ifdef USE_MANUFACTUR_DSC_CMD
+#define NT35597_WQXGA_DSC_VIDEO_ON_COMMAND 30
+#else
+#define NT35597_WQXGA_DSC_VIDEO_ON_COMMAND 28
+#endif
+
+
+static char nt35597_wqxga_dsc_video_off_cmd0[] = {
+	0x28, 0x00, 0x05, 0x80
+};
+
+static char nt35597_wqxga_dsc_video_off_cmd1[] = {
+	0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd nt35597_wqxga_dsc_video_off_command[] = {
+	{0x4, nt35597_wqxga_dsc_video_off_cmd0, 0x32},
+	{0x4, nt35597_wqxga_dsc_video_off_cmd1, 0x78}
+};
+
+#define NT35597_WQXGA_DSC_VIDEO_OFF_COMMAND 2
+
+static struct command_state nt35597_wqxga_dsc_video_state = {
+	0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information                                            */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info nt35597_wqxga_dsc_video_command_panel = {
+	1, 1, 1, 0, 0, 0x2c, 0, 0, 0, 1, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information                                              */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info nt35597_wqxga_dsc_video_video_panel = {
+	0, 0, 0, 0, 1, 1, 1, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration                                                        */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration nt35597_wqxga_dsc_video_lane_config = {
+	4, 0, 1, 1, 1, 1, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing                                                              */
+/*---------------------------------------------------------------------------*/
+static const uint32_t nt35597_wqxga_dsc_thulium_video_timings[] = {
+	0x20, 0x1d, 0x05, 0x07, 0x03, 0x03, 0x4, 0xa0,
+	0x20, 0x1d, 0x05, 0x07, 0x03, 0x03, 0x4, 0xa0,
+	0x20, 0x1d, 0x05, 0x07, 0x03, 0x03, 0x4, 0xa0,
+	0x20, 0x1d, 0x05, 0x07, 0x03, 0x03, 0x4, 0xa0,
+	0x20, 0x12, 0x05, 0x06, 0x03, 0x13, 0x4, 0xa0,
+};
+
+static struct panel_timing nt35597_wqxga_dsc_video_timing_info = {
+	0x0, 0x04, 0x0b, 0x24
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence                                                      */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence nt35597_wqxga_dsc_video_reset_seq = {
+	{1, 0, 1, }, {20, 20, 50, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting                                                         */
+/*---------------------------------------------------------------------------*/
+static struct backlight nt35597_wqxga_dsc_video_backlight = {
+	1, 1, 4095, 100, 1, "PMIC_8941"		/* BL_WLED */
+};
+
+static struct labibb_desc nt35597_wqxga_dsc_video_labibb = {
+	0, 1, 5500000, 5500000, 5500000, 5500000, 3, 3, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Dynamic fps supported frequencies by panel                                */
+/*---------------------------------------------------------------------------*/
+static const struct dfps_panel_info nt35597_wqxga_dsc_video_dfps = {
+	1, 8, {53, 54, 55, 56, 57, 58, 59, 60}
+};
+
+/*---------------------------------------------------------------------------*/
+/* DSC									     */
+/*---------------------------------------------------------------------------*/
+static const struct dsc_parameters nt35597_wqxga_dsc_video_paras = {
+	1, 0, 0, 16, 720, 8, 8, 2, 1, 0, 0, 0
+};
+
+#endif
diff --git a/dev/gcdb/display/panel_display.c b/dev/gcdb/display/panel_display.c
index 4ea95d1..1c0a82a 100755
--- a/dev/gcdb/display/panel_display.c
+++ b/dev/gcdb/display/panel_display.c
@@ -243,30 +243,52 @@
 	pinfo->mipi.t_clk_pre = pstruct->paneltiminginfo->tclk_pre;
 	pinfo->mipi.mdp_trigger = pstruct->paneltiminginfo->dsi_mdp_trigger;
 	pinfo->mipi.dma_trigger = pstruct->paneltiminginfo->dsi_dma_trigger;
+	pinfo->fbc.comp_ratio = 1;
 
-	pinfo->fbc.enabled = pstruct->fbcinfo.enabled;
-	if (pinfo->fbc.enabled) {
+	if (pinfo->compression_mode == COMPRESSION_DSC) {
+		struct dsc_desc *dsc = NULL;
+
+		pinfo->dsc.major = pstruct->dsc_paras.major;
+		pinfo->dsc.minor = pstruct->dsc_paras.minor;
+		pinfo->dsc.pps_id = pstruct->dsc_paras.pps_id;
+		pinfo->dsc.slice_height = pstruct->dsc_paras.slice_height;
+		pinfo->dsc.slice_width = pstruct->dsc_paras.slice_width;
+		pinfo->dsc.bpp = pstruct->dsc_paras.bpp;
+		pinfo->dsc.bpc = pstruct->dsc_paras.bpc;
+		pinfo->dsc.slice_per_pkt = pstruct->dsc_paras.slice_per_pkt;
+		pinfo->dsc.ich_reset_value = pstruct->dsc_paras.ich_reset_value;
+		pinfo->dsc.ich_reset_override = pstruct->dsc_paras.ich_reset_override;
+		pinfo->dsc.block_pred_enable = pstruct->dsc_paras.block_prediction;
+		pinfo->dsc.enable_422 = 0;
+		pinfo->dsc.convert_rgb = 1;
+		pinfo->dsc.vbr_enable = 0;
+
+		dsc = &pinfo->dsc;
+		if (dsc) {
+			if (dsc->parameter_calc)
+                                dsc->parameter_calc(pinfo);
+                }
+	} else if (pinfo->compression_mode == COMPRESSION_FBC) {
 		pinfo->fbc.enabled = pstruct->fbcinfo.enabled;
-		pinfo->fbc.comp_ratio= pstruct->fbcinfo.comp_ratio;
-		pinfo->fbc.comp_mode = pstruct->fbcinfo.comp_mode;
-		pinfo->fbc.qerr_enable = pstruct->fbcinfo.qerr_enable;
-		pinfo->fbc.cd_bias = pstruct->fbcinfo.cd_bias;
-		pinfo->fbc.pat_enable = pstruct->fbcinfo.pat_enable;
-		pinfo->fbc.vlc_enable = pstruct->fbcinfo.vlc_enable;
-		pinfo->fbc.bflc_enable = pstruct->fbcinfo.bflc_enable;
-		pinfo->fbc.line_x_budget = pstruct->fbcinfo.line_x_budget;
-		pinfo->fbc.block_x_budget = pstruct->fbcinfo.block_x_budget;
-		pinfo->fbc.block_budget = pstruct->fbcinfo.block_budget;
-		pinfo->fbc.lossless_mode_thd = pstruct->fbcinfo.lossless_mode_thd;
-		pinfo->fbc.lossy_mode_thd = pstruct->fbcinfo.lossy_mode_thd;
-		pinfo->fbc.lossy_rgb_thd = pstruct->fbcinfo.lossy_rgb_thd;
-		pinfo->fbc.lossy_mode_idx = pstruct->fbcinfo.lossy_mode_idx;
-		pinfo->fbc.slice_height = pstruct->fbcinfo.slice_height;
-		pinfo->fbc.pred_mode = pstruct->fbcinfo.pred_mode;
-		pinfo->fbc.max_pred_err = pstruct->fbcinfo.max_pred_err;
-
-	} else {
-		pinfo->fbc.comp_ratio = 1;
+		if (pinfo->fbc.enabled) {
+			pinfo->fbc.comp_ratio= pstruct->fbcinfo.comp_ratio;
+			pinfo->fbc.comp_mode = pstruct->fbcinfo.comp_mode;
+			pinfo->fbc.qerr_enable = pstruct->fbcinfo.qerr_enable;
+			pinfo->fbc.cd_bias = pstruct->fbcinfo.cd_bias;
+			pinfo->fbc.pat_enable = pstruct->fbcinfo.pat_enable;
+			pinfo->fbc.vlc_enable = pstruct->fbcinfo.vlc_enable;
+			pinfo->fbc.bflc_enable = pstruct->fbcinfo.bflc_enable;
+			pinfo->fbc.line_x_budget = pstruct->fbcinfo.line_x_budget;
+			pinfo->fbc.block_x_budget = pstruct->fbcinfo.block_x_budget;
+			pinfo->fbc.block_budget = pstruct->fbcinfo.block_budget;
+			pinfo->fbc.lossless_mode_thd = pstruct->fbcinfo.lossless_mode_thd;
+			pinfo->fbc.lossy_mode_thd = pstruct->fbcinfo.lossy_mode_thd;
+			pinfo->fbc.lossy_rgb_thd = pstruct->fbcinfo.lossy_rgb_thd;
+			pinfo->fbc.lossy_mode_idx = pstruct->fbcinfo.lossy_mode_idx;
+			pinfo->fbc.slice_height = pstruct->fbcinfo.slice_height;
+			pinfo->fbc.pred_mode = pstruct->fbcinfo.pred_mode;
+			pinfo->fbc.max_pred_err = pstruct->fbcinfo.max_pred_err;
+		}
 	}
 
 	pinfo->pre_on = dsi_panel_pre_on;
@@ -330,6 +352,7 @@
 	uint32_t final_xres, final_yres, final_width;
 	uint32_t final_height, final_hbp, final_hfp,final_vbp;
 	uint32_t final_vfp, final_hpw, final_vpw, low_pwr_stop;
+	struct dsc_desc *dsc = NULL;
 
 	if (pinfo->mipi.dual_dsi)
 		panel_width = panel_width / 2;
@@ -343,14 +366,19 @@
 	if (pinfo->mipi.data_lane3)
 		lane_enable |= (1 << 3);
 
+	if (pinfo->compression_mode == COMPRESSION_DSC) {
+		dsc = &pinfo->dsc;
+		panel_width = dsc->pclk_per_line;
+	}
+
 	final_xres = panel_width;
 	final_width = panel_width + pinfo->lcdc.xres_pad;
 
 	if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio) {
 		final_xres /= pinfo->fbc.comp_ratio;
 		final_width /=	pinfo->fbc.comp_ratio;
-		dprintf(SPEW, "DSI xres =%d final_width=%d\n", final_xres,
-				final_width);
+		dprintf(SPEW, "DSI xres =%d final_width=%d\n",
+				final_xres, final_width);
 	}
 	final_yres = pinfo->yres;
 	final_height = pinfo->yres + pinfo->lcdc.yres_pad;
@@ -364,7 +392,8 @@
 			(pinfo->mipi.hbp_power_stop << 4) |
 			pinfo->mipi.hsa_power_stop;
 
-	ret = mdss_dsi_video_mode_config(final_width, final_height,
+	ret = mdss_dsi_video_mode_config(pinfo,
+			final_width, final_height,
 			final_xres, final_yres,
 			final_hfp, final_hbp + final_hpw,
 			final_vfp, final_vbp + final_vpw,
@@ -379,7 +408,8 @@
 			pinfo->mipi.ctl_base);
 
 	if (pinfo->mipi.dual_dsi)
-		ret = mdss_dsi_video_mode_config(final_width, final_height,
+		ret = mdss_dsi_video_mode_config(pinfo,
+				final_width, final_height,
 				final_xres, final_yres,
 				final_hfp, final_hbp + final_hpw,
 				final_vfp, final_vbp + final_vpw,
@@ -405,6 +435,7 @@
 	uint32_t panel_width = pinfo->xres;
 	uint32_t final_xres, final_yres, final_width;
 	uint32_t final_height;
+	struct dsc_desc *dsc = NULL;
 
 	if (pinfo->mipi.dual_dsi)
 		panel_width = panel_width / 2;
@@ -418,19 +449,26 @@
 	if (pinfo->mipi.data_lane3)
 		lane_en |= (1 << 3);
 
+	if (pinfo->compression_mode == COMPRESSION_DSC) {
+		dsc = &pinfo->dsc;
+		panel_width = dsc->pclk_per_line;
+	}
+
 	final_xres = panel_width;
 	final_width = panel_width + pinfo->lcdc.xres_pad;
 
-	if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio) {
-		final_xres /= pinfo->fbc.comp_ratio;
-		final_width /=	pinfo->fbc.comp_ratio;
-		dprintf(SPEW, "DSI xres =%d final_width=%d\n", final_xres,
-				final_width);
+	if (pinfo->compression_mode == COMPRESSION_FBC) {
+		if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio) {
+			final_xres /= pinfo->fbc.comp_ratio;
+			final_width /=	pinfo->fbc.comp_ratio;
+			dprintf(SPEW, "DSI xres =%d final_width=%d\n",
+						final_xres, final_width);
+		}
 	}
 	final_yres = pinfo->yres;
 	final_height = pinfo->yres + pinfo->lcdc.yres_pad;
 
-	ret = mdss_dsi_cmd_mode_config(final_width, final_height,
+	ret = mdss_dsi_cmd_mode_config(pinfo, final_width, final_height,
 			final_xres, final_yres,
 			pinfo->mipi.dst_format,
 			ystride, lane_en,
@@ -438,7 +476,7 @@
 			pinfo->mipi.ctl_base);
 
 	if (pinfo->mipi.dual_dsi)
-		ret = mdss_dsi_cmd_mode_config(final_width, final_height,
+		ret = mdss_dsi_cmd_mode_config(pinfo, final_width, final_height,
 				final_xres, final_yres,
 				pinfo->mipi.dst_format,
 				ystride, lane_en,
diff --git a/dev/gcdb/display/panel_display.h b/dev/gcdb/display/panel_display.h
index 3fd78ae..a998fc2 100755
--- a/dev/gcdb/display/panel_display.h
+++ b/dev/gcdb/display/panel_display.h
@@ -65,6 +65,7 @@
 	struct panel_reset_sequence *panelresetseq;
 	struct backlight            *backlightinfo;
 	struct fb_compression	    fbcinfo;
+	struct dsc_parameters	    dsc_paras;
 };
 
 struct panel_list {
diff --git a/include/platform.h b/include/platform.h
index 0c59056..50ef337 100644
--- a/include/platform.h
+++ b/include/platform.h
@@ -70,4 +70,5 @@
 uint32_t platform_detect_panel();
 uint32_t platform_get_max_periph();
 int platform_is_msm8996();
+uint64_t platform_get_ddr_start();
 #endif
diff --git a/platform/msm8996/include/platform/iomap.h b/platform/msm8996/include/platform/iomap.h
index ea2a0bf..758182e 100644
--- a/platform/msm8996/include/platform/iomap.h
+++ b/platform/msm8996/include/platform/iomap.h
@@ -213,7 +213,7 @@
 #define MMSS_DSI_PHY_PLL_CORE_KVCO_CODE 0x0168
 
 #define MDP_BASE                    (0x900000)
-
+#define REG_MDP(off)                (MDP_BASE + (off))
 
 #ifdef MDP_PP_0_BASE
 #undef MDP_PP_0_BASE
@@ -225,7 +225,8 @@
 #endif
 #define MDP_PP_1_BASE               REG_MDP(0x71800)
 
-#define REG_MDP(off)                (MDP_BASE + (off))
+#define MDP_DSC_0_BASE			REG_MDP(0x81000)
+#define MDP_DSC_1_BASE			REG_MDP(0x81400)
 
 #ifdef MDP_HW_REV
 #undef MDP_HW_REV
@@ -522,9 +523,26 @@
 #define VIDEO_MODE_VSYNC            0x034
 #define VIDEO_MODE_VSYNC_VPOS       0x038
 
+#define VIDEO_COMPRESSION_MODE_CTRL		0x2A0
+#define VIDEO_COMPRESSION_MODE_CTRL_2		0x2A4
+#define CMD_COMPRESSION_MODE_CTRL		0x2A8
+#define CMD_COMPRESSION_MODE_CTRL_2		0x2Ac
+#define CMD_COMPRESSION_MODE_CTRL_3		0x2B0
+
 #define QPNP_LED_CTRL_BASE          0xD000
 #define QPNP_BLUE_LPG_CTRL_BASE     0xB100
 #define QPNP_GREEN_LPG_CTRL_BASE    0xB200
 #define QPNP_RED_LPG_CTRL_BASE      0xB300
 
+#define APSS_WDOG_BASE              0x9830000
+#define APPS_WDOG_BARK_VAL_REG      (APSS_WDOG_BASE + 0x10)
+#define APPS_WDOG_BITE_VAL_REG      (APSS_WDOG_BASE + 0x14)
+#define APPS_WDOG_RESET_REG         (APSS_WDOG_BASE + 0x04)
+#define APPS_WDOG_CTL_REG           (APSS_WDOG_BASE + 0x08)
+
+#define DDR_START                    platform_get_ddr_start()
+#define ABOOT_FORCE_KERNEL_ADDR      DDR_START + 0x8000
+#define ABOOT_FORCE_RAMDISK_ADDR     DDR_START + 0x2200000
+#define ABOOT_FORCE_TAGS_ADDR        DDR_START + 0x2000000
+#define ABOOT_FORCE_KERNEL64_ADDR    DDR_START + 0x80000
 #endif
diff --git a/platform/msm8996/platform.c b/platform/msm8996/platform.c
index 8bdfff0..633857a 100644
--- a/platform/msm8996/platform.c
+++ b/platform/msm8996/platform.c
@@ -57,22 +57,29 @@
 #define COMMON_MEMORY       (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
                            MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
 
+static uint64_t ddr_start;
 
 static mmu_section_t default_mmu_section_table[] =
 {
-/*        Physical addr,    Virtual addr,     Mapping type ,              Size (in MB),            Flags */
+/*       Physical addr,    Virtual addr,     Mapping type ,              Size (in MB),            Flags */
     {    0x00000000,        0x00000000,       MMU_L2_NS_SECTION_MAPPING,  512,                IOMAP_MEMORY},
-    {    KERNEL_ADDR,       KERNEL_ADDR,      MMU_L2_NS_SECTION_MAPPING,  KERNEL_SIZE,        COMMON_MEMORY},
-    {    0x40000000,        0x40000000,       MMU_L1_NS_SECTION_MAPPING,  1024       ,        COMMON_MEMORY},
-    {    0x80000000,        0x80000000,       MMU_L2_NS_SECTION_MAPPING,  88         ,        COMMON_MEMORY},
     {    MEMBASE,           MEMBASE,          MMU_L2_NS_SECTION_MAPPING,  (MEMSIZE / MB),      LK_MEMORY},
     {    SCRATCH_ADDR,      SCRATCH_ADDR,     MMU_L2_NS_SECTION_MAPPING,  SCRATCH_SIZE,        SCRATCH_MEMORY},
     {    MSM_SHARED_BASE,   MSM_SHARED_BASE,  MMU_L2_NS_SECTION_MAPPING,  MSM_SHARED_SIZE,     COMMON_MEMORY},
     {    RPMB_SND_RCV_BUF,  RPMB_SND_RCV_BUF, MMU_L2_NS_SECTION_MAPPING,  RPMB_SND_RCV_BUF_SZ, IOMAP_MEMORY},
 };
 
+static mmu_section_t default_mmu_section_table_3gb[] =
+{
+/*       Physical addr,    Virtual addr,     Mapping type ,              Size (in MB),            Flags */
+    {    0x40000000,        0x40000000,       MMU_L1_NS_SECTION_MAPPING,  1024       ,        COMMON_MEMORY},
+    {    0x80000000,        0x80000000,       MMU_L2_NS_SECTION_MAPPING,  88         ,        COMMON_MEMORY},
+};
+
+
 static mmu_section_t dload_mmu_section_table[] =
 {
+/*    Physical addr,    Virtual addr,     Mapping type ,              Size (in MB),            Flags */
     { 0x85800000, 0x85800000, MMU_L2_NS_SECTION_MAPPING, 178, COMMON_MEMORY},
 };
 
@@ -110,10 +117,43 @@
 {
 	int i;
 	int table_sz = ARRAY_SIZE(default_mmu_section_table);
+	mmu_section_t kernel_mmu_section_table;
+	uint64_t ddr_size = smem_get_ddr_size();
 
+	if (ddr_size == MEM_4GB)
+	{
+		ddr_start = 0x80000000;
+	}
+	else if (ddr_size == MEM_3GB)
+	{
+		ddr_start = 0x20000000;
+	}
+	else
+	{
+		dprintf(CRITICAL, "Unsupported memory map\n");
+		ASSERT(0);
+	}
+
+	kernel_mmu_section_table.paddress = ddr_start;
+	kernel_mmu_section_table.vaddress = ddr_start;
+	kernel_mmu_section_table.type = MMU_L2_NS_SECTION_MAPPING;
+	kernel_mmu_section_table.size = KERNEL_SIZE;
+	kernel_mmu_section_table.flags = COMMON_MEMORY;
+
+	/* Map kernel entry */
+	arm_mmu_map_entry(&kernel_mmu_section_table);
+
+	/* Map default memory needed for lk , scratch, rpmb & iomap */
 	for (i = 0 ; i < table_sz; i++)
 		arm_mmu_map_entry(&default_mmu_section_table[i]);
 
+	/* Map the rest of the DDR for 3GB needed for ramdump */
+	if (ddr_size == MEM_3GB)
+	{
+		for (i = 0 ; i < (int)ARRAY_SIZE(default_mmu_section_table_3gb); i++)
+			arm_mmu_map_entry(&default_mmu_section_table_3gb[i]);
+	}
+
 	if (scm_device_enter_dload())
 	{
 		/* TZ & Hyp memory can be mapped only while entering the download mode */
@@ -162,3 +202,8 @@
 	else
 		return 0;
 }
+
+uint64_t platform_get_ddr_start()
+{
+	return ddr_start;
+}
diff --git a/platform/msm_shared/hsusb.c b/platform/msm_shared/hsusb.c
index abb3b1d..6a8e9e6 100644
--- a/platform/msm_shared/hsusb.c
+++ b/platform/msm_shared/hsusb.c
@@ -64,8 +64,8 @@
 	if ((len > 255) || (len < 2) || (num > 255) || (type > 255))
 		return 0;
 
-	if (!(desc = malloc(sizeof(struct udc_descriptor) + len)))
-		return 0;
+	desc = malloc(sizeof(struct udc_descriptor) + len);
+	ASSERT(desc);
 
 	desc->next = 0;
 	desc->tag = (type << 8) | num;
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index 43e2c0e..9253548 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -196,6 +196,31 @@
 #define MDSS_MDP_REG_PP_FBC_BUDGET_CTL          0x038
 #define MDSS_MDP_REG_PP_FBC_LOSSY_MODE          0x03C
 
+#define MDSS_MDP_REG_DCE_SEL			REG_MDP(0x1450)
+
+#define MDSS_MDP_PP_DSC_MODE                0x0A0
+#define MDSS_MDP_PP_DCE_DATA_OUT_SWAP	0x0C8
+
+#define MDSS_MDP_DSC_COMMON_MODE		0x00
+#define MDSS_MDP_DSC_ENC			0x04
+#define MDSS_MDP_DSC_PICTURE			0x08
+#define MDSS_MDP_DSC_SLICE			0x0c
+#define MDSS_MDP_DSC_CHUNK_SIZE			0x10
+#define MDSS_MDP_DSC_DELAY			0x14
+#define MDSS_MDP_DSC_SCALE_INITIAL		0x18
+#define MDSS_MDP_DSC_SCALE_DEC_INTERVAL		0x1c
+#define MDSS_MDP_DSC_SCALE_INC_INTERVAL		0x20
+#define MDSS_MDP_DSC_FIRST_LINE_BPG_OFFSET	0x24
+#define MDSS_MDP_DSC_BPG_OFFSET			0x28
+#define MDSS_MDP_DSC_DSC_OFFSET			0x2c
+#define MDSS_MDP_DSC_FLATNESS			0x30
+#define MDSS_MDP_DSC_RC_MODEL_SIZE		0x34
+#define MDSS_MDP_DSC_RC				0x38
+#define MDSS_MDP_DSC_RC_BUF_THRESH		0x3c	/* 14 bytes */
+#define MDSS_MDP_DSC_RANGE_MIN_QP		0x74	/* 15 bytes */
+#define MDSS_MDP_DSC_RANGE_MAX_QP		0xB0	/* 15 bytes */
+#define MDSS_MDP_DSC_RANGE_BPG_OFFSET		0xEc	/* 15 bytes */
+
 void mdp_set_revision(int rev);
 int mdp_get_revision();
 int mdp_dsi_video_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
@@ -222,4 +247,10 @@
 void mdss_hdmi_get_vic(char *buf);
 int msm_display_off();
 void display_shutdown(void);
+
+void mdss_dsc_parameters_calc(struct msm_panel_info *pinfo);
+int mdss_dsc_to_buf(struct msm_panel_info *pinfo);
+void mdss_dsc_dsi_config(uint32_t ctl_base, int mode, struct dsc_desc *dsc);
+void mdss_dsc_mdp_config(struct msm_panel_info *pinfo);
+
 #endif
diff --git a/platform/msm_shared/include/mipi_dsi.h b/platform/msm_shared/include/mipi_dsi.h
index 845c495..c445230 100644
--- a/platform/msm_shared/include/mipi_dsi.h
+++ b/platform/msm_shared/include/mipi_dsi.h
@@ -240,7 +240,8 @@
 				uint32_t phy_base);
 int mipi_dsi_phy_init(struct mipi_dsi_panel_config *pinfo);
 
-int mdss_dsi_video_mode_config(uint16_t disp_width,
+int mdss_dsi_video_mode_config(struct msm_panel_info *pinfo,
+	uint16_t disp_width,
 	uint16_t disp_height,
 	uint16_t img_width,
 	uint16_t img_height,
@@ -258,7 +259,8 @@
 	uint8_t eof_bllp_pwr,
 	uint8_t interleav,
 	uint32_t ctl_base);
-int mdss_dsi_cmd_mode_config(uint16_t disp_width,
+int mdss_dsi_cmd_mode_config(struct msm_panel_info *pinfo,
+	uint16_t disp_width,
 	uint16_t disp_height,
 	uint16_t img_width,
 	uint16_t img_height,
@@ -284,4 +286,5 @@
 void mdss_dsi_uniphy_pll_lock_detect_setting(uint32_t pll_base);
 void mdss_dsi_uniphy_pll_sw_reset(uint32_t pll_base);
 int mdss_dsi_post_on(struct msm_fb_panel_data *panel);
+
 #endif
diff --git a/platform/msm_shared/include/mmu.h b/platform/msm_shared/include/mmu.h
index d70872e..9154066 100644
--- a/platform/msm_shared/include/mmu.h
+++ b/platform/msm_shared/include/mmu.h
@@ -32,6 +32,9 @@
 #include <sys/types.h>
 #include <arch/arm/mmu.h>
 
+#define MEM_4GB      0x100000000
+#define MEM_3GB      0xC0000000
+
 #ifdef LPAE
 typedef struct {
 	uint64_t paddress;
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index 03c8ae9..f918876 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -120,6 +120,87 @@
 	uint8_t dst_split;
 };
 
+enum {
+	COMPRESSION_NONE,
+	COMPRESSION_DSC,
+	COMPRESSION_FBC
+};
+
+#define DCS_HDR_LEN	4
+#define DSC_PPS_LEN	128
+
+struct msm_panel_info;
+
+struct dsc_desc {
+	int data_path_model;            /* multiplex + split_panel */
+	int ich_reset_value;
+	int ich_reset_override;
+	int initial_lines;
+	int slice_last_group_size;
+	int bpp;        /* target bit per pixel */
+	int bpc;        /* bit per component */
+	int line_buf_depth;
+	int config_by_manufacture_cmd;
+	int block_pred_enable;
+	int vbr_enable;
+	int enable_422;
+	int convert_rgb;
+	int input_10_bits;
+	int slice_per_pkt;
+
+	int major;
+	int minor;
+	int pps_id;
+
+	int pic_height;
+	int pic_width;
+	int slice_height;
+	int slice_width;
+	int chunk_size;
+
+	int pkt_per_line;
+	int bytes_in_slice;
+	int bytes_per_pkt;
+	int eol_byte_num;
+	int pclk_per_line;      /* width */
+
+	int initial_dec_delay;
+	int initial_xmit_delay;
+
+	int initial_scale_value;
+	int scale_decrement_interval;
+	int scale_increment_interval;
+
+	int first_line_bpg_offset;
+	int nfl_bpg_offset;
+	int slice_bpg_offset;
+
+	int initial_offset;
+	int final_offset;
+
+	int rc_model_size;      /* rate_buffer_size */
+
+	int det_thresh_flatness;
+	int max_qp_flatness;
+	int min_qp_flatness;
+	int edge_factor;
+	int quant_incr_limit0;
+	int quant_incr_limit1;
+	int tgt_offset_hi;
+	int tgt_offset_lo;
+	char *buf_thresh;
+	char *range_min_qp;
+	char *range_max_qp;
+	char *range_bpg_offset;
+	char pps_buf[DCS_HDR_LEN + DSC_PPS_LEN];
+
+	void (*parameter_calc) (struct msm_panel_info *pinfo);
+	int (*dsc2buf) (struct msm_panel_info *pinfo);
+	void (*dsi_dsc_config) (uint32_t base, int mode, struct dsc_desc *dsc);
+	void (*mdp_dsc_config) (struct msm_panel_info *pinfo);
+
+};
+
 struct fbc_panel_info {
 	uint32_t enabled;
 	uint32_t comp_ratio;
@@ -304,6 +385,7 @@
 	uint32_t clk_rate;
 	uint32_t orientation;
 	uint32_t dest;
+	uint32_t compression_mode;
 	/*  Select pipe type for handoff */
 	uint32_t pipe_type;
 	char     lowpowerstop;
@@ -316,6 +398,7 @@
 	struct lcd_panel_info lcd;
 	struct lcdc_panel_info lcdc;
 	struct fbc_panel_info fbc;
+	struct dsc_desc dsc;
 	struct mipi_panel_info mipi;
 	struct lvds_panel_info lvds;
 	struct hdmi_panel_info hdmi;
diff --git a/platform/msm_shared/mdp3.c b/platform/msm_shared/mdp3.c
index 43f5123..5a8a848 100644
--- a/platform/msm_shared/mdp3.c
+++ b/platform/msm_shared/mdp3.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -71,10 +71,13 @@
 	writel(0x0, MDP_DMA_P_WATERMARK_0);
 	writel(0x0, MDP_DMA_P_WATERMARK_1);
 	writel(0x0, MDP_DMA_P_WATERMARK_2);
-	if (pinfo->xres >= 720)
+	if (pinfo->xres >= 720) {
 		writel(0xFFFF, MDP_PANIC_LUT0);
-	else
+		writel(0xFF00, MDP_ROBUST_LUT);
+	} else {
 		writel(0x00FF, MDP_PANIC_LUT0);
+		writel(0xFFF0, MDP_ROBUST_LUT);
+	}
 	writel(0x1, MDP_PANIC_ROBUST_CTRL);
 	writel(0xFF00, MDP_ROBUST_LUT);
 
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index ef083ea..901f42e 100755
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -479,6 +479,7 @@
 	uint32_t display_hctl, hsync_ctl, display_vstart, display_vend;
 	uint32_t adjust_xres = 0;
 	uint32_t upper = 0, lower = 0;
+	struct dsc_desc *dsc = NULL;
 
 	struct lcdc_panel_info *lcdc = NULL;
 	struct intf_timing_params itp = {0};
@@ -513,12 +514,22 @@
 		writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CONFIG */
 	}
 
-	if (!pinfo->fbc.enabled || !pinfo->fbc.comp_ratio)
-		pinfo->fbc.comp_ratio = 1;
+	if (pinfo->compression_mode == COMPRESSION_DSC) {
+		dsc = &pinfo->dsc;
+	} else if (pinfo->compression_mode == COMPRESSION_FBC) {
+		if (!pinfo->fbc.enabled || !pinfo->fbc.comp_ratio)
+			pinfo->fbc.comp_ratio = 1;
+	}
 
 	itp.xres = (adjust_xres / pinfo->fbc.comp_ratio);
 	itp.yres = pinfo->yres;
 	itp.width =((adjust_xres + pinfo->lcdc.xres_pad) / pinfo->fbc.comp_ratio);
+
+	if (dsc) {
+		itp.xres = dsc->pclk_per_line;
+		itp.width = dsc->pclk_per_line;
+	}
+
 	itp.height = pinfo->yres + pinfo->lcdc.yres_pad;
 	itp.h_back_porch = pinfo->lcdc.h_back_porch;
 	itp.h_front_porch = pinfo->lcdc.h_front_porch;
@@ -593,6 +604,7 @@
 	uint32_t prefetch_avail, prefetch_needed;
 	uint32_t adjust_xres = 0;
 	uint32_t fetch_enable = BIT(31);
+	struct dsc_desc *dsc;
 
 	struct lcdc_panel_info *lcdc = NULL;
 
@@ -617,8 +629,13 @@
 	if (pinfo->lcdc.split_display)
 		adjust_xres /= 2;
 
-	if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio)
-		adjust_xres /= pinfo->fbc.comp_ratio;
+	if (pinfo->compression_mode == COMPRESSION_DSC) {
+		dsc = &pinfo->dsc;
+		adjust_xres = dsc->pclk_per_line;
+	} else if (pinfo->compression_mode == COMPRESSION_FBC) {
+		if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio)
+			adjust_xres /= pinfo->fbc.comp_ratio;
+	}
 
 	/*
 	 * Fetch should always be outside the active lines. If the fetching
@@ -956,8 +973,19 @@
 	/*If dst_split is enabled only intf 2 needs to be enabled.
 	CTL_1 path should not be set since CTL_0 itself is going
 	to split after DSPP block*/
-	if (pinfo->fbc.enabled)
-		mdss_fbc_cfg(pinfo);
+
+	if (pinfo->compression_mode == COMPRESSION_DSC) {
+		struct dsc_desc *dsc = NULL;
+
+		dsc = &pinfo->dsc;
+		if (dsc) {
+			if (dsc->mdp_dsc_config)
+				dsc->mdp_dsc_config(pinfo);
+		}
+	} else if (pinfo->compression_mode == COMPRESSION_FBC) {
+		if (pinfo->fbc.enabled)
+			mdss_fbc_cfg(pinfo);
+	}
 
 	if (pinfo->mipi.dual_dsi) {
 		if (!pinfo->lcdc.dst_split) {
@@ -1108,8 +1136,18 @@
 	reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 1);
 	writel(reg, MDP_CTL_0_BASE + CTL_TOP);
 
-	if (pinfo->fbc.enabled)
-		mdss_fbc_cfg(pinfo);
+	if (pinfo->compression_mode == COMPRESSION_DSC) {
+		struct dsc_desc *dsc = NULL;
+
+		dsc = &pinfo->dsc;
+		if (dsc) {
+			if (dsc->mdp_dsc_config)
+				dsc->mdp_dsc_config(pinfo);
+		}
+	} else if (pinfo->compression_mode == COMPRESSION_FBC) {
+		if (pinfo->fbc.enabled)
+			mdss_fbc_cfg(pinfo);
+	}
 
 	if (pinfo->mipi.dual_dsi) {
 		writel(0x213F, sintf_base + MDP_PANEL_FORMAT);
diff --git a/platform/msm_shared/mipi_dsc.c b/platform/msm_shared/mipi_dsc.c
new file mode 100644
index 0000000..33821c0
--- /dev/null
+++ b/platform/msm_shared/mipi_dsc.c
@@ -0,0 +1,513 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *   * Neither the name of The Linux Foundation nor
+ *     the names of its contributors may be used to endorse or promote
+ *     products derived from this software without specific prior written
+ *     permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <mdp5.h>
+#include <reg.h>
+#include <bits.h>
+#include <msm_panel.h>
+#include <panel.h>
+#include <platform/iomap.h>
+#include <mipi_dsi.h>
+
+/*
+ * rc_buf_thresh = {896, 1792, 2688, 3548, 4480, 5376, 6272, 6720,
+ *		7168, 7616, 7744, 7872, 8000, 8064, 8192};
+ *	(x >> 6) & 0x0ff)
+ */
+static char dsc_rc_buf_thresh[] = {0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54,
+		0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e};
+static char dsc_rc_range_min_qp[] = {0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5,
+				5, 5, 7, 13};
+static char dsc_rc_range_max_qp[] = {4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11,
+			 12, 13, 13, 15};
+static char dsc_rc_range_bpg_offset[] = {2, 0, 0, -2, -4, -6, -8, -8,
+			-8, -10, -10, -12, -12, -12, -12};
+
+#define CEIL(x, y)              (((x) + ((y)-1)) / (y))
+
+int mdss_dsc_to_buf(struct msm_panel_info *pinfo)
+{
+	struct dsc_desc *dsc;
+	char *bp;
+	char data;
+	int i, bpp;
+
+	dsc = &pinfo->dsc;
+	bp = dsc->pps_buf;
+
+	*bp++ = 128;	/* pps length */
+	*bp++ = 0;
+	*bp++ = 0x0a;	/* PPS data type */
+	*bp++ = 0xc0;	/* last + long pkt */
+
+	/* pps payload */
+	*bp++ = ((dsc->major << 4) | dsc->minor);	/* pps0 */
+	*bp++ = dsc->pps_id;				/* pps1 */
+	bp++;					/* pps2, reserved */
+
+	data = dsc->line_buf_depth & 0x0f;
+	data |= (dsc->bpc << 4);
+	*bp++ = data;				 /* pps3 */
+
+	bpp = dsc->bpp;
+	bpp <<= 4;	/* 4 fraction bits */
+	data = (bpp >> 8);
+	data &= 0x03;		/* upper two bits */
+	data |= (dsc->block_pred_enable << 5);
+	data |= (dsc->convert_rgb << 4);
+	data |= (dsc->enable_422 << 3);
+	data |= (dsc->vbr_enable << 2);
+	*bp++ = data;				/* pps4 */
+	*bp++ = bpp;				/* pps5 */
+
+	*bp++ = (dsc->pic_height >> 8);		/* pps6 */
+	*bp++ = (dsc->pic_height & 0x0ff);	/* pps7 */
+	*bp++ = (dsc->pic_width >> 8);		/* pps8 */
+	*bp++ = (dsc->pic_width & 0x0ff);	/* pps9 */
+
+	*bp++ = (dsc->slice_height >> 8);	/* pps10 */
+	*bp++ = (dsc->slice_height & 0x0ff);	/* pps11 */
+	*bp++ = (dsc->slice_width >> 8);	/* pps12 */
+	*bp++ = (dsc->slice_width & 0x0ff);	/* pps13 */
+
+	*bp++ = (dsc->chunk_size >> 8);		/* pps14 */
+	*bp++ = (dsc->chunk_size & 0x0ff);	/* pps15 */
+
+	data = dsc->initial_xmit_delay >> 8;
+	data &= 0x03;
+	*bp++ = data;				/* pps16, bit 0, 1 */
+	*bp++ = dsc->initial_xmit_delay;	/* pps17 */
+
+	*bp++ = (dsc->initial_dec_delay >> 8);	/* pps18 */
+	*bp++ = dsc->initial_dec_delay;		/* pps19 */
+
+	bp++;					/* pps20, reserved */
+
+	*bp++ = (dsc->initial_scale_value & 0x3f); /* pps21 */
+
+	data = (dsc->scale_increment_interval >> 8);
+	data &= 0x0f;
+	*bp++ =  data;				/* pps22 */
+	*bp++ = dsc->scale_increment_interval;	/* pps23 */
+
+	data = (dsc->scale_decrement_interval >> 8);
+	data &= 0x0f;
+	*bp++ = data;				/* pps24 */
+	*bp++ = (dsc->scale_decrement_interval & 0x0ff);/* pps25 */
+
+	bp++;			/* pps26, reserved */
+
+	*bp++ = (dsc->first_line_bpg_offset & 0x1f);/* pps27 */
+
+	*bp++ = (dsc->nfl_bpg_offset >> 8);	/* pps28 */
+	*bp++ = (dsc->nfl_bpg_offset & 0x0ff);	/* pps29 */
+	*bp++ = (dsc->slice_bpg_offset >> 8);	/* pps30 */
+	*bp++ = (dsc->slice_bpg_offset & 0x0ff);/* pps31 */
+
+	*bp++ = (dsc->initial_offset >> 8);	/* pps32 */
+	*bp++ = (dsc->initial_offset & 0x0ff);	/* pps33 */
+
+	*bp++ = (dsc->final_offset >> 8);	/* pps34 */
+	*bp++ = (dsc->final_offset & 0x0ff);	/* pps35 */
+
+	*bp++ = (dsc->min_qp_flatness & 0x1f);	/* pps36 */
+	*bp++ = (dsc->max_qp_flatness & 0x1f);	/* pps37 */
+
+	*bp++ = (dsc->rc_model_size >> 8);	/* pps38 */
+	*bp++ = (dsc->rc_model_size & 0x0ff);	/* pps39 */
+
+	*bp++ = (dsc->edge_factor & 0x0f);	/* pps40 */
+
+	*bp++ = (dsc->quant_incr_limit0 & 0x1f);	/* pps41 */
+	*bp++ = (dsc->quant_incr_limit1 & 0x1f);	/* pps42 */
+
+	data = (dsc->tgt_offset_hi << 4);
+	data |= (dsc->tgt_offset_lo & 0x0f);
+	*bp++ = data;				/* pps43 */
+
+	for (i = 0; i < 14; i++)
+		*bp++ = dsc->buf_thresh[i];	/* pps44 - pps57 */
+
+	for (i = 0; i < 15; i++) {		/* pps58 - pps87 */
+		data = (dsc->range_min_qp[i] & 0x1f); /* 5 bits */
+		data <<= 3;
+		data |= ((dsc->range_max_qp[i] >> 2) & 0x07); /* 3 bits */
+		*bp++ = data;
+		data = (dsc->range_max_qp[i] & 0x03); /* 2 bits */
+		data <<= 6;
+		data |= (dsc->range_bpg_offset[i] & 0x3f); /* 6 bits */
+		*bp++ = data;
+	}
+
+	/* pps88 to pps127 are reserved */
+
+	return 128;
+}
+
+static int mdss_dsc_initial_line_calc(int bpc, int xmit_delay,
+			int slice_width, int slice_per_line)
+{
+	int ssm_delay;
+	int total_pixels;
+
+	ssm_delay = ((bpc < 10) ? 83 : 91);
+	total_pixels = ssm_delay * 3 + 30 + xmit_delay + 6;
+	total_pixels += ((slice_per_line > 1) ? (ssm_delay * 3) : 0);
+
+	return CEIL(total_pixels, slice_width);
+}
+
+void mdss_dsc_parameters_calc(struct msm_panel_info *pinfo)
+{
+	struct dsc_desc *dsc;
+	int bpp, bpc;
+	int mux_words_size;
+	int groups_per_line, groups_total;
+	int min_rate_buffer_size;
+	int hrd_delay;
+	int pre_num_extra_mux_bits, num_extra_mux_bits;
+	int slice_bits;
+	int target_bpp_x16;
+	int data;
+	int final_value, final_scale;
+	int slice_per_line, bytes_in_slice, total_bytes;
+
+	dsc = &pinfo->dsc;
+	dsc->rc_model_size = 8192;	/* rate_buffer_size */
+	dsc->first_line_bpg_offset = 12;
+	dsc->min_qp_flatness = 3;
+	dsc->max_qp_flatness = 12;
+	dsc->line_buf_depth = 9;
+
+	dsc->edge_factor = 6;
+	dsc->quant_incr_limit0 = 11;
+	dsc->quant_incr_limit1 = 11;
+	dsc->tgt_offset_hi = 3;
+	dsc->tgt_offset_lo = 3;
+
+	dsc->buf_thresh = dsc_rc_buf_thresh;
+	dsc->range_min_qp = dsc_rc_range_min_qp;
+	dsc->range_max_qp = dsc_rc_range_max_qp;
+	dsc->range_bpg_offset = dsc_rc_range_bpg_offset;
+
+	dsc->pic_width = pinfo->xres;
+	dsc->pic_height = pinfo->yres;
+
+	bpp = dsc->bpp;
+	bpc = dsc->bpc;
+
+	if (bpp == 8)
+		dsc->initial_offset = 6144;
+	else
+		dsc->initial_offset = 2048;	/* bpp = 12 */
+
+	if (bpc == 8)
+		mux_words_size = 48;
+	else
+		mux_words_size = 64;	/* bpc == 12 */
+
+	slice_per_line = CEIL(dsc->pic_width, dsc->slice_width);
+
+	dsc->pkt_per_line = slice_per_line / dsc->slice_per_pkt;
+	if (slice_per_line % dsc->slice_per_pkt)
+		dsc->pkt_per_line = 1;		/* default*/
+
+	bytes_in_slice = CEIL(dsc->pic_width, slice_per_line);
+
+	bytes_in_slice *= dsc->bpp;	/* bites per compressed pixel */
+	bytes_in_slice = CEIL(bytes_in_slice, 8);
+
+	dsc->bytes_in_slice = bytes_in_slice;
+
+	dprintf(SPEW, "%s: slice_per_line=%d pkt_per_line=%d bytes_in_slice=%d\n",
+		__func__, slice_per_line, dsc->pkt_per_line, bytes_in_slice);
+
+	total_bytes = bytes_in_slice * slice_per_line;
+	dsc->eol_byte_num = total_bytes % 3;
+	dsc->pclk_per_line =  CEIL(total_bytes, 3);
+
+	dsc->slice_last_group_size = 3 - dsc->eol_byte_num;
+
+	dprintf(SPEW, "%s: pclk_per_line=%d total_bytes=%d eol_byte_num=%d\n",
+		__func__, dsc->pclk_per_line, total_bytes, dsc->eol_byte_num);
+
+	dsc->bytes_per_pkt = bytes_in_slice * dsc->slice_per_pkt;
+
+	dsc->det_thresh_flatness = 7 + (bpc - 8);
+
+	dsc->initial_xmit_delay = dsc->rc_model_size / (2 * bpp);
+
+	dsc->initial_lines = mdss_dsc_initial_line_calc(bpc,
+		dsc->initial_xmit_delay, dsc->slice_width, slice_per_line);
+
+	groups_per_line = CEIL(dsc->slice_width, 3);
+
+	dsc->chunk_size = dsc->slice_width * bpp / 8;
+	if ((dsc->slice_width * bpp) % 8)
+		dsc->chunk_size++;
+
+
+	/* rbs-min */
+	min_rate_buffer_size =  dsc->rc_model_size - dsc->initial_offset +
+			dsc->initial_xmit_delay * bpp +
+			groups_per_line * dsc->first_line_bpg_offset;
+
+	hrd_delay = CEIL(min_rate_buffer_size, bpp);
+
+	dsc->initial_dec_delay = hrd_delay - dsc->initial_xmit_delay;
+
+	dsc->initial_scale_value = 8 * dsc->rc_model_size /
+			(dsc->rc_model_size - dsc->initial_offset);
+
+	slice_bits = 8 * dsc->chunk_size * dsc->slice_height;
+
+	groups_total = groups_per_line * dsc->slice_height;
+
+	data = dsc->first_line_bpg_offset * 2048;
+
+	dsc->nfl_bpg_offset = CEIL(data, (dsc->slice_height - 1));
+
+	pre_num_extra_mux_bits = 3 * (mux_words_size + (4 * bpc + 4) - 2);
+
+	num_extra_mux_bits = pre_num_extra_mux_bits - (mux_words_size -
+		((slice_bits - pre_num_extra_mux_bits) % mux_words_size));
+
+	data = 2048 * (dsc->rc_model_size - dsc->initial_offset
+		+ num_extra_mux_bits);
+	dsc->slice_bpg_offset = CEIL(data, groups_total);
+
+	/* bpp * 16 + 0.5 */
+	data = bpp * 16;
+	data *= 2;
+	data++;
+	data /= 2;
+	target_bpp_x16 = data;
+
+	data = (dsc->initial_xmit_delay * target_bpp_x16) / 16;
+	final_value =  dsc->rc_model_size - data + num_extra_mux_bits;
+
+	final_scale = 8 * dsc->rc_model_size /
+		(dsc->rc_model_size - final_value);
+
+	dsc->final_offset = final_value;
+
+	data = (final_scale - 9) * (dsc->nfl_bpg_offset +
+		dsc->slice_bpg_offset);
+	dsc->scale_increment_interval = (2048 * dsc->final_offset) / data;
+
+	dsc->scale_decrement_interval = groups_per_line /
+		(dsc->initial_scale_value - 8);
+
+	dprintf(SPEW, "%s: initial_xmit_delay=%d\n", __func__,
+		dsc->initial_xmit_delay);
+
+	dprintf(SPEW, "%s: bpg_offset, nfl=%d slice=%d\n", __func__,
+		dsc->nfl_bpg_offset, dsc->slice_bpg_offset);
+
+	dprintf(SPEW, "%s: groups_per_line=%d chunk_size=%d\n", __func__,
+		groups_per_line, dsc->chunk_size);
+	dprintf(SPEW, "%s:min_rate_buffer_size=%d hrd_delay=%d\n", __func__,
+		min_rate_buffer_size, hrd_delay);
+	dprintf(SPEW, "%s:initial_dec_delay=%d initial_scale_value=%d\n", __func__,
+		dsc->initial_dec_delay, dsc->initial_scale_value);
+	dprintf(SPEW, "%s:slice_bits=%d, groups_total=%d\n", __func__,
+		slice_bits, groups_total);
+	dprintf(SPEW, "%s: first_line_bgp_offset=%d slice_height=%d\n", __func__,
+		dsc->first_line_bpg_offset, dsc->slice_height);
+	dprintf(SPEW, "%s:final_value=%d final_scale=%d\n", __func__,
+		final_value, final_scale);
+	dprintf(SPEW, "%s: sacle_increment_interval=%d scale_decrement_interval=%d\n",
+		__func__, dsc->scale_increment_interval,
+		dsc->scale_decrement_interval);
+}
+
+void mdss_dsc_mdp_config(struct msm_panel_info *pinfo)
+{
+	unsigned int data;
+	unsigned int offset, off;
+	struct dsc_desc *dsc;
+	char *lp;
+        char *cp;
+        int i, bpp, lsb;
+
+	/* dce0_sel->pp0, dce1_sel->pp1 */
+	writel(0x0, MDSS_MDP_REG_DCE_SEL);
+
+	/* dsc enable */
+	writel(1, MDP_PP_0_BASE + MDSS_MDP_PP_DSC_MODE);
+
+	data = readl(MDP_PP_0_BASE + MDSS_MDP_PP_DCE_DATA_OUT_SWAP);
+	data |= BIT(18);	/* endian flip */
+	writel(data, MDP_PP_0_BASE + MDSS_MDP_PP_DCE_DATA_OUT_SWAP);
+
+	offset = MDP_DSC_0_BASE;
+
+	data = 0;
+	dsc = &pinfo->dsc;
+	if (pinfo->type == MIPI_VIDEO_PANEL)
+		data = BIT(2);	/* video mode */
+
+	writel(data, offset + MDSS_MDP_DSC_COMMON_MODE);
+
+	data = dsc->ich_reset_value | dsc->ich_reset_override;
+	data <<= 28;
+	data |= (dsc->initial_lines << 20);
+	data |= ((dsc->slice_last_group_size - 1) << 18);
+
+	/* bpp is 6.4 format, 4 LSBs bits are for fractional part */
+	lsb = dsc->bpp % 4;
+	bpp = dsc->bpp / 4;
+	bpp *= 4;	/* either 8 or 12 */
+	bpp <<= 4;
+	bpp |= lsb;
+	data |= (bpp << 8);
+	data |= (dsc->block_pred_enable << 7);
+	data |= (dsc->line_buf_depth << 3);
+	data |= (dsc->enable_422 << 2);
+	data |= (dsc->convert_rgb << 1);
+	data |= dsc->input_10_bits;
+
+	dprintf(SPEW, "%s: %d %d %d %d %d %d %d %d %d %d, data=%x\n",
+		__func__, dsc->ich_reset_value, dsc->ich_reset_override,
+		dsc->initial_lines , dsc->slice_last_group_size,
+		dsc->bpp, dsc->block_pred_enable, dsc->line_buf_depth,
+		dsc->enable_422, dsc->convert_rgb, dsc->input_10_bits, data);
+
+	writel(data, offset + MDSS_MDP_DSC_ENC);
+
+	data = dsc->pic_width << 16;
+	data |= dsc->pic_height;
+	writel(data, offset + MDSS_MDP_DSC_PICTURE);
+
+	data = dsc->slice_width << 16;
+	data |= dsc->slice_height;
+	writel(data, offset + MDSS_MDP_DSC_SLICE);
+
+	data = dsc->chunk_size << 16;
+	writel(data, offset + MDSS_MDP_DSC_CHUNK_SIZE);
+
+	dprintf(SPEW, "%s: pic_w=%d pic_h=%d, slice_h=%d slice_w=%d, chunk=%d\n",
+		__func__, dsc->pic_width, dsc->pic_height,
+		dsc->slice_width, dsc->slice_height, dsc->chunk_size);
+
+	data = dsc->initial_dec_delay << 16;
+	data |= dsc->initial_xmit_delay;
+	writel(data, offset + MDSS_MDP_DSC_DELAY);
+
+	data = dsc->initial_scale_value;
+	writel(data, offset + MDSS_MDP_DSC_SCALE_INITIAL);
+
+	data = dsc->scale_decrement_interval;
+	writel(data, offset + MDSS_MDP_DSC_SCALE_DEC_INTERVAL);
+
+	data = dsc->scale_increment_interval;
+	writel(data, offset + MDSS_MDP_DSC_SCALE_INC_INTERVAL);
+
+	data = dsc->first_line_bpg_offset;
+	writel(data, offset + MDSS_MDP_DSC_FIRST_LINE_BPG_OFFSET);
+
+	data = dsc->nfl_bpg_offset << 16;
+	data |= dsc->slice_bpg_offset;
+	writel(data, offset + MDSS_MDP_DSC_BPG_OFFSET);
+
+	data = dsc->initial_offset << 16;
+	data |= dsc->final_offset;
+	writel(data, offset + MDSS_MDP_DSC_DSC_OFFSET);
+
+	data = dsc->det_thresh_flatness << 10;
+	data |= dsc->max_qp_flatness << 5;
+	data |= dsc->min_qp_flatness;
+	writel(data, offset + MDSS_MDP_DSC_FLATNESS);
+
+	data = dsc->rc_model_size;	/* rate_buffer_size */
+	writel(data, offset + MDSS_MDP_DSC_RC_MODEL_SIZE);
+
+	data = dsc->tgt_offset_lo << 18;
+	data |= dsc->tgt_offset_hi << 14;
+	data |= dsc->quant_incr_limit1 << 9;
+	data |= dsc->quant_incr_limit0 << 4;
+	data |= dsc->edge_factor;
+	writel(data, offset + MDSS_MDP_DSC_RC);
+
+	lp = dsc->buf_thresh;
+	off = offset + MDSS_MDP_DSC_RC_BUF_THRESH;
+	for (i = 0; i < 14; i++) {
+		writel(*lp++, off);
+		off += 4;
+	}
+
+	cp = dsc->range_min_qp;
+	off = offset + MDSS_MDP_DSC_RANGE_MIN_QP;
+	for (i = 0; i < 15; i++) {
+		writel(*cp++, off);
+		off += 4;
+	}
+
+	cp = dsc->range_max_qp;
+	off = offset + MDSS_MDP_DSC_RANGE_MAX_QP;
+	for (i = 0; i < 15; i++) {
+		writel(*cp++, off);
+		off += 4;
+	}
+
+	cp = dsc->range_bpg_offset;
+	off = offset + MDSS_MDP_DSC_RANGE_BPG_OFFSET;
+	for (i = 0; i < 15; i++) {
+		writel(*cp++, off);
+		off += 4;
+	}
+}
+
+void mdss_dsc_dsi_config(uint32_t ctl_base, int mode,
+                                struct dsc_desc *dsc)
+{
+        unsigned int data;
+
+	if (mode == DSI_VIDEO_MODE) {
+		writel(0, ctl_base + VIDEO_COMPRESSION_MODE_CTRL_2);
+                data = dsc->bytes_per_pkt << 16;
+                data |= (0x0b << 8);    /*  dtype of compressed image */
+                data |= (dsc->pkt_per_line - 1) << 6;
+                data |= dsc->eol_byte_num << 4;
+                data |= 1;      /* enable */
+
+		writel(data, ctl_base + VIDEO_COMPRESSION_MODE_CTRL);
+        } else {
+                /* strem 0 */
+		writel(0, ctl_base + CMD_COMPRESSION_MODE_CTRL_3);
+
+		data = dsc->bytes_in_slice;
+		writel(data, ctl_base + CMD_COMPRESSION_MODE_CTRL_2);
+
+                data = 0x39 << 8;
+                data |= (dsc->pkt_per_line - 1) << 6;
+                data |= dsc->eol_byte_num << 4;
+                data |= 1;      /* enable */
+		writel(data, ctl_base + CMD_COMPRESSION_MODE_CTRL);
+        }
+}
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 1031562..f7115c1 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -498,7 +498,8 @@
 	return status;
 }
 
-int mdss_dsi_video_mode_config(uint16_t disp_width,
+int mdss_dsi_video_mode_config(struct msm_panel_info *pinfo,
+	uint16_t disp_width,
 	uint16_t disp_height,
 	uint16_t img_width,
 	uint16_t img_height,
@@ -521,6 +522,10 @@
 
 #if (DISPLAY_TYPE_MDSS == 1)
 	int last_line_interleave_en = 0;
+	struct dsc_desc *dsc = NULL;
+
+	if (pinfo->compression_mode == COMPRESSION_DSC)
+		dsc = &pinfo->dsc;
 
 	/*Check if EOF_BLLP_PWR_MODE bit is set*/
 	if(eof_bllp_pwr & 0x8)
@@ -599,6 +604,10 @@
 
 	writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4
 			| 0x103, ctl_base + CTRL);
+	if (dsc) {
+		if (dsc->dsi_dsc_config)
+			dsc->dsi_dsc_config(pinfo->mipi.ctl_base, DSI_VIDEO_MODE, dsc);
+	}
 #endif
 
 	return status;
@@ -609,6 +618,8 @@
 	int ret = NO_ERROR;
 	struct msm_panel_info *pinfo;
 	struct mipi_panel_info *mipi;
+	struct dsc_desc *dsc = NULL;
+	struct mipi_dsi_cmd cmd;
 
 #if (DISPLAY_TYPE_MDSS == 1)
 	if (!panel)
@@ -617,6 +628,15 @@
 	pinfo = &(panel->panel_info);
 	mipi = &(pinfo->mipi);
 
+
+	if (pinfo->compression_mode == COMPRESSION_DSC) {
+		dsc = &pinfo->dsc;
+		if (dsc) {
+			if (dsc->dsc2buf)
+				dsc->dsc2buf(pinfo);
+		}
+	}
+
 	dprintf(SPEW, "ctl_base=0x%08x, phy_base=0x%08x\n", mipi->ctl_base,
 		mipi->phy_base);
 
@@ -649,6 +669,13 @@
 		}
 	}
 
+	if (dsc) {
+		cmd.size = DCS_HDR_LEN + DSC_PPS_LEN;
+		cmd.payload = dsc->pps_buf;
+		cmd.wait = 0x10;
+		mdss_dsi_cmds_tx(mipi, &cmd, 1, mipi->broadcast);
+	}
+
 	if (pinfo->rotate && panel->rotate)
 		pinfo->rotate();
 #endif
@@ -671,7 +698,8 @@
 	return ret;
 }
 
-int mdss_dsi_cmd_mode_config(uint16_t disp_width,
+int mdss_dsi_cmd_mode_config(struct msm_panel_info *pinfo,
+	uint16_t disp_width,
 	uint16_t disp_height,
 	uint16_t img_width,
 	uint16_t img_height,
@@ -682,6 +710,8 @@
 	uint32_t ctl_base)
 {
 	uint16_t dst_fmt = 0;
+	struct dsc_desc *dsc = NULL;
+	unsigned int data;
 
 	switch (dst_format) {
 	case DSI_VIDEO_DST_FORMAT_RGB565:
@@ -717,14 +747,37 @@
 	writel(0x02020202, ctl_base + INT_CTRL);
 
 	writel(dst_fmt, ctl_base + COMMAND_MODE_MDP_CTRL);
-	writel((img_width * ystride + 1) << 16 | 0x0039,
-	       ctl_base + COMMAND_MODE_MDP_STREAM0_CTRL);
-	writel((img_width * ystride + 1) << 16 | 0x0039,
-	       ctl_base + COMMAND_MODE_MDP_STREAM1_CTRL);
-	writel(img_height << 16 | img_width,
-	       ctl_base + COMMAND_MODE_MDP_STREAM0_TOTAL);
-	writel(img_height << 16 | img_width,
-	       ctl_base + COMMAND_MODE_MDP_STREAM1_TOTAL);
+
+	if (pinfo->compression_mode == COMPRESSION_DSC)
+		dsc = &pinfo->dsc;
+
+	if (dsc) {
+		data = dsc->bytes_per_pkt;
+		if (pinfo->mipi.insert_dcs_cmd)
+			data++;
+		data <<= 16;
+		data |= 0x039;
+		writel(data, ctl_base + COMMAND_MODE_MDP_STREAM0_CTRL);
+		writel(data, ctl_base + COMMAND_MODE_MDP_STREAM1_CTRL);
+		data = dsc->pic_height << 16;
+		data |= dsc->pclk_per_line;
+		writel(data, ctl_base + COMMAND_MODE_MDP_STREAM0_TOTAL);
+		writel(data, ctl_base + COMMAND_MODE_MDP_STREAM1_TOTAL);
+
+		if (dsc->dsi_dsc_config)
+			dsc->dsi_dsc_config(pinfo->mipi.ctl_base, DSI_VIDEO_MODE, dsc);
+	} else {
+
+		writel((img_width * ystride + 1) << 16 | 0x0039,
+		       ctl_base + COMMAND_MODE_MDP_STREAM0_CTRL);
+		writel((img_width * ystride + 1) << 16 | 0x0039,
+		       ctl_base + COMMAND_MODE_MDP_STREAM1_CTRL);
+		writel(img_height << 16 | img_width,
+		       ctl_base + COMMAND_MODE_MDP_STREAM0_TOTAL);
+		writel(img_height << 16 | img_width,
+		       ctl_base + COMMAND_MODE_MDP_STREAM1_TOTAL);
+	}
+
 	writel(0x13c2c, ctl_base + COMMAND_MODE_MDP_DCS_CMD_CTRL);
 	writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 | 0x105,
 	       ctl_base + CTRL);
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index d1ebd05..eacc445 100644
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -553,6 +553,7 @@
 			$(LOCAL_DIR)/mdp5.o \
 			$(LOCAL_DIR)/display.o \
 			$(LOCAL_DIR)/mipi_dsi.o \
+			$(LOCAL_DIR)/mipi_dsc.o \
 			$(LOCAL_DIR)/mipi_dsi_phy.o \
 			$(LOCAL_DIR)/mipi_dsi_autopll_thulium.o
 endif
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index aa8cd1f..7fbe57f 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -653,4 +653,5 @@
 uint32_t smem_get_ram_ptable_len(void);
 void* smem_get_alloc_entry(smem_mem_type_t type, uint32_t* size);
 uint32_t get_ddr_start();
+uint64_t smem_get_ddr_size();
 #endif				/* __PLATFORM_MSM_SHARED_SMEM_H */
diff --git a/platform/msm_shared/smem_ptable.c b/platform/msm_shared/smem_ptable.c
index 647b0dc..4ed47b7 100644
--- a/platform/msm_shared/smem_ptable.c
+++ b/platform/msm_shared/smem_ptable.c
@@ -325,3 +325,25 @@
 	ASSERT("DDR Start Mem Not found\n");
 	return 0;
 }
+
+uint64_t smem_get_ddr_size()
+{
+	uint32_t i;
+	ram_partition ptn_entry;
+	uint32_t len = 0;
+	uint64_t size = 0;
+
+	ASSERT(smem_ram_ptable_init_v1());
+
+	len = smem_get_ram_ptable_len();
+
+	/* Determine the Start addr of the DDR RAM */
+	for(i = 0; i < len; i++)
+	{
+		smem_get_ram_ptable_entry(&ptn_entry, i);
+		if(ptn_entry.type == SYS_MEMORY && ptn_entry.category == SDRAM)
+			size += ptn_entry.size;
+	}
+
+	return size;
+}
diff --git a/platform/msm_shared/usb30_udc.c b/platform/msm_shared/usb30_udc.c
index 49d47d1..f175cb8 100644
--- a/platform/msm_shared/usb30_udc.c
+++ b/platform/msm_shared/usb30_udc.c
@@ -1382,8 +1382,8 @@
 	if ((len > 255) || (len < 2) || (num > 255) || (type > 255))
 		return 0;
 
-	if (!(desc = malloc(sizeof(struct udc_descriptor) + len)))
-		return 0;
+	desc = malloc(sizeof(struct udc_descriptor) + len);
+	ASSERT(desc);
 
 	desc->next    = 0;
 	desc->tag     = (type << 8) | num;
diff --git a/project/msm8952.mk b/project/msm8952.mk
index 2a88469..23bff86 100644
--- a/project/msm8952.mk
+++ b/project/msm8952.mk
@@ -60,6 +60,8 @@
 DEFINES += SMD_SUPPORT=1
 endif
 
+ENABLE_MDTP_SUPPORT := 1
+
 ifeq ($(ENABLE_MDTP_SUPPORT),1)
 DEFINES += MDTP_SUPPORT=1
 DEFINES += MDTP_EFUSE_ADDRESS=0x0C858250 # QFPROM_RAW_QC_SPARE_REG_LSB_ADDR
diff --git a/project/msm8996.mk b/project/msm8996.mk
index b7beef7..2669b56 100644
--- a/project/msm8996.mk
+++ b/project/msm8996.mk
@@ -36,10 +36,6 @@
 
 DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
 
-DEFINES += ABOOT_FORCE_KERNEL_ADDR=0x20008000
-DEFINES += ABOOT_FORCE_RAMDISK_ADDR=0x22200000
-DEFINES += ABOOT_FORCE_TAGS_ADDR=0x22000000
-DEFINES += ABOOT_FORCE_KERNEL64_ADDR=0x20080000
 DEFINES += USB_RESET_FROM_CLK=1
 DEFINES += USE_BOOTDEV_CMDLINE=1
 DEFINES += USE_RPMB_FOR_DEVINFO=1
diff --git a/target/msm8909/init.c b/target/msm8909/init.c
index ec1a568..72506f3 100644
--- a/target/msm8909/init.c
+++ b/target/msm8909/init.c
@@ -61,6 +61,7 @@
 #define PMIC_ARB_CHANNEL_NUM    0
 #define PMIC_ARB_OWNER_ID       0
 #define TLMM_VOL_UP_BTN_GPIO    90
+#define TLMM_VOL_DOWN_BTN_GPIO  91
 
 #if PON_VIB_SUPPORT
 #define VIBRATE_TIME    250
@@ -74,6 +75,7 @@
 #define CE_READ_PIPE_LOCK_GRP   0
 #define CE_WRITE_PIPE_LOCK_GRP  0
 #define CE_ARRAY_SIZE           20
+#define SUB_TYPE_SKUT           0x0A
 
 extern void smem_ptable_init(void);
 extern void smem_add_modem_partitions(struct ptable *flash_ptable);
@@ -222,8 +224,24 @@
 /* Return 1 if vol_down pressed */
 uint32_t target_volume_down()
 {
-	/* Volume down button tied in with PMIC RESIN. */
-	return pm8x41_resin_status();
+	if ((board_hardware_id() == HW_PLATFORM_QRD) &&
+			(board_hardware_subtype() == SUB_TYPE_SKUT)) {
+		uint32_t status = 0;
+
+		gpio_tlmm_config(TLMM_VOL_DOWN_BTN_GPIO, 0, GPIO_INPUT, GPIO_PULL_UP, GPIO_2MA, GPIO_ENABLE);
+
+		/* Wait for the gpio config to take effect - debounce time */
+		thread_sleep(10);
+
+		/* Get status of GPIO */
+		status = gpio_status(TLMM_VOL_DOWN_BTN_GPIO);
+
+		/* Active low signal. */
+		return !status;
+	} else {
+		/* Volume down button tied in with PMIC RESIN. */
+		return pm8x41_resin_status();
+	}
 }
 
 static void target_keystatus()
diff --git a/target/msm8909/target_display.c b/target/msm8909/target_display.c
index 6a7f3b8..803c5f2 100755
--- a/target/msm8909/target_display.c
+++ b/target/msm8909/target_display.c
@@ -247,7 +247,7 @@
 		 * Enable auto functional gating
 		 * on DSI CMD AXI fetch from DDR
 		 */
-		writel(0x3ffff, MDP_CGC_EN);
+		writel(0x3fbff, MDP_CGC_EN);
 		ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
 		if (ret) {
 			dprintf(CRITICAL,
diff --git a/target/msm8916/oem_panel.c b/target/msm8916/oem_panel.c
index 3d57f24..090a1b0 100644
--- a/target/msm8916/oem_panel.c
+++ b/target/msm8916/oem_panel.c
@@ -744,20 +744,8 @@
 		}
 		break;
 	case HW_PLATFORM_SBC:
-		if (platform_is_apq8016()) {
-			/* Set Switch GPIO to DSI2HDMI mode */
-			target_set_switch_gpio(1);
-			/* ADV7533 DSI to HDMI Bridge Chip Connected */
-			mipi_dsi_i2c_device_init();
-			/* Read ADV Chip ID */
-			if (!mipi_dsi_i2c_read_byte(ADV7533_MAIN, 0x00, &rev)) {
-				dprintf(INFO, "ADV7533 Rev ID: 0x%x\n",rev);
-			} else {
-				dprintf(CRITICAL, "error reading Rev ID from bridge chip\n");
-				return PANEL_TYPE_UNKNOWN;
-			}
-			panel_id = ADV7533_720P_VIDEO_PANEL;
-		}
+		if (platform_is_apq8016())
+			panel_id = ADV7533_1080P_VIDEO_PANEL;
 		break;
 	default:
 		dprintf(CRITICAL, "Display not enabled for %d HW type\n",
@@ -766,6 +754,20 @@
 	}
 
 panel_init:
+	if (platform_is_apq8016() && (hw_id == HW_PLATFORM_SBC)) {
+		/* Set Switch GPIO to DSI2HDMI mode */
+		target_set_switch_gpio(1);
+		/* ADV7533 DSI to HDMI Bridge Chip Connected */
+		mipi_dsi_i2c_device_init();
+		/* Read ADV Chip ID */
+		if (!mipi_dsi_i2c_read_byte(ADV7533_MAIN, 0x00, &rev)) {
+			dprintf(INFO, "ADV7533 Rev ID: 0x%x\n",rev);
+		} else {
+			dprintf(CRITICAL, "error reading Rev ID from bridge chip\n");
+			return PANEL_TYPE_UNKNOWN;
+		}
+	}
+
 	/*
 	 * Update all data structures after 'panel_init' label. Only panel
 	 * selection is supposed to happen before that.
diff --git a/target/msm8952/target_display.c b/target/msm8952/target_display.c
index adc5815..8773514 100644
--- a/target/msm8952/target_display.c
+++ b/target/msm8952/target_display.c
@@ -51,6 +51,11 @@
 #include "include/display_resource.h"
 #include "gcdb_display.h"
 
+#define DSC_CMD_PANEL "dsc_cmd_panel"
+#define DSC_VID_PANEL "dsc_vid_panel"
+#define DSC_CMD_PANEL_STRING "1:dsi:0:none:1:qcom,mdss_dsi_nt35597_dsc_wqxga_cmd"
+#define DSC_VID_PANEL_STRING "1:dsi:0:none:1:qcom,mdss_dsi_nt35597_dsc_wqxga_video"
+
 /*---------------------------------------------------------------------------*/
 /* GPIO configuration                                                        */
 /*---------------------------------------------------------------------------*/
@@ -508,7 +513,11 @@
 		qpnp_ibb_enable(true); /*5V boost*/
 		mdelay(50);
 	} else {
-		regulator_disable(ldo_num);
+		/*
+		 * LDO1, LDO2 and LDO6 are shared with other subsystems.
+		 * Do not disable them.
+		 */
+		regulator_disable(REG_LDO17);
 	}
 
 	return NO_ERROR;
@@ -516,7 +525,35 @@
 
 bool target_display_panel_node(char *pbuf, uint16_t buf_size)
 {
-	return gcdb_display_cmdline_arg(pbuf, buf_size);
+	int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX);
+	bool ret = true;
+	struct oem_panel_data oem = mdss_dsi_get_oem_data();
+
+	if (!strcmp(oem.panel, DSC_CMD_PANEL)) {
+		if (buf_size < (prefix_string_len +
+			strlen(DSC_CMD_PANEL_STRING))) {
+			dprintf(CRITICAL, "DSC command line argument is greater than buffer size\n");
+			return false;
+		}
+		strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size);
+		buf_size -= prefix_string_len;
+		pbuf += prefix_string_len;
+		strlcpy(pbuf, DSC_CMD_PANEL_STRING, buf_size);
+	} else if (!strcmp(oem.panel, DSC_VID_PANEL)) {
+		if (buf_size < (prefix_string_len +
+			strlen(DSC_VID_PANEL_STRING))) {
+			dprintf(CRITICAL, "DSC command line argument is greater than buffer size\n");
+			return false;
+		}
+		strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size);
+		buf_size -= prefix_string_len;
+		pbuf += prefix_string_len;
+		strlcpy(pbuf, DSC_VID_PANEL_STRING, buf_size);
+	} else {
+		ret = gcdb_display_cmdline_arg(pbuf, buf_size);
+	}
+
+	return ret;
 }
 
 void target_display_init(const char *panel_name)
@@ -531,6 +568,8 @@
 	if (!strcmp(oem.panel, NO_PANEL_CONFIG)
 		|| !strcmp(oem.panel, SIM_VIDEO_PANEL)
 		|| !strcmp(oem.panel, SIM_CMD_PANEL)
+		|| !strcmp(oem.panel, DSC_CMD_PANEL)
+		|| !strcmp(oem.panel, DSC_VID_PANEL)
 		|| oem.skip) {
 		dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n",
 			oem.panel);
diff --git a/target/msm8994/oem_panel.c b/target/msm8994/oem_panel.c
index de71ef9..1470faf 100644
--- a/target/msm8994/oem_panel.c
+++ b/target/msm8994/oem_panel.c
@@ -251,6 +251,8 @@
 			= JDI_4K_DUALDSI_VIDEO_OFF_COMMAND;
 		memcpy(phy_db->timing,
 			jdi_4k_dualdsi_video_timings, TIMING_SIZE);
+
+		pinfo->compression_mode = COMPRESSION_FBC;
 		memcpy(&panelstruct->fbcinfo, &jdi_4k_dualdsi_video_fbc,
 				sizeof(struct fb_compression));
 		break;
diff --git a/target/msm8996/init.c b/target/msm8996/init.c
index 488ed47..a627874 100644
--- a/target/msm8996/init.c
+++ b/target/msm8996/init.c
@@ -151,7 +151,8 @@
 	}
 
 #if ENABLE_WBC
-	pm_appsbl_set_dcin_suspend(1);
+	if (board_hardware_id() == HW_PLATFORM_MTP)
+		pm_appsbl_set_dcin_suspend(1);
 #endif
 
 	/* Tear down glink channels */
@@ -253,7 +254,8 @@
 	 * Charging should happen as early as possible, any other driver
 	 * initialization before this should consider the power impact
 	 */
-	pm_appsbl_chg_check_weak_battery_status(1);
+	if (board_hardware_id() == HW_PLATFORM_MTP)
+		pm_appsbl_chg_check_weak_battery_status(1);
 #endif
 
 	target_keystatus();
diff --git a/target/msm8996/oem_panel.c b/target/msm8996/oem_panel.c
index 654c849..3fbb979 100644
--- a/target/msm8996/oem_panel.c
+++ b/target/msm8996/oem_panel.c
@@ -41,12 +41,15 @@
 #include "target/display.h"
 #include "panel_display.h"
 #include <mipi_dsi.h>
+#include <mdp5.h>
 
 /*---------------------------------------------------------------------------*/
 /* GCDB Panel Database                                                       */
 /*---------------------------------------------------------------------------*/
 #include "include/panel_nt35597_wqxga_dualdsi_video.h"
 #include "include/panel_nt35597_wqxga_dualdsi_cmd.h"
+#include "include/panel_nt35597_wqxga_dsc_video.h"
+#include "include/panel_nt35597_wqxga_dsc_cmd.h"
 #include "include/panel_sharp_wqxga_dualdsi_video.h"
 #include "include/panel_jdi_qhd_dualdsi_video.h"
 #include "include/panel_jdi_qhd_dualdsi_cmd.h"
@@ -55,9 +58,11 @@
 /* static panel selection variable                                           */
 /*---------------------------------------------------------------------------*/
 enum {
+	SHARP_WQXGA_DUALDSI_VIDEO_PANEL,
 	NT35597_WQXGA_DUALDSI_VIDEO_PANEL,
 	NT35597_WQXGA_DUALDSI_CMD_PANEL,
-	SHARP_WQXGA_DUALDSI_VIDEO_PANEL,
+	NT35597_WQXGA_DSC_VIDEO_PANEL,
+	NT35597_WQXGA_DSC_CMD_PANEL,
 	JDI_QHD_DUALDSI_VIDEO_PANEL,
 	JDI_QHD_DUALDSI_CMD_PANEL,
 	UNKNOWN_PANEL
@@ -68,9 +73,11 @@
  * Any panel in this list can be selected using fastboot oem command.
  */
 static struct panel_list supp_panels[] = {
+	{"sharp_wqxga_dualdsi_video", SHARP_WQXGA_DUALDSI_VIDEO_PANEL},
 	{"nt35597_wqxga_dualdsi_video", NT35597_WQXGA_DUALDSI_VIDEO_PANEL},
 	{"nt35597_wqxga_dualdsi_cmd", NT35597_WQXGA_DUALDSI_CMD_PANEL},
-	{"sharp_wqxga_dualdsi_video", SHARP_WQXGA_DUALDSI_VIDEO_PANEL},
+	{"nt35597_wqxga_dsc_video", NT35597_WQXGA_DSC_VIDEO_PANEL},
+	{"nt35597_wqxga_dsc_cmd", NT35597_WQXGA_DSC_CMD_PANEL},
 	{"jdi_qhd_dualdsi_video", JDI_QHD_DUALDSI_VIDEO_PANEL},
 	{"jdi_qhd_dualdsi_cmd", JDI_QHD_DUALDSI_CMD_PANEL},
 };
@@ -200,6 +207,84 @@
 			MAX_TIMING_CONFIG * sizeof(uint32_t));
 		pinfo->mipi.tx_eot_append = true;
 		break;
+	case NT35597_WQXGA_DSC_VIDEO_PANEL:
+		pan_type = PANEL_TYPE_DSI;
+		pinfo->lcd_reg_en = 0;
+		panelstruct->paneldata    = &nt35597_wqxga_dsc_video_panel_data;
+		panelstruct->panelres     = &nt35597_wqxga_dsc_video_panel_res;
+		panelstruct->color        = &nt35597_wqxga_dsc_video_color;
+		panelstruct->videopanel   = &nt35597_wqxga_dsc_video_video_panel;
+		panelstruct->commandpanel = &nt35597_wqxga_dsc_video_command_panel;
+		panelstruct->state        = &nt35597_wqxga_dsc_video_state;
+		panelstruct->laneconfig   = &nt35597_wqxga_dsc_video_lane_config;
+		panelstruct->paneltiminginfo
+			= &nt35597_wqxga_dsc_video_timing_info;
+		panelstruct->panelresetseq
+					 = &nt35597_wqxga_dsc_video_reset_seq;
+		panelstruct->backlightinfo = &nt35597_wqxga_dsc_video_backlight;
+
+		pinfo->labibb = &nt35597_wqxga_dsc_video_labibb;
+
+		pinfo->mipi.panel_on_cmds
+			= nt35597_wqxga_dsc_video_on_command;
+		pinfo->mipi.num_of_panel_on_cmds
+			= NT35597_WQXGA_DSC_VIDEO_ON_COMMAND;
+		pinfo->mipi.panel_off_cmds
+			= nt35597_wqxga_dsc_video_off_command;
+		pinfo->mipi.num_of_panel_off_cmds
+			= NT35597_WQXGA_DSC_VIDEO_OFF_COMMAND;
+		memcpy(phy_db->timing,
+			nt35597_wqxga_dsc_thulium_video_timings,
+			MAX_TIMING_CONFIG * sizeof(uint32_t));
+		pinfo->mipi.tx_eot_append = true;
+
+		pinfo->compression_mode = COMPRESSION_DSC;
+		memcpy(&panelstruct->dsc_paras, &nt35597_wqxga_dsc_video_paras,
+				sizeof(struct dsc_parameters));
+		pinfo->dsc.parameter_calc =  mdss_dsc_parameters_calc;
+		pinfo->dsc.dsc2buf = mdss_dsc_to_buf;
+		pinfo->dsc.dsi_dsc_config = mdss_dsc_dsi_config;
+		pinfo->dsc.mdp_dsc_config = mdss_dsc_mdp_config;
+		break;
+	case NT35597_WQXGA_DSC_CMD_PANEL:
+		pan_type = PANEL_TYPE_DSI;
+		pinfo->lcd_reg_en = 0;
+		panelstruct->paneldata    = &nt35597_wqxga_dsc_cmd_panel_data;
+		panelstruct->panelres     = &nt35597_wqxga_dsc_cmd_panel_res;
+		panelstruct->color        = &nt35597_wqxga_dsc_cmd_color;
+		panelstruct->videopanel   = &nt35597_wqxga_dsc_cmd_video_panel;
+		panelstruct->commandpanel = &nt35597_wqxga_dsc_cmd_command_panel;
+		panelstruct->state        = &nt35597_wqxga_dsc_cmd_state;
+		panelstruct->laneconfig   = &nt35597_wqxga_dsc_cmd_lane_config;
+		panelstruct->paneltiminginfo
+			= &nt35597_wqxga_dsc_cmd_timing_info;
+		panelstruct->panelresetseq
+					 = &nt35597_wqxga_dsc_cmd_reset_seq;
+		panelstruct->backlightinfo = &nt35597_wqxga_dsc_cmd_backlight;
+
+		pinfo->labibb = &nt35597_wqxga_dsc_cmd_labibb;
+
+		pinfo->mipi.panel_on_cmds
+			= nt35597_wqxga_dsc_cmd_on_command;
+		pinfo->mipi.num_of_panel_on_cmds
+			= NT35597_WQXGA_DSC_CMD_ON_COMMAND;
+		pinfo->mipi.panel_off_cmds
+			= nt35597_wqxga_dsc_cmd_off_command;
+		pinfo->mipi.num_of_panel_off_cmds
+			= NT35597_WQXGA_DSC_CMD_OFF_COMMAND;
+		memcpy(phy_db->timing,
+			nt35597_wqxga_dsc_thulium_cmd_timings,
+			MAX_TIMING_CONFIG * sizeof(uint32_t));
+		pinfo->mipi.tx_eot_append = true;
+
+		pinfo->compression_mode = COMPRESSION_DSC;
+		memcpy(&panelstruct->dsc_paras, &nt35597_wqxga_dsc_cmd_paras,
+				sizeof(struct dsc_parameters));
+		pinfo->dsc.parameter_calc =  mdss_dsc_parameters_calc;
+		pinfo->dsc.dsc2buf = mdss_dsc_to_buf;
+		pinfo->dsc.dsi_dsc_config = mdss_dsc_dsi_config;
+		pinfo->dsc.mdp_dsc_config = mdss_dsc_mdp_config;
+		break;
 	case JDI_QHD_DUALDSI_VIDEO_PANEL:
 		pan_type = PANEL_TYPE_DSI;
 		pinfo->lcd_reg_en = 1;
diff --git a/target/msm8996/rules.mk b/target/msm8996/rules.mk
index a0c3a8d..d9349f7 100644
--- a/target/msm8996/rules.mk
+++ b/target/msm8996/rules.mk
@@ -12,7 +12,6 @@
 
 SCRATCH_ADDR := 0x91100000
 SCRATCH_SIZE := 750
-KERNEL_ADDR  := 0x20000000
 KERNEL_SIZE  := 512
 # LPAE supports only 32 virtual address, L1 pt size is 4
 L1_PT_SZ     := 4
@@ -37,7 +36,6 @@
 	MEMBASE=$(MEMBASE) \
 	BASE_ADDR=$(BASE_ADDR) \
 	TAGS_ADDR=$(TAGS_ADDR) \
-	KERNEL_ADDR=$(KERNEL_ADDR) \
 	KERNEL_SIZE=$(KERNEL_SIZE) \
 	RAMDISK_ADDR=$(RAMDISK_ADDR) \
 	SCRATCH_ADDR=$(SCRATCH_ADDR) \