| commit | 302a6330a4567ade1d864fb94948bd73fc37b2c7 | [log] [tgz] |
|---|---|---|
| author | Shashank Mittal <mittals@codeaurora.org> | Wed May 04 10:32:48 2011 -0700 |
| committer | Murali Nalajala <mnalajal@codeaurora.org> | Thu May 12 14:28:48 2011 +0530 |
| tree | f1c6a3e763f7f11e995627ad815ed8aedb3f0676 | |
| parent | d120bb23ae33fd86f6798ce4e999d8fba0c654ee [diff] |
msm7x27a: Fix acpuclock code for 7x27a. In 7x27a, A11S_CLK_SEL register supports new settings. While configuring AHB_CLK_DIV and CLK_SEL_SRC, other bits should remain unaffected. Change-Id: Ic258fe5f28302ff9b47db6515359dc2dafcfcec9