diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
old mode 100755
new mode 100644
index dd8b1ba..5d036f5
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -312,11 +312,13 @@
 			break;
 	}
 
-	if ((strstr(cmdline, DISPLAY_DEFAULT_PREFIX) == NULL) &&
-		target_display_panel_node(device.display_panel,
-		display_panel_buf, MAX_PANEL_BUF_SIZE) &&
-		strlen(display_panel_buf)) {
-		cmdline_len += strlen(display_panel_buf);
+	if (cmdline) {
+		if ((strstr(cmdline, DISPLAY_DEFAULT_PREFIX) == NULL) &&
+			target_display_panel_node(device.display_panel,
+			display_panel_buf, MAX_PANEL_BUF_SIZE) &&
+			strlen(display_panel_buf)) {
+			cmdline_len += strlen(display_panel_buf);
+		}
 	}
 
 	if (target_warm_boot()) {
@@ -326,11 +328,13 @@
 
 	if (cmdline_len > 0) {
 		const char *src;
-		unsigned char *dst = (unsigned char*) malloc((cmdline_len + 4) & (~3));
-		ASSERT(dst != NULL);
+		unsigned char *dst;
+
+		cmdline_final = (unsigned char*) malloc((cmdline_len + 4) & (~3));
+		ASSERT(cmdline_final != NULL);
+		dst = cmdline_final;
 
 		/* Save start ptr for debug print */
-		cmdline_final = dst;
 		if (have_cmdline) {
 			src = cmdline;
 			while ((*dst++ = *src++));
@@ -469,7 +473,7 @@
 	if (boot_dev_buf)
 		free(boot_dev_buf);
 
-	dprintf(INFO, "cmdline: %s\n", cmdline_final);
+	dprintf(INFO, "cmdline: %s\n", cmdline_final ? cmdline_final : "");
 	return cmdline_final;
 }
 
@@ -590,6 +594,7 @@
 	generate_atags(tags, final_cmdline, ramdisk, ramdisk_size);
 #endif
 
+	free(final_cmdline);
 	/* Perform target specific cleanup */
 	target_uninit();
 
@@ -630,7 +635,7 @@
 int check_aboot_addr_range_overlap(uint32_t start, uint32_t size)
 {
 	/* Check for boundary conditions. */
-	if ((start + size) < start)
+	if ((UINT_MAX - start) < size)
 		return -1;
 
 	/* Check for memory overlap. */
@@ -1794,44 +1799,47 @@
 		lun_set = true;
 	}
 
-	if (!strcmp(pname, "partition"))
+	if (pname)
 	{
-		dprintf(INFO, "Attempt to write partition image.\n");
-		if (write_partition(sz, (unsigned char *) data)) {
-			fastboot_fail("failed to write partition");
-			return;
-		}
-	}
-	else
-	{
-		index = partition_get_index(pname);
-		ptn = partition_get_offset(index);
-		if(ptn == 0) {
-			fastboot_fail("partition table doesn't exist");
-			return;
-		}
-
-		if (!strcmp(pname, "boot") || !strcmp(pname, "recovery")) {
-			if (memcmp((void *)data, BOOT_MAGIC, BOOT_MAGIC_SIZE)) {
-				fastboot_fail("image is not a boot image");
+		if (!strcmp(pname, "partition"))
+		{
+			dprintf(INFO, "Attempt to write partition image.\n");
+			if (write_partition(sz, (unsigned char *) data)) {
+				fastboot_fail("failed to write partition");
 				return;
 			}
 		}
-
-		if(!lun_set)
+		else
 		{
-			lun = partition_get_lun(index);
-			mmc_set_lun(lun);
-		}
+			index = partition_get_index(pname);
+			ptn = partition_get_offset(index);
+			if(ptn == 0) {
+				fastboot_fail("partition table doesn't exist");
+				return;
+			}
 
-		size = partition_get_size(index);
-		if (ROUND_TO_PAGE(sz,511) > size) {
-			fastboot_fail("size too large");
-			return;
-		}
-		else if (mmc_write(ptn , sz, (unsigned int *)data)) {
-			fastboot_fail("flash write failure");
-			return;
+			if (!strcmp(pname, "boot") || !strcmp(pname, "recovery")) {
+				if (memcmp((void *)data, BOOT_MAGIC, BOOT_MAGIC_SIZE)) {
+					fastboot_fail("image is not a boot image");
+					return;
+				}
+			}
+
+			if(!lun_set)
+			{
+				lun = partition_get_lun(index);
+				mmc_set_lun(lun);
+			}
+
+			size = partition_get_size(index);
+			if (ROUND_TO_PAGE(sz,511) > size) {
+				fastboot_fail("size too large");
+				return;
+			}
+			else if (mmc_write(ptn , sz, (unsigned int *)data)) {
+				fastboot_fail("flash write failure");
+				return;
+			}
 		}
 	}
 	fastboot_okay("");
@@ -2492,6 +2500,13 @@
 
 	memset(display_panel_buf, '\0', MAX_PANEL_BUF_SIZE);
 
+	/*
+	 * Check power off reason if user force reset,
+	 * if yes phone will do normal boot.
+	 */
+	if (is_user_force_reset())
+		goto normal_boot;
+
 	/* Check if we should do something other than booting up */
 	if (keys_get_state(KEY_VOLUMEUP) && keys_get_state(KEY_VOLUMEDOWN))
 	{
@@ -2527,6 +2542,7 @@
 		boot_into_fastboot = true;
 	}
 
+normal_boot:
 	if (!boot_into_fastboot)
 	{
 		if (target_is_emmc_boot())
diff --git a/app/aboot/recovery.c b/app/aboot/recovery.c
index 817a6be..3c42902 100644
--- a/app/aboot/recovery.c
+++ b/app/aboot/recovery.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
 
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -32,6 +32,8 @@
 #include <string.h>
 #include <kernel/thread.h>
 #include <arch/ops.h>
+#include <arch/defines.h>
+#include <malloc.h>
 
 #include <dev/flash.h>
 #include <lib/ptable.h>
@@ -409,43 +411,54 @@
 {
 	char *ptn_name = "misc";
 	unsigned long long ptn = 0;
-	unsigned int size = ROUND_TO_PAGE(sizeof(*in),511);
-	unsigned char data[size];
+	unsigned int size;
 	int index = INVALID_PTN;
 
+	size = mmc_get_device_blocksize();
 	index = partition_get_index((unsigned char *) ptn_name);
 	ptn = partition_get_offset(index);
 	if(ptn == 0) {
 		dprintf(CRITICAL,"partition %s doesn't exist\n",ptn_name);
 		return -1;
 	}
-	if (mmc_read(ptn , (unsigned int*)data, size)) {
+	if (mmc_read(ptn , (unsigned int*)in, size)) {
 		dprintf(CRITICAL,"mmc read failure %s %d\n",ptn_name, size);
 		return -1;
 	}
-	memcpy(in, data, sizeof(*in));
+
 	return 0;
 }
 
 int _emmc_recovery_init(void)
 {
 	int update_status = 0;
-	struct recovery_message msg;
+	struct recovery_message *msg;
+	uint32_t block_size = 0;
+
+	block_size = mmc_get_device_blocksize();
 
 	// get recovery message
-	if(emmc_get_recovery_msg(&msg))
+	msg = (struct recovery_message *)memalign(CACHE_LINE, block_size);
+	ASSERT(msg);
+
+	if(emmc_get_recovery_msg(msg))
+	{
+		if(msg)
+			free(msg);
 		return -1;
-	msg.command[sizeof(msg.command)-1] = '\0'; //Ensure termination
-	if (msg.command[0] != 0 && msg.command[0] != 255) {
-		dprintf(INFO,"Recovery command: %d %s\n",
-			sizeof(msg.command), msg.command);
 	}
 
-	if (!strncmp(msg.command, "boot-recovery", strlen("boot-recovery"))) {
+	msg->command[sizeof(msg->command)-1] = '\0'; //Ensure termination
+	if (msg->command[0] != 0 && msg->command[0] != 255) {
+		dprintf(INFO,"Recovery command: %d %s\n",
+			sizeof(msg->command), msg->command);
+	}
+
+	if (!strcmp(msg->command, "boot-recovery")) {
 		boot_into_recovery = 1;
 	}
 
-	if (!strcmp("update-radio",msg.command))
+	if (!strcmp("update-radio",msg->command))
 	{
 		/* We're now here due to radio update, so check for update status */
 		int ret = get_boot_info_apps(UPDATE_STATUS, (unsigned int *) &update_status);
@@ -453,28 +466,32 @@
 		if(!ret && (update_status & 0x01))
 		{
 			dprintf(INFO,"radio update success\n");
-			strlcpy(msg.status, "OKAY", sizeof(msg.status));
+			strlcpy(msg->status, "OKAY", sizeof(msg->status));
 		}
 		else
 		{
 			dprintf(INFO,"radio update failed\n");
-			strlcpy(msg.status, "failed-update", sizeof(msg.status));
+			strlcpy(msg->status, "failed-update", sizeof(msg->status));
 		}
 		boot_into_recovery = 1;		// Boot in recovery mode
 	}
-	if (!strcmp("reset-device-info",msg.command))
+	if (!strcmp("reset-device-info",msg->command))
 	{
 		reset_device_info();
 	}
-	if (!strcmp("root-detect",msg.command))
+	if (!strcmp("root-detect",msg->command))
 	{
 		set_device_root();
 	}
 	else
-		return 0;	// do nothing
+		goto out;// do nothing
 
-	strlcpy(msg.command, "", sizeof(msg.command));	// clearing recovery command
-	emmc_set_recovery_msg(&msg);	// send recovery message
+	strlcpy(msg->command, "", sizeof(msg->command));	// clearing recovery command
+	emmc_set_recovery_msg(msg);	// send recovery message
+
+out:
+	if(msg)
+		free(msg);
 	return 0;
 }
 
diff --git a/app/aboot/rules.mk b/app/aboot/rules.mk
index a26937b..5342d7a 100644
--- a/app/aboot/rules.mk
+++ b/app/aboot/rules.mk
@@ -2,6 +2,8 @@
 
 INCLUDES += -I$(LK_TOP_DIR)/platform/msm_shared/include
 
+DEFINES += ASSERT_ON_TAMPER=1
+
 OBJS += \
 	$(LOCAL_DIR)/aboot.o \
 	$(LOCAL_DIR)/fastboot.o \
diff --git a/dev/gcdb/display/gcdb_autopll.c b/dev/gcdb/display/gcdb_autopll.c
index e7d7a0e..38ba3b4 100755
--- a/dev/gcdb/display/gcdb_autopll.c
+++ b/dev/gcdb/display/gcdb_autopll.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -37,9 +37,8 @@
 
 static struct mdss_dsi_pll_config pll_data;
 
-static uint32_t calculate_bitclock(struct msm_panel_info *pinfo)
+static void calculate_bitclock(struct msm_panel_info *pinfo)
 {
-	uint32_t ret = NO_ERROR;
 	uint32_t h_period = 0, v_period = 0;
 	uint32_t width = pinfo->xres;
 
@@ -67,8 +66,6 @@
 	pll_data.byte_clock = pll_data.bit_clock >> 3;
 
 	pll_data.halfbit_clock = pll_data.bit_clock >> 1;
-
-	return ret;
 }
 
 static uint32_t calculate_div1()
@@ -140,9 +137,38 @@
 	pll_data.posdiv3--;	/* Register needs one value less */
 }
 
-static uint32_t calculate_vco(uint8_t bpp, uint8_t num_of_lanes)
+static uint32_t calculate_dec_frac_start()
 {
-	uint32_t ret = NO_ERROR;
+	uint32_t refclk = 19200000;
+	uint32_t vco_rate = pll_data.vco_clock;
+	uint32_t tmp, mod;
+
+	vco_rate /= 2;
+	pll_data.dec_start = vco_rate / refclk;
+	tmp = vco_rate % refclk; /* module, fraction */
+	tmp /= 192;
+	tmp *= 1024;
+	tmp /= 100;
+	tmp *= 1024;
+	tmp /= 1000;
+	pll_data.frac_start = tmp;
+
+	vco_rate *= 2; /* restore */
+	tmp = vco_rate / refclk;/* div 1000 first */
+	mod = vco_rate % refclk;
+	tmp *= 127;
+	mod *= 127;
+	mod /= refclk;
+	tmp += mod;
+	tmp /= 10;
+	pll_data.lock_comp = tmp;
+
+	dprintf(SPEW, "%s: dec_start=%u dec_frac=%u lock_comp=%u\n", __func__,
+		pll_data.dec_start, pll_data.frac_start, pll_data.lock_comp);
+}
+
+static uint32_t calculate_vco_28nm(uint8_t bpp, uint8_t num_of_lanes)
+{
 	uint8_t  counter = 0;
 	uint32_t temprate = 0;
 
@@ -172,7 +198,85 @@
 	/* calculate mnd and div3 for direct and indirect path */
 	calculate_div3(bpp, num_of_lanes);
 
-	return ret;
+	return NO_ERROR;
+}
+
+static uint32_t calculate_vco_20nm(uint8_t bpp, uint8_t lanes)
+{
+	uint32_t vco, dsi_clk;
+	int mod, ndiv, hr_oclk2, hr_oclk3;
+	int m = 1;
+	int n = 1;
+	int bpp_m = 3;	/* bpp = 3 */
+	int bpp_n = 1;
+
+	if (bpp == BITS_18) {
+		bpp_m = 9; /* bpp = 2.25 */
+		bpp_n = 4;
+
+		if (lanes == 2) {
+			m = 2;
+			n = 9;
+		} else if (lanes == 4) {
+			m = 4;
+			n = 9;
+		}
+	} else if (bpp == BITS_16) {
+		bpp_m = 2; /* bpp = 2 */
+		bpp_n = 1;
+		if (lanes == 3) {
+			m = 3;
+			n = 8;
+		}
+	}
+
+	hr_oclk2 = 4;
+
+	/* If bitclock is more than VCO min value */
+	if (pll_data.halfbit_clock >= HALF_VCO_MIN_CLOCK_20NM) {
+		/* Direct Mode */
+		vco  = pll_data.halfbit_clock << 1;
+		/* support vco clock to max value only */
+		if (vco > VCO_MAX_CLOCK_20NM)
+			vco = VCO_MAX_CLOCK_20NM;
+
+		pll_data.directpath = 0x0;
+		pll_data.byte_clock = vco / 2 / hr_oclk2;
+		pll_data.lp_div_mux = 0x0;
+		ndiv = 1;
+		hr_oclk3 = hr_oclk2 * m / n * bpp_m / bpp_n / lanes;
+	} else {
+		/* Indirect Mode */
+		mod =  VCO_MIN_CLOCK_20NM % (4 * pll_data.halfbit_clock );
+		ndiv = VCO_MIN_CLOCK_20NM / (4 * pll_data.halfbit_clock );
+		if (mod)
+			ndiv += 1;
+
+		vco = pll_data.halfbit_clock * 4 * ndiv;
+		pll_data.lp_div_mux = 0x1;
+		pll_data.directpath = 0x02; /* set bit 1 to enable for
+						 indirect path */
+
+		pll_data.byte_clock = vco / 4 / hr_oclk2 / ndiv;
+		hr_oclk3 = hr_oclk2 * m / n  * ndiv * 2 * bpp_m / bpp_n / lanes;
+	}
+
+	pll_data.vco_clock = vco;
+	dsi_clk = vco / 2 / hr_oclk3;
+	pll_data.ndiv = ndiv;
+	pll_data.hr_oclk2 = hr_oclk2 - 1; 	/* strat from 0 */
+	pll_data.hr_oclk3 = hr_oclk3 - 1; 	/* strat from 0 */
+
+	pll_data.pclk_m = m;		/* M */
+	pll_data.pclk_n = ~(n - m); 	/* ~(N-M) */
+	pll_data.pclk_d = ~n;		/* ~N  */
+
+	dprintf(SPEW, "%s: oclk2=%d oclk3=%d ndiv=%d vco=%u dsi_clk=%u byte_clk=%u\n",
+	__func__, hr_oclk2, hr_oclk3, ndiv, vco, dsi_clk, pll_data.byte_clock);
+
+	calculate_dec_frac_start();
+
+	return NO_ERROR;
 }
 
 uint32_t calculate_clock_config(struct msm_panel_info *pinfo)
@@ -181,7 +285,10 @@
 
 	calculate_bitclock(pinfo);
 
-	calculate_vco(pinfo->bpp, pinfo->mipi.num_of_lanes);
+	if (pinfo->mipi.mdss_dsi_phy_db->is_pll_20nm)
+		ret = calculate_vco_20nm(pinfo->bpp, pinfo->mipi.num_of_lanes);
+	else
+		ret = calculate_vco_28nm(pinfo->bpp, pinfo->mipi.num_of_lanes);
 
 	pinfo->mipi.dsi_pll_config = &pll_data;
 
diff --git a/dev/gcdb/display/gcdb_autopll.h b/dev/gcdb/display/gcdb_autopll.h
index 259abd6..ee0070d 100755
--- a/dev/gcdb/display/gcdb_autopll.h
+++ b/dev/gcdb/display/gcdb_autopll.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -43,6 +43,16 @@
 #define HALFBIT_CLOCK3 44000000  /* VCO min clock div by 8 */
 #define HALFBIT_CLOCK4 40000000  /* VCO min clock div by 9 */
 
+#define VCO_MIN_CLOCK_20NM 	1000000000
+#define VCO_MAX_CLOCK_20NM 	2000000000
+
+#define HALF_VCO_MIN_CLOCK_20NM (VCO_MIN_CLOCK_20NM >> 1)
+
+#define HALFBIT_CLOCK1_20NM 	500000000 /* VCO min clock div by 2 */
+#define HALFBIT_CLOCK2_20NM 	250000000  /* VCO min clock div by 4 */
+#define HALFBIT_CLOCK3_20NM 	125000000  /* VCO min clock div by 8 */
+#define HALFBIT_CLOCK4_20NM 	120000000  /* VCO min clock div by 9 */
+
 #define BITS_24 24
 #define BITS_18 18
 #define BITS_16 16
diff --git a/dev/gcdb/display/gcdb_display.c b/dev/gcdb/display/gcdb_display.c
index 9574a16..f41277f 100755
--- a/dev/gcdb/display/gcdb_display.c
+++ b/dev/gcdb/display/gcdb_display.c
@@ -159,7 +159,7 @@
 	return ret;
 }
 
-bool gcdb_display_cmdline_arg(char *pbuf, uint16_t buf_size)
+bool gcdb_display_cmdline_arg(char *panel_name, char *pbuf, uint16_t buf_size)
 {
 	char *dsi_id = NULL;
 	char *panel_node = NULL;
@@ -168,31 +168,32 @@
 	uint32_t arg_size = 0;
 	bool ret = true;
 	char *default_str;
-	int panel_mode = SPLIT_DISPLAY_FLAG | DUAL_PIPE_FLAG;
+	int panel_mode = SPLIT_DISPLAY_FLAG | DUAL_PIPE_FLAG | DST_SPLIT_FLAG;
 	int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX);
 
-	if (panelstruct.paneldata)
-	{
+	if (!strcmp(panel_name, SIM_VIDEO_PANEL)) {
+		dsi_id = SIM_DSI_ID;
+		panel_mode = 0;
+		panel_node = SIM_VIDEO_PANEL_NODE;
+	}  else if (!strcmp(panel_name, SIM_DUALDSI_VIDEO_PANEL)) {
+		dsi_id = SIM_DSI_ID;
+		panel_mode = 1;
+		panel_node = SIM_DUALDSI_VIDEO_PANEL_NODE;
+		slave_panel_node = SIM_DUALDSI_VIDEO_SLAVE_PANEL_NODE;
+	} else if (panelstruct.paneldata) {
 		dsi_id = panelstruct.paneldata->panel_controller;
 		panel_node = panelstruct.paneldata->panel_node_id;
 		panel_mode = panelstruct.paneldata->panel_operating_mode &
 							panel_mode;
 		slave_panel_node = panelstruct.paneldata->slave_panel_node_id;
-	}
-	else
-	{
+	} else {
 		if (target_is_edp())
-		{
 			default_str = "0:edp:";
-		}
 		else
-		{
 			default_str = "0:dsi:0:";
-		}
 
 		arg_size = prefix_string_len + strlen(default_str);
-		if (buf_size < arg_size)
-		{
+		if (buf_size < arg_size) {
 			dprintf(CRITICAL, "display command line buffer is small\n");
 			return false;
 		}
@@ -227,13 +228,10 @@
 	if (panel_mode)
 		arg_size += DSI_1_STRING_LEN + slave_panel_node_len;
 
-	if (buf_size < arg_size)
-	{
+	if (buf_size < arg_size) {
 		dprintf(CRITICAL, "display command line buffer is small\n");
 		ret = false;
-	}
-	else
-	{
+	} else {
 		strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size);
 		pbuf += prefix_string_len;
 		buf_size -= prefix_string_len;
diff --git a/dev/gcdb/display/gcdb_display.h b/dev/gcdb/display/gcdb_display.h
index 5727067..23c2811 100755
--- a/dev/gcdb/display/gcdb_display.h
+++ b/dev/gcdb/display/gcdb_display.h
@@ -57,7 +57,7 @@
 int target_ldo_ctrl(uint8_t enable);
 
 int gcdb_display_init(const char *panel_name, uint32_t rev, void *base);
-bool gcdb_display_cmdline_arg(char *pbuf, uint16_t buf_size);
+bool gcdb_display_cmdline_arg(char *panel_name, char *pbuf, uint16_t buf_size);
 void gcdb_display_shutdown();
 
 #endif /*_GCDB_DISPLAY_H_ */
diff --git a/dev/gcdb/display/include/display_resource.h b/dev/gcdb/display/include/display_resource.h
index 5caad1e..ce95769 100755
--- a/dev/gcdb/display/include/display_resource.h
+++ b/dev/gcdb/display/include/display_resource.h
@@ -43,6 +43,13 @@
 #define LK_OVERRIDE_PANEL_LEN  2
 
 #define NO_PANEL_CONFIG "none"
+#define SIM_VIDEO_PANEL "sim_video_panel"
+#define SIM_DUALDSI_VIDEO_PANEL "sim_dualdsi_video_panel"
+
+#define SIM_DSI_ID "dsi:0:"
+#define SIM_VIDEO_PANEL_NODE "qcom,mdss_dsi_sim_video"
+#define SIM_DUALDSI_VIDEO_PANEL_NODE "qcom,mdss_dsi_sim_video_0"
+#define SIM_DUALDSI_VIDEO_SLAVE_PANEL_NODE "qcom,mdss_dsi_sim_video_1"
 
 /*---------------------------------------------------------------------------*/
 /* Structure definition                                                      */
diff --git a/dev/gcdb/display/include/panel_hx8379a_fwvga_video.h b/dev/gcdb/display/include/panel_hx8379a_fwvga_video.h
new file mode 100755
index 0000000..b11b9b4
--- /dev/null
+++ b/dev/gcdb/display/include/panel_hx8379a_fwvga_video.h
@@ -0,0 +1,237 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  * Neither the name of The Linux Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_HX8379A_FWVGA_VIDEO_H_
+#define _PANEL_HX8379A_FWVGA_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files                                                              */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration                                                       */
+/*---------------------------------------------------------------------------*/
+static struct panel_config hx8379a_fwvga_video_panel_data = {
+	"qcom,mdss_dsi_hx8379a_fwvga_video", "dsi:0:", "qcom,mdss-dsi-panel",
+	10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution                                                          */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution hx8379a_fwvga_video_panel_res = {
+	480, 854, 100, 94, 40, 0, 6, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information                                                   */
+/*---------------------------------------------------------------------------*/
+static struct color_info hx8379a_fwvga_video_color = {
+	24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information                                          */
+/*---------------------------------------------------------------------------*/
+static char hx8379a_fwvga_video_on_cmd0[] = {
+	0x04, 0x00, 0x39, 0xC0,
+	0xB9, 0xFF, 0x83, 0x79,
+};
+
+static char hx8379a_fwvga_video_on_cmd1[] = {
+	0x03, 0x00, 0x39, 0xC0,
+	0xBA, 0x51, 0x93, 0xFF,
+};
+
+static char hx8379a_fwvga_video_on_cmd2[] = {
+	0x14, 0x00, 0x39, 0xC0,
+	0xB1, 0x00, 0x50, 0x24,
+	0xEA, 0x51, 0x08, 0x11,
+	0x10, 0xF0, 0x27, 0x2F,
+	0x9A, 0x1A, 0x42, 0x0B,
+	0x7A, 0xF1, 0x00, 0xE6,
+};
+
+static char hx8379a_fwvga_video_on_cmd3[] = {
+	0x0E, 0x00, 0x39, 0xC0,
+	0xB2, 0x00, 0x00, 0xFE,
+	0x07, 0x03, 0x19, 0x44,
+	0x00, 0xFF, 0x07, 0x03,
+	0x19, 0x20, 0xFF, 0xFF,
+};
+
+static char hx8379a_fwvga_video_on_cmd4[] = {
+	0x20, 0x00, 0x39, 0xC0,
+	0xB4, 0x82, 0x08, 0x00,
+	0x32, 0x10, 0x03, 0x32,
+	0x13, 0x70, 0x32, 0x10,
+	0x08, 0x37, 0x01, 0x28,
+	0x07, 0x37, 0x08, 0x3C,
+	0x08, 0x3E, 0x3E, 0x08,
+	0x00, 0x40, 0x08, 0x28,
+	0x08, 0x30, 0x30, 0x04,
+};
+
+static char hx8379a_fwvga_video_on_cmd5[] = {
+	0xcc, 0x02, 0x23, 0x80
+};
+
+static char hx8379a_fwvga_video_on_cmd6[] = {
+	0x30, 0x00, 0x39, 0xC0,
+	0xD5, 0x00, 0x00, 0x0A,
+	0x00, 0x01, 0x05, 0x00,
+	0x03, 0x00, 0x88, 0x88,
+	0x88, 0x88, 0x23, 0x01,
+	0x67, 0x45, 0x02, 0x13,
+	0x88, 0x88, 0x88, 0x88,
+	0x88, 0x88, 0x88, 0x88,
+	0x88, 0x88, 0x54, 0x76,
+	0x10, 0x32, 0x31, 0x20,
+	0x88, 0x88, 0x88, 0x88,
+	0x88, 0x88, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00,
+};
+
+static char hx8379a_fwvga_video_on_cmd7[] = {
+	0x24, 0x00, 0x39, 0xC0,
+	0xE0, 0x79, 0x00, 0x0F,
+	0x14, 0x22, 0x22, 0x39,
+	0x2F, 0x43, 0x04, 0x0A,
+	0x12, 0x14, 0x17, 0x15,
+	0x16, 0x12, 0x16, 0x00,
+	0x0F, 0x14, 0x22, 0x22,
+	0x39, 0x2F, 0x43, 0x04,
+	0x0A, 0x12, 0x14, 0x17,
+	0x15, 0x16, 0x12, 0x16,
+};
+
+static char hx8379a_fwvga_video_on_cmd8[] = {
+	0x05, 0x00, 0x39, 0xC0,
+	0xB6, 0x00, 0x9C, 0x00,
+	0x9C, 0xFF, 0xFF, 0xFF,
+};
+
+static char hx8379a_fwvga_video_on_cmd9[] = {
+	0x11, 0x00, 0x05, 0x80
+};
+
+static char hx8379a_fwvga_video_on_cmd10[] = {
+	0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd hx8379a_fwvga_video_on_command[] = {
+	{0x8, hx8379a_fwvga_video_on_cmd0, 0x00},
+	{0x8, hx8379a_fwvga_video_on_cmd1, 0x00},
+	{0x18, hx8379a_fwvga_video_on_cmd2, 0x00},
+	{0x14, hx8379a_fwvga_video_on_cmd3, 0x00},
+	{0x24, hx8379a_fwvga_video_on_cmd4, 0x00},
+	{0x04, hx8379a_fwvga_video_on_cmd5, 0x00},
+	{0x34, hx8379a_fwvga_video_on_cmd6, 0x00},
+	{0x28, hx8379a_fwvga_video_on_cmd7, 0x00},
+	{0xc, hx8379a_fwvga_video_on_cmd8, 0x00},
+	{0x4, hx8379a_fwvga_video_on_cmd9, 0x96},
+	{0x4, hx8379a_fwvga_video_on_cmd10, 0x78}
+};
+
+#define HX8379A_FWVGA_VIDEO_ON_COMMAND 11
+
+
+static char hx8379a_fwvga_videooff_cmd0[] = {
+	0x28, 0x00, 0x05, 0x80
+};
+
+static char hx8379a_fwvga_videooff_cmd1[] = {
+	0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd hx8379a_fwvga_video_off_command[] = {
+	{0x4, hx8379a_fwvga_videooff_cmd0, 0x32},
+	{0x4, hx8379a_fwvga_videooff_cmd1, 0x78}
+};
+
+#define HX8379A_FWVGA_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state hx8379a_fwvga_video_state = {
+	0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information                                            */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info hx8379a_fwvga_video_command_panel = {
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information                                              */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info hx8379a_fwvga_video_video_panel = {
+	1, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration                                                        */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration hx8379a_fwvga_video_lane_config = {
+	2, 1, 1, 1, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing                                                              */
+/*---------------------------------------------------------------------------*/
+static const uint32_t hx8379a_fwvga_video_timings[] = {
+	0x8B, 0x1f, 0x14, 0x00, 0x45, 0x4A, 0x19, 0x23, 0x23, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing hx8379a_fwvga_video_timing_info = {
+	0, 4, 0x04, 0x1d
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence                                                      */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence hx8379a_fwvga_video_reset_seq = {
+	{1, 0, 1, }, {20, 2, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting                                                         */
+/*---------------------------------------------------------------------------*/
+static struct backlight hx8379a_fwvga_video_backlight = {
+	0, 1, 255, 0, 2, 0
+};
+
+#endif /*_PANEL_HX8379A_FWVGA_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_jdi_fhd_video.h b/dev/gcdb/display/include/panel_jdi_fhd_video.h
new file mode 100644
index 0000000..95522dd
--- /dev/null
+++ b/dev/gcdb/display/include/panel_jdi_fhd_video.h
@@ -0,0 +1,215 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  * Neither the name of The Linux Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_JDI_FHD_VIDEO_H_
+#define _PANEL_JDI_FHD_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files                                                              */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration                                                       */
+/*---------------------------------------------------------------------------*/
+static struct panel_config jdi_fhd_video_panel_data = {
+	"qcom,mdss_dsi_jdi_fhd_video", "dsi:0:", "qcom,mdss-dsi-panel",
+	10, 0, "DISPLAY_1", 0, 0, 56, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution                                                          */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution jdi_fhd_video_panel_res = {
+	1080, 1920, 12, 28, 4, 0, 18, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information                                                   */
+/*---------------------------------------------------------------------------*/
+static struct color_info jdi_fhd_video_color = {
+	24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information                                          */
+/*---------------------------------------------------------------------------*/
+static char jdi_fhd_video_on_cmd0[] = {
+	0xFF, 0xF0, 0x13, 0x80
+};
+
+static char jdi_fhd_video_on_cmd1[] = {
+	0xDD, 0x02, 0x13, 0x80
+};
+
+static char jdi_fhd_video_on_cmd2[] = {
+	0xE3, 0x00, 0x13, 0x80
+};
+
+static char jdi_fhd_video_on_cmd3[] = {
+	0xFB, 0x01, 0x13, 0x80
+};
+
+static char jdi_fhd_video_on_cmd4[] = {
+	0xFF, 0x00, 0x13, 0x80
+};
+
+static char jdi_fhd_video_on_cmd5[] = {
+	0x35, 0x00, 0x15, 0x80
+};
+
+static char jdi_fhd_video_on_cmd6[] = {
+	0x51, 0xFF, 0x15, 0x80
+};
+
+static char jdi_fhd_video_on_cmd7[] = {
+	0x53, 0x2C, 0x15, 0x80
+};
+
+static char jdi_fhd_video_on_cmd8[] = {
+	0xFF, 0x26, 0x13, 0x80
+};
+
+static char jdi_fhd_video_on_cmd9[] = {
+	0x02, 0xFF, 0x13, 0x80
+};
+
+static char jdi_fhd_video_on_cmd10[] = {
+	0xFF, 0x10, 0x13, 0x80
+};
+
+static char jdi_fhd_video_on_cmd11[] = {
+	0xBB, 0x13, 0x13, 0x80
+};
+
+static char jdi_fhd_video_on_cmd12[] = {
+	0xFF, 0x00, 0x13, 0x80
+};
+
+static char jdi_fhd_video_on_cmd13[] = {
+	0x11, 0xFF, 0x05, 0x80
+};
+
+static char jdi_fhd_video_on_cmd14[] = {
+	0x29, 0xFF, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd jdi_fhd_video_on_command[] = {
+	{0x4, jdi_fhd_video_on_cmd0, 0x0a},
+	{0x4, jdi_fhd_video_on_cmd1, 0x0a},
+	{0x4, jdi_fhd_video_on_cmd2, 0x0a},
+	{0x4, jdi_fhd_video_on_cmd3, 0x0a},
+	{0x4, jdi_fhd_video_on_cmd4, 0x0a},
+	{0x4, jdi_fhd_video_on_cmd5, 0x0a},
+	{0x4, jdi_fhd_video_on_cmd6, 0x0a},
+	{0x4, jdi_fhd_video_on_cmd7, 0x0a},
+	{0x4, jdi_fhd_video_on_cmd8, 0x0a},
+	{0x4, jdi_fhd_video_on_cmd9, 0x0a},
+	{0x4, jdi_fhd_video_on_cmd10, 0x0a},
+	{0x4, jdi_fhd_video_on_cmd11, 0x0a},
+	{0x4, jdi_fhd_video_on_cmd12, 0x0a},
+	{0x4, jdi_fhd_video_on_cmd13, 0xC8},
+	{0x4, jdi_fhd_video_on_cmd14, 0x28}
+};
+
+#define JDI_FHD_VIDEO_ON_COMMAND 15
+
+
+static char jdi_fhd_videooff_cmd0[] = {
+	0x28, 0x00, 0x05, 0x80
+};
+
+static char jdi_fhd_videooff_cmd1[] = {
+	0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd jdi_fhd_video_off_command[] = {
+	{0x4, jdi_fhd_videooff_cmd0, 0x32},
+	{0x4, jdi_fhd_videooff_cmd1, 0x78}
+};
+
+#define JDI_FHD_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state jdi_fhd_video_state = {
+	0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information                                            */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info jdi_fhd_video_command_panel = {
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information                                              */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info jdi_fhd_video_video_panel = {
+	0, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration                                                        */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration jdi_fhd_video_lane_config = {
+	4, 0, 1, 1, 1, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing                                                              */
+/*---------------------------------------------------------------------------*/
+static const uint32_t jdi_fhd_video_timings[] = {
+	0xce, 0x2e, 0x1e, 0x00, 0x5a, 0x5c, 0x24, 0x30, 0x24, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing jdi_fhd_video_timing_info = {
+	0x0, 0x04, 0x0a, 0x2c
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence                                                      */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence jdi_fhd_video_reset_seq = {
+	{1, 0, 1, }, {20, 200, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting                                                         */
+/*---------------------------------------------------------------------------*/
+static struct backlight jdi_fhd_video_backlight = {
+	1, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+#endif /*_PANEL_JDI_FHD_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_nt35590_720p_cmd.h b/dev/gcdb/display/include/panel_nt35590_720p_cmd.h
index 34cb79d..72f5a18 100755
--- a/dev/gcdb/display/include/panel_nt35590_720p_cmd.h
+++ b/dev/gcdb/display/include/panel_nt35590_720p_cmd.h
@@ -2390,470 +2390,470 @@
 
 
 static struct mipi_dsi_cmd nt35590_720p_cmd_on_command[] = {
-{ 0x8 , nt35590_720p_cmd_on_cmd0},
-{ 0x8 , nt35590_720p_cmd_on_cmd1},
-{ 0x8 , nt35590_720p_cmd_on_cmd2},
-{ 0x8 , nt35590_720p_cmd_on_cmd3},
-{ 0x8 , nt35590_720p_cmd_on_cmd4},
-{ 0x8 , nt35590_720p_cmd_on_cmd5},
-{ 0x8 , nt35590_720p_cmd_on_cmd6},
-{ 0x8 , nt35590_720p_cmd_on_cmd7},
-{ 0x8 , nt35590_720p_cmd_on_cmd8},
-{ 0x8 , nt35590_720p_cmd_on_cmd9},
-{ 0x8 , nt35590_720p_cmd_on_cmd10},
-{ 0x8 , nt35590_720p_cmd_on_cmd11},
-{ 0x8 , nt35590_720p_cmd_on_cmd12},
-{ 0x8 , nt35590_720p_cmd_on_cmd13},
-{ 0x8 , nt35590_720p_cmd_on_cmd14},
-{ 0x8 , nt35590_720p_cmd_on_cmd15},
-{ 0x8 , nt35590_720p_cmd_on_cmd16},
-{ 0x8 , nt35590_720p_cmd_on_cmd17},
-{ 0x8 , nt35590_720p_cmd_on_cmd18},
-{ 0x8 , nt35590_720p_cmd_on_cmd19},
-{ 0x8 , nt35590_720p_cmd_on_cmd20},
-{ 0x8 , nt35590_720p_cmd_on_cmd21},
-{ 0x8 , nt35590_720p_cmd_on_cmd22},
-{ 0x8 , nt35590_720p_cmd_on_cmd23},
-{ 0x8 , nt35590_720p_cmd_on_cmd24},
-{ 0x8 , nt35590_720p_cmd_on_cmd25},
-{ 0x8 , nt35590_720p_cmd_on_cmd26},
-{ 0x8 , nt35590_720p_cmd_on_cmd27},
-{ 0x8 , nt35590_720p_cmd_on_cmd28},
-{ 0x8 , nt35590_720p_cmd_on_cmd29},
-{ 0x8 , nt35590_720p_cmd_on_cmd30},
-{ 0x8 , nt35590_720p_cmd_on_cmd31},
-{ 0x8 , nt35590_720p_cmd_on_cmd32},
-{ 0x8 , nt35590_720p_cmd_on_cmd33},
-{ 0x8 , nt35590_720p_cmd_on_cmd34},
-{ 0x8 , nt35590_720p_cmd_on_cmd35},
-{ 0x8 , nt35590_720p_cmd_on_cmd36},
-{ 0x8 , nt35590_720p_cmd_on_cmd37},
-{ 0x8 , nt35590_720p_cmd_on_cmd38},
-{ 0x8 , nt35590_720p_cmd_on_cmd39},
-{ 0x8 , nt35590_720p_cmd_on_cmd40},
-{ 0x8 , nt35590_720p_cmd_on_cmd41},
-{ 0x8 , nt35590_720p_cmd_on_cmd42},
-{ 0x8 , nt35590_720p_cmd_on_cmd43},
-{ 0x8 , nt35590_720p_cmd_on_cmd44},
-{ 0x8 , nt35590_720p_cmd_on_cmd45},
-{ 0x8 , nt35590_720p_cmd_on_cmd46},
-{ 0x8 , nt35590_720p_cmd_on_cmd47},
-{ 0x8 , nt35590_720p_cmd_on_cmd48},
-{ 0x8 , nt35590_720p_cmd_on_cmd49},
-{ 0x8 , nt35590_720p_cmd_on_cmd50},
-{ 0x8 , nt35590_720p_cmd_on_cmd51},
-{ 0x8 , nt35590_720p_cmd_on_cmd52},
-{ 0x8 , nt35590_720p_cmd_on_cmd53},
-{ 0x8 , nt35590_720p_cmd_on_cmd54},
-{ 0x8 , nt35590_720p_cmd_on_cmd55},
-{ 0x8 , nt35590_720p_cmd_on_cmd56},
-{ 0x8 , nt35590_720p_cmd_on_cmd57},
-{ 0x8 , nt35590_720p_cmd_on_cmd58},
-{ 0x8 , nt35590_720p_cmd_on_cmd59},
-{ 0x8 , nt35590_720p_cmd_on_cmd60},
-{ 0x8 , nt35590_720p_cmd_on_cmd61},
-{ 0x8 , nt35590_720p_cmd_on_cmd62},
-{ 0x8 , nt35590_720p_cmd_on_cmd63},
-{ 0x8 , nt35590_720p_cmd_on_cmd64},
-{ 0x8 , nt35590_720p_cmd_on_cmd65},
-{ 0x8 , nt35590_720p_cmd_on_cmd66},
-{ 0x8 , nt35590_720p_cmd_on_cmd67},
-{ 0x8 , nt35590_720p_cmd_on_cmd68},
-{ 0x8 , nt35590_720p_cmd_on_cmd69},
-{ 0x8 , nt35590_720p_cmd_on_cmd70},
-{ 0x8 , nt35590_720p_cmd_on_cmd71},
-{ 0x8 , nt35590_720p_cmd_on_cmd72},
-{ 0x8 , nt35590_720p_cmd_on_cmd73},
-{ 0x8 , nt35590_720p_cmd_on_cmd74},
-{ 0x8 , nt35590_720p_cmd_on_cmd75},
-{ 0x8 , nt35590_720p_cmd_on_cmd76},
-{ 0x8 , nt35590_720p_cmd_on_cmd77},
-{ 0x8 , nt35590_720p_cmd_on_cmd78},
-{ 0x8 , nt35590_720p_cmd_on_cmd79},
-{ 0x8 , nt35590_720p_cmd_on_cmd80},
-{ 0x8 , nt35590_720p_cmd_on_cmd81},
-{ 0x8 , nt35590_720p_cmd_on_cmd82},
-{ 0x8 , nt35590_720p_cmd_on_cmd83},
-{ 0x8 , nt35590_720p_cmd_on_cmd84},
-{ 0x8 , nt35590_720p_cmd_on_cmd85},
-{ 0x8 , nt35590_720p_cmd_on_cmd86},
-{ 0x8 , nt35590_720p_cmd_on_cmd87},
-{ 0x8 , nt35590_720p_cmd_on_cmd88},
-{ 0x8 , nt35590_720p_cmd_on_cmd89},
-{ 0x8 , nt35590_720p_cmd_on_cmd90},
-{ 0x8 , nt35590_720p_cmd_on_cmd91},
-{ 0x8 , nt35590_720p_cmd_on_cmd92},
-{ 0x8 , nt35590_720p_cmd_on_cmd93},
-{ 0x8 , nt35590_720p_cmd_on_cmd94},
-{ 0x8 , nt35590_720p_cmd_on_cmd95},
-{ 0x8 , nt35590_720p_cmd_on_cmd96},
-{ 0x8 , nt35590_720p_cmd_on_cmd97},
-{ 0x8 , nt35590_720p_cmd_on_cmd98},
-{ 0x8 , nt35590_720p_cmd_on_cmd99},
-{ 0x8 , nt35590_720p_cmd_on_cmd100},
-{ 0x8 , nt35590_720p_cmd_on_cmd101},
-{ 0x8 , nt35590_720p_cmd_on_cmd102},
-{ 0x8 , nt35590_720p_cmd_on_cmd103},
-{ 0x8 , nt35590_720p_cmd_on_cmd104},
-{ 0x8 , nt35590_720p_cmd_on_cmd105},
-{ 0x8 , nt35590_720p_cmd_on_cmd106},
-{ 0x8 , nt35590_720p_cmd_on_cmd107},
-{ 0x8 , nt35590_720p_cmd_on_cmd108},
-{ 0x8 , nt35590_720p_cmd_on_cmd109},
-{ 0x8 , nt35590_720p_cmd_on_cmd110},
-{ 0x8 , nt35590_720p_cmd_on_cmd111},
-{ 0x8 , nt35590_720p_cmd_on_cmd112},
-{ 0x8 , nt35590_720p_cmd_on_cmd113},
-{ 0x8 , nt35590_720p_cmd_on_cmd114},
-{ 0x8 , nt35590_720p_cmd_on_cmd115},
-{ 0x8 , nt35590_720p_cmd_on_cmd116},
-{ 0x8 , nt35590_720p_cmd_on_cmd117},
-{ 0x8 , nt35590_720p_cmd_on_cmd118},
-{ 0x8 , nt35590_720p_cmd_on_cmd119},
-{ 0x8 , nt35590_720p_cmd_on_cmd120},
-{ 0x8 , nt35590_720p_cmd_on_cmd121},
-{ 0x8 , nt35590_720p_cmd_on_cmd122},
-{ 0x8 , nt35590_720p_cmd_on_cmd123},
-{ 0x8 , nt35590_720p_cmd_on_cmd124},
-{ 0x8 , nt35590_720p_cmd_on_cmd125},
-{ 0x8 , nt35590_720p_cmd_on_cmd126},
-{ 0x8 , nt35590_720p_cmd_on_cmd127},
-{ 0x8 , nt35590_720p_cmd_on_cmd128},
-{ 0x8 , nt35590_720p_cmd_on_cmd129},
-{ 0x8 , nt35590_720p_cmd_on_cmd130},
-{ 0x8 , nt35590_720p_cmd_on_cmd131},
-{ 0x8 , nt35590_720p_cmd_on_cmd132},
-{ 0x8 , nt35590_720p_cmd_on_cmd133},
-{ 0x8 , nt35590_720p_cmd_on_cmd134},
-{ 0x8 , nt35590_720p_cmd_on_cmd135},
-{ 0x8 , nt35590_720p_cmd_on_cmd136},
-{ 0x8 , nt35590_720p_cmd_on_cmd137},
-{ 0x8 , nt35590_720p_cmd_on_cmd138},
-{ 0x8 , nt35590_720p_cmd_on_cmd139},
-{ 0x8 , nt35590_720p_cmd_on_cmd140},
-{ 0x8 , nt35590_720p_cmd_on_cmd141},
-{ 0x8 , nt35590_720p_cmd_on_cmd142},
-{ 0x8 , nt35590_720p_cmd_on_cmd143},
-{ 0x8 , nt35590_720p_cmd_on_cmd144},
-{ 0x8 , nt35590_720p_cmd_on_cmd145},
-{ 0x8 , nt35590_720p_cmd_on_cmd146},
-{ 0x8 , nt35590_720p_cmd_on_cmd147},
-{ 0x8 , nt35590_720p_cmd_on_cmd148},
-{ 0x8 , nt35590_720p_cmd_on_cmd149},
-{ 0x8 , nt35590_720p_cmd_on_cmd150},
-{ 0x8 , nt35590_720p_cmd_on_cmd151},
-{ 0x8 , nt35590_720p_cmd_on_cmd152},
-{ 0x8 , nt35590_720p_cmd_on_cmd153},
-{ 0x8 , nt35590_720p_cmd_on_cmd154},
-{ 0x8 , nt35590_720p_cmd_on_cmd155},
-{ 0x8 , nt35590_720p_cmd_on_cmd156},
-{ 0x8 , nt35590_720p_cmd_on_cmd157},
-{ 0x8 , nt35590_720p_cmd_on_cmd158},
-{ 0x8 , nt35590_720p_cmd_on_cmd159},
-{ 0x8 , nt35590_720p_cmd_on_cmd160},
-{ 0x8 , nt35590_720p_cmd_on_cmd161},
-{ 0x8 , nt35590_720p_cmd_on_cmd162},
-{ 0x8 , nt35590_720p_cmd_on_cmd163},
-{ 0x8 , nt35590_720p_cmd_on_cmd164},
-{ 0x8 , nt35590_720p_cmd_on_cmd165},
-{ 0x8 , nt35590_720p_cmd_on_cmd166},
-{ 0x8 , nt35590_720p_cmd_on_cmd167},
-{ 0x8 , nt35590_720p_cmd_on_cmd168},
-{ 0x8 , nt35590_720p_cmd_on_cmd169},
-{ 0x8 , nt35590_720p_cmd_on_cmd170},
-{ 0x8 , nt35590_720p_cmd_on_cmd171},
-{ 0x8 , nt35590_720p_cmd_on_cmd172},
-{ 0x8 , nt35590_720p_cmd_on_cmd173},
-{ 0x8 , nt35590_720p_cmd_on_cmd174},
-{ 0x8 , nt35590_720p_cmd_on_cmd175},
-{ 0x8 , nt35590_720p_cmd_on_cmd176},
-{ 0x8 , nt35590_720p_cmd_on_cmd177},
-{ 0x8 , nt35590_720p_cmd_on_cmd178},
-{ 0x8 , nt35590_720p_cmd_on_cmd179},
-{ 0x8 , nt35590_720p_cmd_on_cmd180},
-{ 0x8 , nt35590_720p_cmd_on_cmd181},
-{ 0x8 , nt35590_720p_cmd_on_cmd182},
-{ 0x8 , nt35590_720p_cmd_on_cmd183},
-{ 0x8 , nt35590_720p_cmd_on_cmd184},
-{ 0x8 , nt35590_720p_cmd_on_cmd185},
-{ 0x8 , nt35590_720p_cmd_on_cmd186},
-{ 0x8 , nt35590_720p_cmd_on_cmd187},
-{ 0x8 , nt35590_720p_cmd_on_cmd188},
-{ 0x8 , nt35590_720p_cmd_on_cmd189},
-{ 0x8 , nt35590_720p_cmd_on_cmd190},
-{ 0x8 , nt35590_720p_cmd_on_cmd191},
-{ 0x8 , nt35590_720p_cmd_on_cmd192},
-{ 0x8 , nt35590_720p_cmd_on_cmd193},
-{ 0x8 , nt35590_720p_cmd_on_cmd194},
-{ 0x8 , nt35590_720p_cmd_on_cmd195},
-{ 0x8 , nt35590_720p_cmd_on_cmd196},
-{ 0x8 , nt35590_720p_cmd_on_cmd197},
-{ 0x8 , nt35590_720p_cmd_on_cmd198},
-{ 0x8 , nt35590_720p_cmd_on_cmd199},
-{ 0x8 , nt35590_720p_cmd_on_cmd200},
-{ 0x8 , nt35590_720p_cmd_on_cmd201},
-{ 0x8 , nt35590_720p_cmd_on_cmd202},
-{ 0x8 , nt35590_720p_cmd_on_cmd203},
-{ 0x8 , nt35590_720p_cmd_on_cmd204},
-{ 0x8 , nt35590_720p_cmd_on_cmd205},
-{ 0x8 , nt35590_720p_cmd_on_cmd206},
-{ 0x8 , nt35590_720p_cmd_on_cmd207},
-{ 0x8 , nt35590_720p_cmd_on_cmd208},
-{ 0x8 , nt35590_720p_cmd_on_cmd209},
-{ 0x8 , nt35590_720p_cmd_on_cmd210},
-{ 0x8 , nt35590_720p_cmd_on_cmd211},
-{ 0x8 , nt35590_720p_cmd_on_cmd212},
-{ 0x8 , nt35590_720p_cmd_on_cmd213},
-{ 0x8 , nt35590_720p_cmd_on_cmd214},
-{ 0x8 , nt35590_720p_cmd_on_cmd215},
-{ 0x8 , nt35590_720p_cmd_on_cmd216},
-{ 0x8 , nt35590_720p_cmd_on_cmd217},
-{ 0x8 , nt35590_720p_cmd_on_cmd218},
-{ 0x8 , nt35590_720p_cmd_on_cmd219},
-{ 0x8 , nt35590_720p_cmd_on_cmd220},
-{ 0x8 , nt35590_720p_cmd_on_cmd221},
-{ 0x8 , nt35590_720p_cmd_on_cmd222},
-{ 0x8 , nt35590_720p_cmd_on_cmd223},
-{ 0x8 , nt35590_720p_cmd_on_cmd224},
-{ 0x8 , nt35590_720p_cmd_on_cmd225},
-{ 0x8 , nt35590_720p_cmd_on_cmd226},
-{ 0x8 , nt35590_720p_cmd_on_cmd227},
-{ 0x8 , nt35590_720p_cmd_on_cmd228},
-{ 0x8 , nt35590_720p_cmd_on_cmd229},
-{ 0x8 , nt35590_720p_cmd_on_cmd230},
-{ 0x8 , nt35590_720p_cmd_on_cmd231},
-{ 0x8 , nt35590_720p_cmd_on_cmd232},
-{ 0x8 , nt35590_720p_cmd_on_cmd233},
-{ 0x8 , nt35590_720p_cmd_on_cmd234},
-{ 0x8 , nt35590_720p_cmd_on_cmd235},
-{ 0x8 , nt35590_720p_cmd_on_cmd236},
-{ 0x8 , nt35590_720p_cmd_on_cmd237},
-{ 0x8 , nt35590_720p_cmd_on_cmd238},
-{ 0x8 , nt35590_720p_cmd_on_cmd239},
-{ 0x8 , nt35590_720p_cmd_on_cmd240},
-{ 0x8 , nt35590_720p_cmd_on_cmd241},
-{ 0x8 , nt35590_720p_cmd_on_cmd242},
-{ 0x8 , nt35590_720p_cmd_on_cmd243},
-{ 0x8 , nt35590_720p_cmd_on_cmd244},
-{ 0x8 , nt35590_720p_cmd_on_cmd245},
-{ 0x8 , nt35590_720p_cmd_on_cmd246},
-{ 0x8 , nt35590_720p_cmd_on_cmd247},
-{ 0x8 , nt35590_720p_cmd_on_cmd248},
-{ 0x8 , nt35590_720p_cmd_on_cmd249},
-{ 0x8 , nt35590_720p_cmd_on_cmd250},
-{ 0x8 , nt35590_720p_cmd_on_cmd251},
-{ 0x8 , nt35590_720p_cmd_on_cmd252},
-{ 0x8 , nt35590_720p_cmd_on_cmd253},
-{ 0x8 , nt35590_720p_cmd_on_cmd254},
-{ 0x8 , nt35590_720p_cmd_on_cmd255},
-{ 0x8 , nt35590_720p_cmd_on_cmd256},
-{ 0x8 , nt35590_720p_cmd_on_cmd257},
-{ 0x8 , nt35590_720p_cmd_on_cmd258},
-{ 0x8 , nt35590_720p_cmd_on_cmd259},
-{ 0x8 , nt35590_720p_cmd_on_cmd260},
-{ 0x8 , nt35590_720p_cmd_on_cmd261},
-{ 0x8 , nt35590_720p_cmd_on_cmd262},
-{ 0x8 , nt35590_720p_cmd_on_cmd263},
-{ 0x8 , nt35590_720p_cmd_on_cmd264},
-{ 0x8 , nt35590_720p_cmd_on_cmd265},
-{ 0x8 , nt35590_720p_cmd_on_cmd266},
-{ 0x8 , nt35590_720p_cmd_on_cmd267},
-{ 0x8 , nt35590_720p_cmd_on_cmd268},
-{ 0x8 , nt35590_720p_cmd_on_cmd269},
-{ 0x8 , nt35590_720p_cmd_on_cmd270},
-{ 0x8 , nt35590_720p_cmd_on_cmd271},
-{ 0x8 , nt35590_720p_cmd_on_cmd272},
-{ 0x8 , nt35590_720p_cmd_on_cmd273},
-{ 0x8 , nt35590_720p_cmd_on_cmd274},
-{ 0x8 , nt35590_720p_cmd_on_cmd275},
-{ 0x8 , nt35590_720p_cmd_on_cmd276},
-{ 0x8 , nt35590_720p_cmd_on_cmd277},
-{ 0x8 , nt35590_720p_cmd_on_cmd278},
-{ 0x8 , nt35590_720p_cmd_on_cmd279},
-{ 0x8 , nt35590_720p_cmd_on_cmd280},
-{ 0x8 , nt35590_720p_cmd_on_cmd281},
-{ 0x8 , nt35590_720p_cmd_on_cmd282},
-{ 0x8 , nt35590_720p_cmd_on_cmd283},
-{ 0x8 , nt35590_720p_cmd_on_cmd284},
-{ 0x8 , nt35590_720p_cmd_on_cmd285},
-{ 0x8 , nt35590_720p_cmd_on_cmd286},
-{ 0x8 , nt35590_720p_cmd_on_cmd287},
-{ 0x8 , nt35590_720p_cmd_on_cmd288},
-{ 0x8 , nt35590_720p_cmd_on_cmd289},
-{ 0x8 , nt35590_720p_cmd_on_cmd290},
-{ 0x8 , nt35590_720p_cmd_on_cmd291},
-{ 0x8 , nt35590_720p_cmd_on_cmd292},
-{ 0x8 , nt35590_720p_cmd_on_cmd293},
-{ 0x8 , nt35590_720p_cmd_on_cmd294},
-{ 0x8 , nt35590_720p_cmd_on_cmd295},
-{ 0x8 , nt35590_720p_cmd_on_cmd296},
-{ 0x8 , nt35590_720p_cmd_on_cmd297},
-{ 0x8 , nt35590_720p_cmd_on_cmd298},
-{ 0x8 , nt35590_720p_cmd_on_cmd299},
-{ 0x8 , nt35590_720p_cmd_on_cmd300},
-{ 0x8 , nt35590_720p_cmd_on_cmd301},
-{ 0x8 , nt35590_720p_cmd_on_cmd302},
-{ 0x8 , nt35590_720p_cmd_on_cmd303},
-{ 0x8 , nt35590_720p_cmd_on_cmd304},
-{ 0x8 , nt35590_720p_cmd_on_cmd305},
-{ 0x8 , nt35590_720p_cmd_on_cmd306},
-{ 0x8 , nt35590_720p_cmd_on_cmd307},
-{ 0x8 , nt35590_720p_cmd_on_cmd308},
-{ 0x8 , nt35590_720p_cmd_on_cmd309},
-{ 0x8 , nt35590_720p_cmd_on_cmd310},
-{ 0x8 , nt35590_720p_cmd_on_cmd311},
-{ 0x8 , nt35590_720p_cmd_on_cmd312},
-{ 0x8 , nt35590_720p_cmd_on_cmd313},
-{ 0x8 , nt35590_720p_cmd_on_cmd314},
-{ 0x8 , nt35590_720p_cmd_on_cmd315},
-{ 0x8 , nt35590_720p_cmd_on_cmd316},
-{ 0x8 , nt35590_720p_cmd_on_cmd317},
-{ 0x8 , nt35590_720p_cmd_on_cmd318},
-{ 0x8 , nt35590_720p_cmd_on_cmd319},
-{ 0x8 , nt35590_720p_cmd_on_cmd320},
-{ 0x8 , nt35590_720p_cmd_on_cmd321},
-{ 0x8 , nt35590_720p_cmd_on_cmd322},
-{ 0x8 , nt35590_720p_cmd_on_cmd323},
-{ 0x8 , nt35590_720p_cmd_on_cmd324},
-{ 0x8 , nt35590_720p_cmd_on_cmd325},
-{ 0x8 , nt35590_720p_cmd_on_cmd326},
-{ 0x8 , nt35590_720p_cmd_on_cmd327},
-{ 0x8 , nt35590_720p_cmd_on_cmd328},
-{ 0x8 , nt35590_720p_cmd_on_cmd329},
-{ 0x8 , nt35590_720p_cmd_on_cmd330},
-{ 0x8 , nt35590_720p_cmd_on_cmd331},
-{ 0x8 , nt35590_720p_cmd_on_cmd332},
-{ 0x8 , nt35590_720p_cmd_on_cmd333},
-{ 0x8 , nt35590_720p_cmd_on_cmd334},
-{ 0x8 , nt35590_720p_cmd_on_cmd335},
-{ 0x8 , nt35590_720p_cmd_on_cmd336},
-{ 0x8 , nt35590_720p_cmd_on_cmd337},
-{ 0x8 , nt35590_720p_cmd_on_cmd338},
-{ 0x8 , nt35590_720p_cmd_on_cmd339},
-{ 0x8 , nt35590_720p_cmd_on_cmd340},
-{ 0x8 , nt35590_720p_cmd_on_cmd341},
-{ 0x8 , nt35590_720p_cmd_on_cmd342},
-{ 0x8 , nt35590_720p_cmd_on_cmd343},
-{ 0x8 , nt35590_720p_cmd_on_cmd344},
-{ 0x8 , nt35590_720p_cmd_on_cmd345},
-{ 0x8 , nt35590_720p_cmd_on_cmd346},
-{ 0x8 , nt35590_720p_cmd_on_cmd347},
-{ 0x8 , nt35590_720p_cmd_on_cmd348},
-{ 0x8 , nt35590_720p_cmd_on_cmd349},
-{ 0x8 , nt35590_720p_cmd_on_cmd350},
-{ 0x8 , nt35590_720p_cmd_on_cmd351},
-{ 0x8 , nt35590_720p_cmd_on_cmd352},
-{ 0x8 , nt35590_720p_cmd_on_cmd353},
-{ 0x8 , nt35590_720p_cmd_on_cmd354},
-{ 0x8 , nt35590_720p_cmd_on_cmd355},
-{ 0x8 , nt35590_720p_cmd_on_cmd356},
-{ 0x8 , nt35590_720p_cmd_on_cmd357},
-{ 0x8 , nt35590_720p_cmd_on_cmd358},
-{ 0x8 , nt35590_720p_cmd_on_cmd359},
-{ 0x8 , nt35590_720p_cmd_on_cmd360},
-{ 0x8 , nt35590_720p_cmd_on_cmd361},
-{ 0x8 , nt35590_720p_cmd_on_cmd362},
-{ 0x8 , nt35590_720p_cmd_on_cmd363},
-{ 0x8 , nt35590_720p_cmd_on_cmd364},
-{ 0x8 , nt35590_720p_cmd_on_cmd365},
-{ 0x8 , nt35590_720p_cmd_on_cmd366},
-{ 0x8 , nt35590_720p_cmd_on_cmd367},
-{ 0x8 , nt35590_720p_cmd_on_cmd368},
-{ 0x8 , nt35590_720p_cmd_on_cmd369},
-{ 0x8 , nt35590_720p_cmd_on_cmd370},
-{ 0x8 , nt35590_720p_cmd_on_cmd371},
-{ 0x8 , nt35590_720p_cmd_on_cmd372},
-{ 0x8 , nt35590_720p_cmd_on_cmd373},
-{ 0x8 , nt35590_720p_cmd_on_cmd374},
-{ 0x8 , nt35590_720p_cmd_on_cmd375},
-{ 0x8 , nt35590_720p_cmd_on_cmd376},
-{ 0x8 , nt35590_720p_cmd_on_cmd377},
-{ 0x8 , nt35590_720p_cmd_on_cmd378},
-{ 0x8 , nt35590_720p_cmd_on_cmd379},
-{ 0x8 , nt35590_720p_cmd_on_cmd380},
-{ 0x8 , nt35590_720p_cmd_on_cmd381},
-{ 0x8 , nt35590_720p_cmd_on_cmd382},
-{ 0x8 , nt35590_720p_cmd_on_cmd383},
-{ 0x8 , nt35590_720p_cmd_on_cmd384},
-{ 0x8 , nt35590_720p_cmd_on_cmd385},
-{ 0x8 , nt35590_720p_cmd_on_cmd386},
-{ 0x8 , nt35590_720p_cmd_on_cmd387},
-{ 0x8 , nt35590_720p_cmd_on_cmd388},
-{ 0x8 , nt35590_720p_cmd_on_cmd389},
-{ 0x8 , nt35590_720p_cmd_on_cmd390},
-{ 0x8 , nt35590_720p_cmd_on_cmd391},
-{ 0x8 , nt35590_720p_cmd_on_cmd392},
-{ 0x8 , nt35590_720p_cmd_on_cmd393},
-{ 0x8 , nt35590_720p_cmd_on_cmd394},
-{ 0x8 , nt35590_720p_cmd_on_cmd395},
-{ 0x8 , nt35590_720p_cmd_on_cmd396},
-{ 0x8 , nt35590_720p_cmd_on_cmd397},
-{ 0x8 , nt35590_720p_cmd_on_cmd398},
-{ 0x8 , nt35590_720p_cmd_on_cmd399},
-{ 0x8 , nt35590_720p_cmd_on_cmd400},
-{ 0x8 , nt35590_720p_cmd_on_cmd401},
-{ 0x8 , nt35590_720p_cmd_on_cmd402},
-{ 0x8 , nt35590_720p_cmd_on_cmd403},
-{ 0x8 , nt35590_720p_cmd_on_cmd404},
-{ 0x8 , nt35590_720p_cmd_on_cmd405},
-{ 0x8 , nt35590_720p_cmd_on_cmd406},
-{ 0x8 , nt35590_720p_cmd_on_cmd407},
-{ 0x8 , nt35590_720p_cmd_on_cmd408},
-{ 0x8 , nt35590_720p_cmd_on_cmd409},
-{ 0x8 , nt35590_720p_cmd_on_cmd410},
-{ 0x8 , nt35590_720p_cmd_on_cmd411},
-{ 0x8 , nt35590_720p_cmd_on_cmd412},
-{ 0x8 , nt35590_720p_cmd_on_cmd413},
-{ 0x8 , nt35590_720p_cmd_on_cmd414},
-{ 0x8 , nt35590_720p_cmd_on_cmd415},
-{ 0x8 , nt35590_720p_cmd_on_cmd416},
-{ 0x8 , nt35590_720p_cmd_on_cmd417},
-{ 0x8 , nt35590_720p_cmd_on_cmd418},
-{ 0x8 , nt35590_720p_cmd_on_cmd419},
-{ 0x8 , nt35590_720p_cmd_on_cmd420},
-{ 0x8 , nt35590_720p_cmd_on_cmd421},
-{ 0x8 , nt35590_720p_cmd_on_cmd422},
-{ 0x8 , nt35590_720p_cmd_on_cmd423},
-{ 0x8 , nt35590_720p_cmd_on_cmd424},
-{ 0x8 , nt35590_720p_cmd_on_cmd425},
-{ 0x8 , nt35590_720p_cmd_on_cmd426},
-{ 0x8 , nt35590_720p_cmd_on_cmd427},
-{ 0x8 , nt35590_720p_cmd_on_cmd428},
-{ 0x8 , nt35590_720p_cmd_on_cmd429},
-{ 0x8 , nt35590_720p_cmd_on_cmd430},
-{ 0x8 , nt35590_720p_cmd_on_cmd431},
-{ 0x8 , nt35590_720p_cmd_on_cmd432},
-{ 0x8 , nt35590_720p_cmd_on_cmd433},
-{ 0x8 , nt35590_720p_cmd_on_cmd434},
-{ 0x8 , nt35590_720p_cmd_on_cmd435},
-{ 0x8 , nt35590_720p_cmd_on_cmd436},
-{ 0x8 , nt35590_720p_cmd_on_cmd437},
-{ 0x8 , nt35590_720p_cmd_on_cmd438},
-{ 0x8 , nt35590_720p_cmd_on_cmd439},
-{ 0x8 , nt35590_720p_cmd_on_cmd440},
-{ 0x8 , nt35590_720p_cmd_on_cmd441},
-{ 0x8 , nt35590_720p_cmd_on_cmd442},
-{ 0x8 , nt35590_720p_cmd_on_cmd443},
-{ 0x8 , nt35590_720p_cmd_on_cmd444},
-{ 0x8 , nt35590_720p_cmd_on_cmd445},
-{ 0x8 , nt35590_720p_cmd_on_cmd446},
-{ 0x8 , nt35590_720p_cmd_on_cmd447},
-{ 0x8 , nt35590_720p_cmd_on_cmd448},
-{ 0x8 , nt35590_720p_cmd_on_cmd449},
-{ 0x8 , nt35590_720p_cmd_on_cmd450},
-{ 0x8 , nt35590_720p_cmd_on_cmd451},
-{ 0x8 , nt35590_720p_cmd_on_cmd452},
-{ 0x8 , nt35590_720p_cmd_on_cmd453},
-{ 0x8 , nt35590_720p_cmd_on_cmd454},
-{ 0x8 , nt35590_720p_cmd_on_cmd455},
-{ 0x8 , nt35590_720p_cmd_on_cmd456},
-{ 0x8 , nt35590_720p_cmd_on_cmd457},
-{ 0x8 , nt35590_720p_cmd_on_cmd458},
-{ 0x8 , nt35590_720p_cmd_on_cmd459},
-{ 0x8 , nt35590_720p_cmd_on_cmd460},
-{ 0x8 , nt35590_720p_cmd_on_cmd461},
-{ 0x8 , nt35590_720p_cmd_on_cmd462},
-{ 0x8 , nt35590_720p_cmd_on_cmd463}
+{ 0x8 , nt35590_720p_cmd_on_cmd0, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd1, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd2, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd3, 0x10},
+{ 0x8 , nt35590_720p_cmd_on_cmd4, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd5, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd6, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd7, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd8, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd9, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd10, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd11, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd12, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd13, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd14, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd15, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd16, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd17, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd18, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd19, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd20, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd21, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd22, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd23, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd24, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd25, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd26, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd27, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd28, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd29, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd30, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd31, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd32, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd33, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd34, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd35, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd36, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd37, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd38, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd39, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd40, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd41, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd42, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd43, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd44, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd45, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd46, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd47, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd48, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd49, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd50, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd51, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd52, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd53, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd54, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd55, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd56, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd57, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd58, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd59, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd60, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd61, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd62, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd63, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd64, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd65, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd66, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd67, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd68, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd69, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd70, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd71, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd72, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd73, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd74, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd75, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd76, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd77, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd78, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd79, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd80, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd81, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd82, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd83, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd84, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd85, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd86, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd87, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd88, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd89, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd90, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd91, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd92, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd93, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd94, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd95, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd96, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd97, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd98, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd99, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd100, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd101, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd102, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd103, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd104, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd105, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd106, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd107, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd108, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd109, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd110, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd111, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd112, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd113, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd114, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd115, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd116, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd117, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd118, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd119, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd120, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd121, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd122, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd123, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd124, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd125, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd126, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd127, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd128, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd129, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd130, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd131, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd132, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd133, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd134, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd135, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd136, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd137, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd138, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd139, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd140, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd141, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd142, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd143, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd144, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd145, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd146, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd147, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd148, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd149, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd150, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd151, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd152, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd153, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd154, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd155, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd156, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd157, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd158, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd159, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd160, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd161, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd162, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd163, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd164, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd165, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd166, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd167, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd168, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd169, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd170, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd171, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd172, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd173, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd174, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd175, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd176, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd177, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd178, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd179, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd180, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd181, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd182, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd183, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd184, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd185, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd186, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd187, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd188, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd189, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd190, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd191, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd192, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd193, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd194, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd195, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd196, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd197, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd198, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd199, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd200, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd201, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd202, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd203, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd204, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd205, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd206, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd207, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd208, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd209, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd210, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd211, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd212, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd213, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd214, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd215, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd216, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd217, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd218, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd219, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd220, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd221, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd222, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd223, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd224, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd225, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd226, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd227, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd228, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd229, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd230, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd231, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd232, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd233, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd234, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd235, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd236, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd237, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd238, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd239, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd240, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd241, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd242, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd243, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd244, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd245, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd246, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd247, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd248, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd249, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd250, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd251, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd252, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd253, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd254, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd255, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd256, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd257, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd258, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd259, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd260, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd261, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd262, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd263, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd264, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd265, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd266, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd267, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd268, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd269, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd270, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd271, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd272, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd273, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd274, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd275, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd276, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd277, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd278, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd279, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd280, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd281, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd282, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd283, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd284, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd285, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd286, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd287, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd288, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd289, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd290, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd291, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd292, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd293, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd294, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd295, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd296, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd297, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd298, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd299, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd300, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd301, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd302, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd303, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd304, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd305, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd306, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd307, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd308, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd309, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd310, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd311, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd312, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd313, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd314, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd315, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd316, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd317, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd318, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd319, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd320, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd321, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd322, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd323, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd324, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd325, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd326, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd327, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd328, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd329, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd330, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd331, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd332, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd333, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd334, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd335, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd336, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd337, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd338, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd339, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd340, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd341, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd342, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd343, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd344, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd345, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd346, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd347, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd348, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd349, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd350, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd351, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd352, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd353, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd354, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd355, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd356, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd357, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd358, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd359, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd360, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd361, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd362, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd363, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd364, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd365, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd366, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd367, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd368, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd369, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd370, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd371, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd372, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd373, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd374, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd375, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd376, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd377, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd378, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd379, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd380, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd381, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd382, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd383, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd384, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd385, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd386, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd387, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd388, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd389, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd390, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd391, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd392, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd393, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd394, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd395, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd396, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd397, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd398, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd399, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd400, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd401, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd402, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd403, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd404, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd405, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd406, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd407, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd408, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd409, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd410, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd411, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd412, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd413, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd414, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd415, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd416, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd417, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd418, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd419, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd420, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd421, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd422, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd423, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd424, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd425, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd426, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd427, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd428, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd429, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd430, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd431, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd432, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd433, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd434, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd435, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd436, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd437, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd438, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd439, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd440, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd441, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd442, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd443, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd444, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd445, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd446, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd447, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd448, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd449, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd450, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd451, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd452, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd453, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd454, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd455, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd456, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd457, 0x64},
+{ 0x8 , nt35590_720p_cmd_on_cmd458, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd459, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd460, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd461, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd462, 0x00},
+{ 0x8 , nt35590_720p_cmd_on_cmd463, 0x78}
 };
 #define NT35590_720P_CMD_ON_COMMAND 464
 
diff --git a/dev/gcdb/display/include/panel_nt35596_1080p_skuk_video.h b/dev/gcdb/display/include/panel_nt35596_1080p_skuk_video.h
index a25afd8..2cd3d07 100644
--- a/dev/gcdb/display/include/panel_nt35596_1080p_skuk_video.h
+++ b/dev/gcdb/display/include/panel_nt35596_1080p_skuk_video.h
@@ -541,22 +541,22 @@
 
 static char nt35596_1080p_skuk_video_on_cmd95[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x0E, 0xBF, 0xFF, 0xFF,
+	0x0E, 0xB5, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd96[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x0F, 0xC2, 0xFF, 0xFF,
+	0x0F, 0xB8, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd97[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x0B, 0xB3, 0xFF, 0xFF,
+	0x0B, 0x55, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd98[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x0C, 0xB3, 0xFF, 0xFF,
+	0x0C, 0x55, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd99[] = {
@@ -586,1877 +586,1882 @@
 
 static char nt35596_1080p_skuk_video_on_cmd104[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x75, 0x00, 0xFF, 0xFF,
+	0xFF, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd105[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x76, 0x00, 0xFF, 0xFF,
+	0xFB, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd106[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x77, 0x00, 0xFF, 0xFF,
+	0x75, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd107[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x78, 0x09, 0xFF, 0xFF,
+	0x76, 0x10, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd108[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x79, 0x00, 0xFF, 0xFF,
+	0x77, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd109[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x7A, 0x1D, 0xFF, 0xFF,
+	0x78, 0x1D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd110[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x7B, 0x00, 0xFF, 0xFF,
+	0x79, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd111[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x7C, 0x2E, 0xFF, 0xFF,
+	0x7A, 0x32, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd112[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x7D, 0x00, 0xFF, 0xFF,
+	0x7B, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd113[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x7E, 0x3D, 0xFF, 0xFF,
+	0x7C, 0x44, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd114[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x7F, 0x00, 0xFF, 0xFF,
+	0x7D, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd115[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x80, 0x4C, 0xFF, 0xFF,
+	0x7E, 0x54, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd116[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x81, 0x00, 0xFF, 0xFF,
+	0x7F, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd117[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x82, 0x59, 0xFF, 0xFF,
+	0x80, 0x63, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd118[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x83, 0x00, 0xFF, 0xFF,
+	0x81, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd119[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x84, 0x66, 0xFF, 0xFF,
+	0x82, 0x71, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd120[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x85, 0x00, 0xFF, 0xFF,
+	0x83, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd121[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x86, 0x73, 0xFF, 0xFF,
+	0x84, 0x7D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd122[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x87, 0x00, 0xFF, 0xFF,
+	0x85, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd123[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x88, 0xA0, 0xFF, 0xFF,
+	0x86, 0x89, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd124[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x89, 0x00, 0xFF, 0xFF,
+	0x87, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd125[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x8A, 0xC7, 0xFF, 0xFF,
+	0x88, 0xB2, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd126[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x8B, 0x01, 0xFF, 0xFF,
+	0x89, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd127[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x8C, 0x0C, 0xFF, 0xFF,
+	0x8A, 0xD5, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd128[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x8D, 0x01, 0xFF, 0xFF,
+	0x8B, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd129[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x8E, 0x46, 0xFF, 0xFF,
+	0x8C, 0x0D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd130[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x8F, 0x01, 0xFF, 0xFF,
+	0x8D, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd131[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x90, 0xA4, 0xFF, 0xFF,
+	0x8E, 0x3B, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd132[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x91, 0x01, 0xFF, 0xFF,
+	0x8F, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd133[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x92, 0xF1, 0xFF, 0xFF,
+	0x90, 0x87, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd134[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x93, 0x01, 0xFF, 0xFF,
+	0x91, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd135[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x94, 0xF3, 0xFF, 0xFF,
+	0x92, 0xC6, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd136[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x95, 0x02, 0xFF, 0xFF,
+	0x93, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd137[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x96, 0x36, 0xFF, 0xFF,
+	0x94, 0xC8, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd138[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x97, 0x02, 0xFF, 0xFF,
+	0x95, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd139[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x98, 0x7B, 0xFF, 0xFF,
+	0x96, 0x04, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd140[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x99, 0x02, 0xFF, 0xFF,
+	0x97, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd141[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x9A, 0xA3, 0xFF, 0xFF,
+	0x98, 0x47, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd142[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x9B, 0x02, 0xFF, 0xFF,
+	0x99, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd143[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x9C, 0xD6, 0xFF, 0xFF,
+	0x9A, 0x72, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd144[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x9D, 0x02, 0xFF, 0xFF,
+	0x9B, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd145[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x9E, 0xF9, 0xFF, 0xFF,
+	0x9C, 0xAC, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd146[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x9F, 0x03, 0xFF, 0xFF,
+	0x9D, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd147[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xA0, 0x26, 0xFF, 0xFF,
+	0x9E, 0xD3, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd148[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xA2, 0x03, 0xFF, 0xFF,
+	0x9F, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd149[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xA3, 0x34, 0xFF, 0xFF,
+	0xA0, 0x07, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd150[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xA4, 0x03, 0xFF, 0xFF,
+	0xA2, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd151[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xA5, 0x43, 0xFF, 0xFF,
+	0xA3, 0x17, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd152[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xA6, 0x03, 0xFF, 0xFF,
+	0xA4, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd153[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xA7, 0x55, 0xFF, 0xFF,
+	0xA5, 0x29, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd154[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xA9, 0x03, 0xFF, 0xFF,
+	0xA6, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd155[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xAA, 0x6A, 0xFF, 0xFF,
+	0xA7, 0x3D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd156[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xAB, 0x03, 0xFF, 0xFF,
+	0xA9, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd157[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xAC, 0x81, 0xFF, 0xFF,
+	0xAA, 0x52, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd158[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xAD, 0x03, 0xFF, 0xFF,
+	0xAB, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd159[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xAE, 0x9F, 0xFF, 0xFF,
+	0xAC, 0x6E, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd160[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xAF, 0x03, 0xFF, 0xFF,
+	0xAD, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd161[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xB0, 0xD1, 0xFF, 0xFF,
+	0xAE, 0x8D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd162[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xB1, 0x03, 0xFF, 0xFF,
+	0xAF, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd163[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xB2, 0xFF, 0xFF, 0xFF,
+	0xB0, 0xB0, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd164[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xB3, 0x00, 0xFF, 0xFF,
+	0xB1, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd165[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xB4, 0x00, 0xFF, 0xFF,
+	0xB2, 0xBF, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd166[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xB5, 0x00, 0xFF, 0xFF,
+	0xB3, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd167[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xB6, 0x09, 0xFF, 0xFF,
+	0xB4, 0x10, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd168[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xB7, 0x00, 0xFF, 0xFF,
+	0xB5, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd169[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xB8, 0x1D, 0xFF, 0xFF,
+	0xB6, 0x1D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd170[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xB9, 0x00, 0xFF, 0xFF,
+	0xB7, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd171[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xBA, 0x2E, 0xFF, 0xFF,
+	0xB8, 0x32, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd172[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xBB, 0x00, 0xFF, 0xFF,
+	0xB9, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd173[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xBC, 0x3D, 0xFF, 0xFF,
+	0xBA, 0x44, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd174[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xBD, 0x00, 0xFF, 0xFF,
+	0xBB, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd175[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xBE, 0x4C, 0xFF, 0xFF,
+	0xBC, 0x54, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd176[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xBF, 0x00, 0xFF, 0xFF,
+	0xBD, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd177[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xC0, 0x59, 0xFF, 0xFF,
+	0xBE, 0x63, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd178[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xC1, 0x00, 0xFF, 0xFF,
+	0xBF, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd179[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xC2, 0x66, 0xFF, 0xFF,
+	0xC0, 0x71, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd180[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xC3, 0x00, 0xFF, 0xFF,
+	0xC1, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd181[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xC4, 0x73, 0xFF, 0xFF,
+	0xC2, 0x7D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd182[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xC5, 0x00, 0xFF, 0xFF,
+	0xC3, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd183[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xC6, 0xA0, 0xFF, 0xFF,
+	0xC4, 0x89, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd184[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xC7, 0x00, 0xFF, 0xFF,
+	0xC5, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd185[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xC8, 0xC7, 0xFF, 0xFF,
+	0xC6, 0xB2, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd186[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xC9, 0x01, 0xFF, 0xFF,
+	0xC7, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd187[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xCA, 0x0C, 0xFF, 0xFF,
+	0xC8, 0xD5, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd188[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xCB, 0x01, 0xFF, 0xFF,
+	0xC9, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd189[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xCC, 0x46, 0xFF, 0xFF,
+	0xCA, 0x0D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd190[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xCD, 0x01, 0xFF, 0xFF,
+	0xCB, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd191[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xCE, 0xA4, 0xFF, 0xFF,
+	0xCC, 0x3B, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd192[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xCF, 0x01, 0xFF, 0xFF,
+	0xCD, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd193[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xD0, 0xF1, 0xFF, 0xFF,
+	0xCE, 0x87, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd194[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xD1, 0x01, 0xFF, 0xFF,
+	0xCF, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd195[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xD2, 0xF3, 0xFF, 0xFF,
+	0xD0, 0xC6, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd196[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xD3, 0x02, 0xFF, 0xFF,
+	0xD1, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd197[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xD4, 0x36, 0xFF, 0xFF,
+	0xD2, 0xC8, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd198[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xD5, 0x02, 0xFF, 0xFF,
+	0xD3, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd199[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xD6, 0x7B, 0xFF, 0xFF,
+	0xD4, 0x04, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd200[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xD7, 0x02, 0xFF, 0xFF,
+	0xD5, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd201[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xD8, 0xA3, 0xFF, 0xFF,
+	0xD6, 0x47, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd202[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xD9, 0x02, 0xFF, 0xFF,
+	0xD7, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd203[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xDA, 0xD6, 0xFF, 0xFF,
+	0xD8, 0x72, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd204[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xDB, 0x02, 0xFF, 0xFF,
+	0xD9, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd205[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xDC, 0xF9, 0xFF, 0xFF,
+	0xDA, 0xAC, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd206[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xDD, 0x03, 0xFF, 0xFF,
+	0xDB, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd207[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xDE, 0x26, 0xFF, 0xFF,
+	0xDC, 0xD3, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd208[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xDF, 0x03, 0xFF, 0xFF,
+	0xDD, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd209[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xE0, 0x34, 0xFF, 0xFF,
+	0xDE, 0x07, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd210[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xE1, 0x03, 0xFF, 0xFF,
+	0xDF, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd211[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xE2, 0x43, 0xFF, 0xFF,
+	0xE0, 0x17, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd212[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xE3, 0x03, 0xFF, 0xFF,
+	0xE1, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd213[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xE4, 0x55, 0xFF, 0xFF,
+	0xE2, 0x29, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd214[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xE5, 0x03, 0xFF, 0xFF,
+	0xE3, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd215[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xE6, 0x6A, 0xFF, 0xFF,
+	0xE4, 0x3D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd216[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xE7, 0x03, 0xFF, 0xFF,
+	0xE5, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd217[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xE8, 0x81, 0xFF, 0xFF,
+	0xE6, 0x52, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd218[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xE9, 0x03, 0xFF, 0xFF,
+	0xE7, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd219[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xEA, 0x9F, 0xFF, 0xFF,
+	0xE8, 0x6E, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd220[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xEB, 0x03, 0xFF, 0xFF,
+	0xE9, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd221[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xEC, 0xD1, 0xFF, 0xFF,
+	0xEA, 0x8D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd222[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xED, 0x03, 0xFF, 0xFF,
+	0xEB, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd223[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xEE, 0xFF, 0xFF, 0xFF,
+	0xEC, 0xB0, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd224[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xEF, 0x00, 0xFF, 0xFF,
+	0xED, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd225[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xF0, 0x00, 0xFF, 0xFF,
+	0xEE, 0xBF, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd226[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xF1, 0x00, 0xFF, 0xFF,
+	0xEF, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd227[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xF2, 0x09, 0xFF, 0xFF,
+	0xF0, 0x10, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd228[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xF3, 0x00, 0xFF, 0xFF,
+	0xF1, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd229[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xF4, 0x1D, 0xFF, 0xFF,
+	0xF2, 0x1D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd230[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xF5, 0x00, 0xFF, 0xFF,
+	0xF3, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd231[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xF6, 0x2E, 0xFF, 0xFF,
+	0xF4, 0x32, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd232[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xF7, 0x00, 0xFF, 0xFF,
+	0xF5, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd233[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xF8, 0x3D, 0xFF, 0xFF,
+	0xF6, 0x44, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd234[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xF9, 0x00, 0xFF, 0xFF,
+	0xF7, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd235[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xFA, 0x4C, 0xFF, 0xFF,
+	0xF8, 0x54, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd236[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xFF, 0x02, 0xFF, 0xFF,
+	0xF9, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd237[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xFB, 0x01, 0xFF, 0xFF,
+	0xFA, 0x63, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd238[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x00, 0x00, 0xFF, 0xFF,
+	0xFF, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd239[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x01, 0x59, 0xFF, 0xFF,
+	0xFB, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd240[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x02, 0x00, 0xFF, 0xFF,
+	0x00, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd241[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x03, 0x66, 0xFF, 0xFF,
+	0x01, 0x71, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd242[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x04, 0x00, 0xFF, 0xFF,
+	0x02, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd243[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x05, 0x73, 0xFF, 0xFF,
+	0x03, 0x7D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd244[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x06, 0x00, 0xFF, 0xFF,
+	0x04, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd245[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x07, 0xA0, 0xFF, 0xFF,
+	0x05, 0x89, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd246[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x08, 0x00, 0xFF, 0xFF,
+	0x06, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd247[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x09, 0xC7, 0xFF, 0xFF,
+	0x07, 0xB2, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd248[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x0A, 0x01, 0xFF, 0xFF,
+	0x08, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd249[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x0B, 0x0C, 0xFF, 0xFF,
+	0x09, 0xD5, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd250[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x0C, 0x01, 0xFF, 0xFF,
+	0x0A, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd251[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x0D, 0x46, 0xFF, 0xFF,
+	0x0B, 0x0D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd252[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x0E, 0x01, 0xFF, 0xFF,
+	0x0C, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd253[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x0F, 0xA4, 0xFF, 0xFF,
+	0x0D, 0x3B, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd254[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x10, 0x01, 0xFF, 0xFF,
+	0x0E, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd255[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x11, 0xF1, 0xFF, 0xFF,
+	0x0F, 0x87, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd256[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x12, 0x01, 0xFF, 0xFF,
+	0x10, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd257[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x13, 0xF3, 0xFF, 0xFF,
+	0x11, 0xC6, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd258[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x14, 0x02, 0xFF, 0xFF,
+	0x12, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd259[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x15, 0x36, 0xFF, 0xFF,
+	0x13, 0xC8, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd260[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x16, 0x02, 0xFF, 0xFF,
+	0x14, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd261[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x17, 0x7B, 0xFF, 0xFF,
+	0x15, 0x04, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd262[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x18, 0x02, 0xFF, 0xFF,
+	0x16, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd263[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x19, 0xA3, 0xFF, 0xFF,
+	0x17, 0x47, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd264[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x1A, 0x02, 0xFF, 0xFF,
+	0x18, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd265[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x1B, 0xD6, 0xFF, 0xFF,
+	0x19, 0x72, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd266[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x1C, 0x02, 0xFF, 0xFF,
+	0x1A, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd267[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x1D, 0xF9, 0xFF, 0xFF,
+	0x1B, 0xAC, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd268[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x1E, 0x03, 0xFF, 0xFF,
+	0x1C, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd269[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x1F, 0x26, 0xFF, 0xFF,
+	0x1D, 0xD3, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd270[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x20, 0x03, 0xFF, 0xFF,
+	0x1E, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd271[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x21, 0x34, 0xFF, 0xFF,
+	0x1F, 0x07, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd272[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x22, 0x03, 0xFF, 0xFF,
+	0x20, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd273[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x23, 0x43, 0xFF, 0xFF,
+	0x21, 0x17, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd274[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x24, 0x03, 0xFF, 0xFF,
+	0x22, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd275[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x25, 0x55, 0xFF, 0xFF,
+	0x23, 0x29, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd276[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x26, 0x03, 0xFF, 0xFF,
+	0x24, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd277[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x27, 0x6A, 0xFF, 0xFF,
+	0x25, 0x3D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd278[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x28, 0x03, 0xFF, 0xFF,
+	0x26, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd279[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x29, 0x81, 0xFF, 0xFF,
+	0x27, 0x52, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd280[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x2A, 0x03, 0xFF, 0xFF,
+	0x28, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd281[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x2B, 0x9F, 0xFF, 0xFF,
+	0x29, 0x6E, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd282[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x2D, 0x03, 0xFF, 0xFF,
+	0x2A, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd283[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x2F, 0xD1, 0xFF, 0xFF,
+	0x2B, 0x8D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd284[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x30, 0x03, 0xFF, 0xFF,
+	0x2D, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd285[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x31, 0xFF, 0xFF, 0xFF,
+	0x2F, 0xB0, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd286[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x32, 0x00, 0xFF, 0xFF,
+	0x30, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd287[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x33, 0x00, 0xFF, 0xFF,
+	0x31, 0xBF, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd288[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x34, 0x00, 0xFF, 0xFF,
+	0x32, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd289[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x35, 0x09, 0xFF, 0xFF,
+	0x33, 0x10, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd290[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x36, 0x00, 0xFF, 0xFF,
+	0x34, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd291[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x37, 0x1D, 0xFF, 0xFF,
+	0x35, 0x1D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd292[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x38, 0x00, 0xFF, 0xFF,
+	0x36, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd293[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x39, 0x2E, 0xFF, 0xFF,
+	0x37, 0x32, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd294[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x3A, 0x00, 0xFF, 0xFF,
+	0x38, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd295[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x3B, 0x3D, 0xFF, 0xFF,
+	0x39, 0x44, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd296[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x3D, 0x00, 0xFF, 0xFF,
+	0x3A, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd297[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x3F, 0x4C, 0xFF, 0xFF,
+	0x3B, 0x54, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd298[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x40, 0x00, 0xFF, 0xFF,
+	0x3D, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd299[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x41, 0x59, 0xFF, 0xFF,
+	0x3F, 0x63, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd300[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x42, 0x00, 0xFF, 0xFF,
+	0x40, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd301[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x43, 0x66, 0xFF, 0xFF,
+	0x41, 0x71, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd302[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x44, 0x00, 0xFF, 0xFF,
+	0x42, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd303[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x45, 0x73, 0xFF, 0xFF,
+	0x43, 0x7D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd304[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x46, 0x00, 0xFF, 0xFF,
+	0x44, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd305[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x47, 0xA0, 0xFF, 0xFF,
+	0x45, 0x89, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd306[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x48, 0x00, 0xFF, 0xFF,
+	0x46, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd307[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x49, 0xC7, 0xFF, 0xFF,
+	0x47, 0xB2, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd308[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x4A, 0x01, 0xFF, 0xFF,
+	0x48, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd309[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x4B, 0x0C, 0xFF, 0xFF,
+	0x49, 0xD5, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd310[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x4C, 0x01, 0xFF, 0xFF,
+	0x4A, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd311[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x4D, 0x46, 0xFF, 0xFF,
+	0x4B, 0x0D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd312[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x4E, 0x01, 0xFF, 0xFF,
+	0x4C, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd313[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x4F, 0xA4, 0xFF, 0xFF,
+	0x4D, 0x3B, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd314[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x50, 0x01, 0xFF, 0xFF,
+	0x4E, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd315[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x51, 0xF1, 0xFF, 0xFF,
+	0x4F, 0x87, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd316[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x52, 0x01, 0xFF, 0xFF,
+	0x50, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd317[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x53, 0xF3, 0xFF, 0xFF,
+	0x51, 0xC6, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd318[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x54, 0x02, 0xFF, 0xFF,
+	0x52, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd319[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x55, 0x36, 0xFF, 0xFF,
+	0x53, 0xC8, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd320[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x56, 0x02, 0xFF, 0xFF,
+	0x54, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd321[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x58, 0x7B, 0xFF, 0xFF,
+	0x55, 0x04, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd322[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x59, 0x02, 0xFF, 0xFF,
+	0x56, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd323[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x5A, 0xA3, 0xFF, 0xFF,
+	0x58, 0x47, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd324[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x5B, 0x02, 0xFF, 0xFF,
+	0x59, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd325[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x5C, 0xD6, 0xFF, 0xFF,
+	0x5A, 0x72, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd326[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x5D, 0x02, 0xFF, 0xFF,
+	0x5B, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd327[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x5E, 0xF9, 0xFF, 0xFF,
+	0x5C, 0xAC, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd328[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x5F, 0x03, 0xFF, 0xFF,
+	0x5D, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd329[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x60, 0x26, 0xFF, 0xFF,
+	0x5E, 0xD3, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd330[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x61, 0x03, 0xFF, 0xFF,
+	0x5F, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd331[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x62, 0x34, 0xFF, 0xFF,
+	0x60, 0x07, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd332[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x63, 0x03, 0xFF, 0xFF,
+	0x61, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd333[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x64, 0x43, 0xFF, 0xFF,
+	0x62, 0x17, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd334[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x65, 0x03, 0xFF, 0xFF,
+	0x63, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd335[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x66, 0x55, 0xFF, 0xFF,
+	0x64, 0x29, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd336[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x67, 0x03, 0xFF, 0xFF,
+	0x65, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd337[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x68, 0x6A, 0xFF, 0xFF,
+	0x66, 0x3D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd338[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x69, 0x03, 0xFF, 0xFF,
+	0x67, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd339[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x6A, 0x81, 0xFF, 0xFF,
+	0x68, 0x52, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd340[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x6B, 0x03, 0xFF, 0xFF,
+	0x69, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd341[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x6C, 0x9F, 0xFF, 0xFF,
+	0x6A, 0x6E, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd342[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x6D, 0x03, 0xFF, 0xFF,
+	0x6B, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd343[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x6E, 0xD1, 0xFF, 0xFF,
+	0x6C, 0x8D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd344[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x6F, 0x03, 0xFF, 0xFF,
+	0x6D, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd345[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x70, 0xFF, 0xFF, 0xFF,
+	0x6E, 0xB0, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd346[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x71, 0x00, 0xFF, 0xFF,
+	0x6F, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd347[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x72, 0x00, 0xFF, 0xFF,
+	0x70, 0xBF, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd348[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x73, 0x00, 0xFF, 0xFF,
+	0x71, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd349[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x74, 0x09, 0xFF, 0xFF,
+	0x72, 0x10, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd350[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x75, 0x00, 0xFF, 0xFF,
+	0x73, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd351[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x76, 0x1D, 0xFF, 0xFF,
+	0x74, 0x1D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd352[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x77, 0x00, 0xFF, 0xFF,
+	0x75, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd353[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x78, 0x2E, 0xFF, 0xFF,
+	0x76, 0x32, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd354[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x79, 0x00, 0xFF, 0xFF,
+	0x77, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd355[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x7A, 0x3D, 0xFF, 0xFF,
+	0x78, 0x44, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd356[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x7B, 0x00, 0xFF, 0xFF,
+	0x79, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd357[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x7C, 0x4C, 0xFF, 0xFF,
+	0x7A, 0x54, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd358[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x7D, 0x00, 0xFF, 0xFF,
+	0x7B, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd359[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x7E, 0x59, 0xFF, 0xFF,
+	0x7C, 0x63, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd360[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x7F, 0x00, 0xFF, 0xFF,
+	0x7D, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd361[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x80, 0x66, 0xFF, 0xFF,
+	0x7E, 0x71, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd362[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x81, 0x00, 0xFF, 0xFF,
+	0x7F, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd363[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x82, 0x73, 0xFF, 0xFF,
+	0x80, 0x7D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd364[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x83, 0x00, 0xFF, 0xFF,
+	0x81, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd365[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x84, 0xA0, 0xFF, 0xFF,
+	0x82, 0x89, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd366[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x85, 0x00, 0xFF, 0xFF,
+	0x83, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd367[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x86, 0xC7, 0xFF, 0xFF,
+	0x84, 0xB2, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd368[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x87, 0x01, 0xFF, 0xFF,
+	0x85, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd369[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x88, 0x0C, 0xFF, 0xFF,
+	0x86, 0xD5, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd370[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x89, 0x01, 0xFF, 0xFF,
+	0x87, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd371[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x8A, 0x46, 0xFF, 0xFF,
+	0x88, 0x0D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd372[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x8B, 0x01, 0xFF, 0xFF,
+	0x89, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd373[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x8C, 0xA4, 0xFF, 0xFF,
+	0x8A, 0x3B, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd374[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x8D, 0x01, 0xFF, 0xFF,
+	0x8B, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd375[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x8E, 0xF1, 0xFF, 0xFF,
+	0x8C, 0x87, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd376[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x8F, 0x01, 0xFF, 0xFF,
+	0x8D, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd377[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x90, 0xF3, 0xFF, 0xFF,
+	0x8E, 0xC6, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd378[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x91, 0x02, 0xFF, 0xFF,
+	0x8F, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd379[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x92, 0x36, 0xFF, 0xFF,
+	0x90, 0xC8, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd380[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x93, 0x02, 0xFF, 0xFF,
+	0x91, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd381[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x94, 0x7B, 0xFF, 0xFF,
+	0x92, 0x04, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd382[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x95, 0x02, 0xFF, 0xFF,
+	0x93, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd383[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x96, 0xA3, 0xFF, 0xFF,
+	0x94, 0x47, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd384[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x97, 0x02, 0xFF, 0xFF,
+	0x95, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd385[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x98, 0xD6, 0xFF, 0xFF,
+	0x96, 0x72, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd386[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x99, 0x02, 0xFF, 0xFF,
+	0x97, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd387[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x9A, 0xF9, 0xFF, 0xFF,
+	0x98, 0xAC, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd388[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x9B, 0x03, 0xFF, 0xFF,
+	0x99, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd389[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x9C, 0x26, 0xFF, 0xFF,
+	0x9A, 0xD3, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd390[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x9D, 0x03, 0xFF, 0xFF,
+	0x9B, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd391[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x9E, 0x34, 0xFF, 0xFF,
+	0x9C, 0x07, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd392[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x9F, 0x03, 0xFF, 0xFF,
+	0x9D, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd393[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xA0, 0x43, 0xFF, 0xFF,
+	0x9E, 0x17, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd394[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xA2, 0x03, 0xFF, 0xFF,
+	0x9F, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd395[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xA3, 0x55, 0xFF, 0xFF,
+	0xA0, 0x29, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd396[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xA4, 0x03, 0xFF, 0xFF,
+	0xA2, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd397[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xA5, 0x6A, 0xFF, 0xFF,
+	0xA3, 0x3D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd398[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xA6, 0x03, 0xFF, 0xFF,
+	0xA4, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd399[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xA7, 0x81, 0xFF, 0xFF,
+	0xA5, 0x52, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd400[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xA9, 0x03, 0xFF, 0xFF,
+	0xA6, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd401[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xAA, 0x9F, 0xFF, 0xFF,
+	0xA7, 0x6E, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd402[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xAB, 0x03, 0xFF, 0xFF,
+	0xA9, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd403[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xAC, 0xD1, 0xFF, 0xFF,
+	0xAA, 0x8D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd404[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xAD, 0x03, 0xFF, 0xFF,
+	0xAB, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd405[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xAE, 0xFF, 0xFF, 0xFF,
+	0xAC, 0xB0, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd406[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xAF, 0x00, 0xFF, 0xFF,
+	0xAD, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd407[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xB0, 0x00, 0xFF, 0xFF,
+	0xAE, 0xBF, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd408[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xB1, 0x00, 0xFF, 0xFF,
+	0xAF, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd409[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xB2, 0x09, 0xFF, 0xFF,
+	0xB0, 0x10, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd410[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xB3, 0x00, 0xFF, 0xFF,
+	0xB1, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd411[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xB4, 0x1D, 0xFF, 0xFF,
+	0xB2, 0x1D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd412[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xB5, 0x00, 0xFF, 0xFF,
+	0xB3, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd413[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xB6, 0x2E, 0xFF, 0xFF,
+	0xB4, 0x32, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd414[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xB7, 0x00, 0xFF, 0xFF,
+	0xB5, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd415[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xB8, 0x3D, 0xFF, 0xFF,
+	0xB6, 0x44, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd416[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xB9, 0x00, 0xFF, 0xFF,
+	0xB7, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd417[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xBA, 0x4C, 0xFF, 0xFF,
+	0xB8, 0x54, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd418[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xBB, 0x00, 0xFF, 0xFF,
+	0xB9, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd419[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xBC, 0x59, 0xFF, 0xFF,
+	0xBA, 0x63, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd420[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xBD, 0x00, 0xFF, 0xFF,
+	0xBB, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd421[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xBE, 0x66, 0xFF, 0xFF,
+	0xBC, 0x71, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd422[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xBF, 0x00, 0xFF, 0xFF,
+	0xBD, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd423[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xC0, 0x73, 0xFF, 0xFF,
+	0xBE, 0x7D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd424[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xC1, 0x00, 0xFF, 0xFF,
+	0xBF, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd425[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xC2, 0xA0, 0xFF, 0xFF,
+	0xC0, 0x89, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd426[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xC3, 0x00, 0xFF, 0xFF,
+	0xC1, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd427[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xC4, 0xC7, 0xFF, 0xFF,
+	0xC2, 0xB2, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd428[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xC5, 0x01, 0xFF, 0xFF,
+	0xC3, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd429[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xC6, 0x0C, 0xFF, 0xFF,
+	0xC4, 0xD5, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd430[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xC7, 0x01, 0xFF, 0xFF,
+	0xC5, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd431[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xC8, 0x46, 0xFF, 0xFF,
+	0xC6, 0x0D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd432[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xC9, 0x01, 0xFF, 0xFF,
+	0xC7, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd433[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xCA, 0xA4, 0xFF, 0xFF,
+	0xC8, 0x3B, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd434[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xCB, 0x01, 0xFF, 0xFF,
+	0xC9, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd435[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xCC, 0xF1, 0xFF, 0xFF,
+	0xCA, 0x87, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd436[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xCD, 0x01, 0xFF, 0xFF,
+	0xCB, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd437[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xCE, 0xF3, 0xFF, 0xFF,
+	0xCC, 0xC6, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd438[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xCF, 0x02, 0xFF, 0xFF,
+	0xCD, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd439[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xD0, 0x36, 0xFF, 0xFF,
+	0xCE, 0xC8, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd440[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xD1, 0x02, 0xFF, 0xFF,
+	0xCF, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd441[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xD2, 0x7B, 0xFF, 0xFF,
+	0xD0, 0x04, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd442[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xD3, 0x02, 0xFF, 0xFF,
+	0xD1, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd443[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xD4, 0xA3, 0xFF, 0xFF,
+	0xD2, 0x47, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd444[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xD5, 0x02, 0xFF, 0xFF,
+	0xD3, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd445[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xD6, 0xD6, 0xFF, 0xFF,
+	0xD4, 0x72, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd446[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xD7, 0x02, 0xFF, 0xFF,
+	0xD5, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd447[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xD8, 0xF9, 0xFF, 0xFF,
+	0xD6, 0xAC, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd448[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xD9, 0x03, 0xFF, 0xFF,
+	0xD7, 0x02, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd449[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xDA, 0x26, 0xFF, 0xFF,
+	0xD8, 0xD3, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd450[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xDB, 0x03, 0xFF, 0xFF,
+	0xD9, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd451[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xDC, 0x34, 0xFF, 0xFF,
+	0xDA, 0x07, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd452[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xDD, 0x03, 0xFF, 0xFF,
+	0xDB, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd453[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xDE, 0x43, 0xFF, 0xFF,
+	0xDC, 0x17, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd454[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xDF, 0x03, 0xFF, 0xFF,
+	0xDD, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd455[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xE0, 0x55, 0xFF, 0xFF,
+	0xDE, 0x29, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd456[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xE1, 0x03, 0xFF, 0xFF,
+	0xDF, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd457[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xE2, 0x6A, 0xFF, 0xFF,
+	0xE0, 0x3D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd458[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xE3, 0x03, 0xFF, 0xFF,
+	0xE1, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd459[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xE4, 0x81, 0xFF, 0xFF,
+	0xE2, 0x52, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd460[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xE5, 0x03, 0xFF, 0xFF,
+	0xE3, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd461[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xE6, 0x9F, 0xFF, 0xFF,
+	0xE4, 0x6E, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd462[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xE7, 0x03, 0xFF, 0xFF,
+	0xE5, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd463[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xE8, 0xD1, 0xFF, 0xFF,
+	0xE6, 0x8D, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd464[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xE9, 0x03, 0xFF, 0xFF,
+	0xE7, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd465[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xEA, 0xFF, 0xFF, 0xFF,
+	0xE8, 0xB0, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd466[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xFF, 0x04, 0xFF, 0xFF,
+	0xE9, 0x03, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd467[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x07, 0x00, 0xFF, 0xFF,
+	0xEA, 0xBF, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd468[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x08, 0x92, 0xFF, 0xFF,
+	0xFF, 0x04, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd469[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xFF, 0x00, 0xFF, 0xFF,
+	0x07, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd470[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xFB, 0x01, 0xFF, 0xFF,
+	0x08, 0x92, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd471[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xD3, 0x09, 0xFF, 0xFF,
+	0xFF, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd472[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0xD4, 0x04, 0xFF, 0xFF,
+	0xFB, 0x01, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd473[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x51, 0x00, 0xFF, 0xFF,
+	0xD3, 0x09, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd474[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x53, 0x2c, 0xFF, 0xFF,
+	0xD4, 0x04, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd475[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x55, 0x00, 0xFF, 0xFF,
+	0x51, 0x7F, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd476[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x11, 0x00, 0xFF, 0xFF,
+	0x53, 0x2C, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd477[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x29, 0x00, 0xFF, 0xFF,
+	0x55, 0x00, 0xFF, 0xFF,
 };
 
 static char nt35596_1080p_skuk_video_on_cmd478[] = {
 	0x02, 0x00, 0x29, 0xC0,
-	0x51, 0x7F, 0xFF, 0xFF,
+	0x11, 0x00, 0xFF, 0xFF,
+};
+
+static char nt35596_1080p_skuk_video_on_cmd479[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0x29, 0x00, 0xFF, 0xFF,
 };
 
 static struct mipi_dsi_cmd nt35596_1080p_skuk_video_on_command[] = {
@@ -2549,7 +2554,7 @@
 	{0x8, nt35596_1080p_skuk_video_on_cmd86, 0x00},
 	{0x8, nt35596_1080p_skuk_video_on_cmd87, 0x00},
 	{0x8, nt35596_1080p_skuk_video_on_cmd88, 0x00},
-	{0x8, nt35596_1080p_skuk_video_on_cmd89, 0x05},
+	{0x8, nt35596_1080p_skuk_video_on_cmd89, 0x00},
 	{0x8, nt35596_1080p_skuk_video_on_cmd90, 0x00},
 	{0x8, nt35596_1080p_skuk_video_on_cmd91, 0x00},
 	{0x8, nt35596_1080p_skuk_video_on_cmd92, 0x00},
@@ -2697,7 +2702,7 @@
 	{0x8, nt35596_1080p_skuk_video_on_cmd234, 0x00},
 	{0x8, nt35596_1080p_skuk_video_on_cmd235, 0x00},
 	{0x8, nt35596_1080p_skuk_video_on_cmd236, 0x00},
-	{0x8, nt35596_1080p_skuk_video_on_cmd237, 0x05},
+	{0x8, nt35596_1080p_skuk_video_on_cmd237, 0x00},
 	{0x8, nt35596_1080p_skuk_video_on_cmd238, 0x00},
 	{0x8, nt35596_1080p_skuk_video_on_cmd239, 0x00},
 	{0x8, nt35596_1080p_skuk_video_on_cmd240, 0x00},
@@ -2930,18 +2935,19 @@
 	{0x8, nt35596_1080p_skuk_video_on_cmd467, 0x00},
 	{0x8, nt35596_1080p_skuk_video_on_cmd468, 0x00},
 	{0x8, nt35596_1080p_skuk_video_on_cmd469, 0x00},
-	{0x8, nt35596_1080p_skuk_video_on_cmd470, 0x05},
+	{0x8, nt35596_1080p_skuk_video_on_cmd470, 0x00},
 	{0x8, nt35596_1080p_skuk_video_on_cmd471, 0x00},
-	{0x8, nt35596_1080p_skuk_video_on_cmd472, 0x00},
+	{0x8, nt35596_1080p_skuk_video_on_cmd472, 0x05},
 	{0x8, nt35596_1080p_skuk_video_on_cmd473, 0x00},
 	{0x8, nt35596_1080p_skuk_video_on_cmd474, 0x00},
 	{0x8, nt35596_1080p_skuk_video_on_cmd475, 0x00},
-	{0x8, nt35596_1080p_skuk_video_on_cmd476, 0x78},
+	{0x8, nt35596_1080p_skuk_video_on_cmd476, 0x00},
 	{0x8, nt35596_1080p_skuk_video_on_cmd477, 0x00},
-	{0x8, nt35596_1080p_skuk_video_on_cmd478, 0x00}
+	{0x8, nt35596_1080p_skuk_video_on_cmd478, 0x78},
+	{0x8, nt35596_1080p_skuk_video_on_cmd479, 0x00}
 };
 
-#define NT35596_1080P_SKUK_VIDEO_ON_COMMAND 479
+#define NT35596_1080P_SKUK_VIDEO_ON_COMMAND 480
 
 
 static char nt35596_1080p_skuk_videooff_cmd0[] = {
diff --git a/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h b/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h
new file mode 100644
index 0000000..376c681
--- /dev/null
+++ b/dev/gcdb/display/include/panel_sharp_wqxga_dualdsi_video.h
@@ -0,0 +1,152 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  * Neither the name of The Linux Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PANEL_SHARP_WQXGA_DUALDSI_VIDEO_H_
+#define _PANEL_SHARP_WQXGA_DUALDSI_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files                                                              */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration                                                       */
+/*---------------------------------------------------------------------------*/
+static struct panel_config sharp_wqxga_dualdsi_video_panel_data = {
+	"qcom,mdss_dsi_sharp_wqxga_video_0", "dsi:0:", "qcom,mdss-dsi-panel",
+	10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 1, 0, 0, 0, 0, 0, 25, 1, 0,
+	"qcom,mdss_dsi_sharp_wqxga_video_1"
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution                                                          */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution sharp_wqxga_dualdsi_video_panel_res = {
+	1600, 2560, 76, 32, 16, 0, 4, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information                                                   */
+/*---------------------------------------------------------------------------*/
+static struct color_info sharp_wqxga_dualdsi_video_color = {
+	24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information                                          */
+/*---------------------------------------------------------------------------*/
+static char sharp_wqxga_dualdsi_video_on_cmd0[] = {
+	0x11, 0x00, 0x05, 0x80
+};
+
+static char sharp_wqxga_dualdsi_video_on_cmd1[] = {
+	0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd sharp_wqxga_dualdsi_video_on_command[] = {
+	{0x4, sharp_wqxga_dualdsi_video_on_cmd0, 0x0a},
+	{0x4, sharp_wqxga_dualdsi_video_on_cmd1, 0x0a}
+};
+
+#define SHARP_WQXGA_DUALDSI_VIDEO_ON_COMMAND 2
+
+
+static char sharp_wqxga_dualdsi_videooff_cmd0[] = {
+	0x28, 0x00, 0x05, 0x80
+};
+
+static char sharp_wqxga_dualdsi_videooff_cmd1[] = {
+	0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd sharp_wqxga_dualdsi_video_off_command[] = {
+	{0x4, sharp_wqxga_dualdsi_videooff_cmd0, 0x32},
+	{0x4, sharp_wqxga_dualdsi_videooff_cmd1, 0x78}
+};
+
+#define SHARP_WQXGA_DUALDSI_VIDEO_OFF_COMMAND 2
+
+static struct command_state sharp_wqxga_dualdsi_video_state = {
+	0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information                                            */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info sharp_wqxga_dualdsi_video_command_panel = {
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information                                              */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info sharp_wqxga_dualdsi_video_video_panel = {
+	0, 0, 0, 0, 1, 1, 1, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration                                                        */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration sharp_wqxga_dualdsi_video_lane_config = {
+	4, 0, 1, 1, 1, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing                                                              */
+/*---------------------------------------------------------------------------*/
+static const uint32_t sharp_wqxga_dualdsi_video_timings[] = {
+	0x32, 0x36, 0x24, 0x00, 0x66, 0x68, 0x28, 0x38,  0x2a, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing sharp_wqxga_dualdsi_video_timing_info = {
+	0x0, 0x04, 0x07, 0x0d
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence                                                      */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence sharp_wqxga_dualdsi_video_reset_seq = {
+	{1, 0, 1, }, {10, 10, 120, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting                                                         */
+/*---------------------------------------------------------------------------*/
+static struct backlight sharp_wqxga_dualdsi_video_backlight = {
+	1, 1, 4095, 100, 1, "PMIC_8941"		/* BL_WLED */
+};
+
+#define SHARP_WQXGA_DUALDSI_VIDEO_SIGNATURE 0x210000
+
+#endif /*_PANEL_SHARP_WQXGA_DUALDSI_VIDEO_H_*/
diff --git a/dev/gcdb/display/panel_display.c b/dev/gcdb/display/panel_display.c
index e34d966..427a548 100644
--- a/dev/gcdb/display/panel_display.c
+++ b/dev/gcdb/display/panel_display.c
@@ -74,6 +74,8 @@
 		pinfo->lcdc.pipe_swap = 1;
 	if (pstruct->paneldata->panel_operating_mode & SPLIT_DISPLAY_FLAG)
 		pinfo->lcdc.split_display = 1;
+	if (pstruct->paneldata->panel_operating_mode & DST_SPLIT_FLAG)
+		pinfo->lcdc.dst_split = 1;
 
 	/* Color setting*/
 	pinfo->lcdc.border_clr = pstruct->color->border_color;
@@ -106,7 +108,7 @@
 	}
 	pinfo->bpp = pstruct->color->color_format;
 	pinfo->clk_rate = pstruct->paneldata->panel_clockrate;
-	pinfo->rotation = pstruct->paneldata->panel_orientation;
+	pinfo->orientation = pstruct->paneldata->panel_orientation;
 	pinfo->mipi.interleave_mode = pstruct->paneldata->interleave_mode;
 	pinfo->mipi.broadcast = pstruct->paneldata->panel_broadcast_mode;
 	pinfo->mipi.vc = pstruct->paneldata->dsi_virtualchannel_id;
diff --git a/dev/gcdb/display/panel_display.h b/dev/gcdb/display/panel_display.h
index 676bd69..a6843ce 100755
--- a/dev/gcdb/display/panel_display.h
+++ b/dev/gcdb/display/panel_display.h
@@ -44,6 +44,7 @@
 #define DUAL_PIPE_FLAG 0x2
 #define PIPE_SWAP_FLAG 0x4
 #define SPLIT_DISPLAY_FLAG 0x8
+#define DST_SPLIT_FLAG 0x10
 
 #define MAX_PANEL_ID_LEN 64
 /*---------------------------------------------------------------------------*/
diff --git a/dev/pmic/pm8x41/include/pm8x41.h b/dev/pmic/pm8x41/include/pm8x41.h
index 5f87bcb..472e69f 100644
--- a/dev/pmic/pm8x41/include/pm8x41.h
+++ b/dev/pmic/pm8x41/include/pm8x41.h
@@ -79,6 +79,10 @@
 #define CBLPWR_N                64
 #define KPDPWR_N                128
 
+/*Target power off reasons*/
+#define KPDPWR_AND_RESIN        32
+#define STAGE3                  128
+
 struct pm8x41_gpio {
 	int direction;
 	int output_buffer;
@@ -203,6 +207,8 @@
 int pm8x41_ldo_control(struct pm8x41_ldo *ldo, uint8_t enable);
 uint8_t pm8x41_get_pmic_rev();
 uint8_t pm8x41_get_pon_reason();
+uint8_t pm8x41_get_pon_poff_reason1();
+uint8_t pm8x41_get_pon_poff_reason2();
 uint32_t pm8x41_get_pwrkey_is_pressed();
 void pm8x41_config_output_mpp(struct pm8x41_mpp *mpp);
 void pm8x41_enable_mpp(struct pm8x41_mpp *mpp, enum mpp_en_ctl enable);
diff --git a/dev/pmic/pm8x41/include/pm8x41_hw.h b/dev/pmic/pm8x41/include/pm8x41_hw.h
index 4a0d803..9d05219 100644
--- a/dev/pmic/pm8x41/include/pm8x41_hw.h
+++ b/dev/pmic/pm8x41/include/pm8x41_hw.h
@@ -65,6 +65,8 @@
 #define PON_PON_REASON1                       0x808
 #define PON_WARMBOOT_STATUS1                  0x80A
 #define PON_WARMBOOT_STATUS2                  0x80B
+#define PON_POFF_REASON1                      0x80C
+#define PON_POFF_REASON2                      0x80D
 #define PON_INT_RT_STS                        0x810
 #define PON_INT_SET_TYPE                      0x811
 #define PON_INT_POLARITY_HIGH                 0x812
diff --git a/dev/pmic/pm8x41/include/pm8x41_wled.h b/dev/pmic/pm8x41/include/pm8x41_wled.h
index 8ad7370..0fe7975 100644
--- a/dev/pmic/pm8x41/include/pm8x41_wled.h
+++ b/dev/pmic/pm8x41/include/pm8x41_wled.h
@@ -77,3 +77,5 @@
 void pm8x41_wled_led_mod_enable(uint8_t enable);
 void pm8x41_wled_enable(uint8_t enable);
 void pm8x41_wled_config_slave_id(uint8_t slave_id);
+uint8_t pm8x41_wled_reg_read(uint32_t addr);
+void pm8x41_wled_reg_write(uint32_t addr, uint8_t val);
diff --git a/dev/pmic/pm8x41/pm8x41.c b/dev/pmic/pm8x41/pm8x41.c
index 480e6e8..3b9783d 100644
--- a/dev/pmic/pm8x41/pm8x41.c
+++ b/dev/pmic/pm8x41/pm8x41.c
@@ -35,6 +35,13 @@
 #include <pm8x41.h>
 #include <platform/timer.h>
 
+static uint8_t mpp_slave_id;
+
+uint8_t pmi8994_config_mpp_slave_id(uint8_t slave_id)
+{
+	mpp_slave_id = slave_id;
+}
+
 /* SPMI helper functions */
 uint8_t pm8x41_reg_read(uint32_t addr)
 {
@@ -380,20 +387,30 @@
 	return REG_READ(PON_PON_REASON1);
 }
 
+uint8_t pm8x41_get_pon_poff_reason1()
+{
+	return REG_READ(PON_POFF_REASON1);
+}
+
+uint8_t pm8x41_get_pon_poff_reason2()
+{
+	return REG_READ(PON_POFF_REASON2);
+}
+
 void pm8x41_enable_mpp(struct pm8x41_mpp *mpp, enum mpp_en_ctl enable)
 {
 	ASSERT(mpp);
 
-	REG_WRITE(mpp->base + MPP_EN_CTL, enable << MPP_EN_CTL_ENABLE_SHIFT);
+	REG_WRITE(((mpp->base + MPP_EN_CTL) + (mpp_slave_id << 16)), enable << MPP_EN_CTL_ENABLE_SHIFT);
 }
 
 void pm8x41_config_output_mpp(struct pm8x41_mpp *mpp)
 {
 	ASSERT(mpp);
 
-	REG_WRITE(mpp->base + MPP_DIG_VIN_CTL, mpp->vin);
+	REG_WRITE(((mpp->base + MPP_DIG_VIN_CTL) + (mpp_slave_id << 16)), mpp->vin);
 
-	REG_WRITE(mpp->base + MPP_MODE_CTL, mpp->mode | (MPP_DIGITAL_OUTPUT << MPP_MODE_CTL_MODE_SHIFT));
+	REG_WRITE(((mpp->base + MPP_MODE_CTL) + (mpp_slave_id << 16)), mpp->mode | (MPP_DIGITAL_OUTPUT << MPP_MODE_CTL_MODE_SHIFT));
 }
 
 uint8_t pm8x41_get_is_cold_boot()
diff --git a/dev/pmic/pm8x41/pm8x41_wled.c b/dev/pmic/pm8x41/pm8x41_wled.c
index 42283e1..9c3b6d3 100644
--- a/dev/pmic/pm8x41/pm8x41_wled.c
+++ b/dev/pmic/pm8x41/pm8x41_wled.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
 
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -33,7 +33,7 @@
 
 static uint8_t wled_slave_id;
 
-static void wled_reg_write(uint32_t addr, uint8_t val)
+void pm8x41_wled_reg_write(uint32_t addr, uint8_t val)
 {
 	uint32_t new_addr;
 	if (wled_slave_id) {
@@ -45,6 +45,21 @@
 	}
 }
 
+uint8_t pm8x41_wled_reg_read(uint32_t addr)
+{
+	uint32_t new_addr;
+	uint8_t val;
+
+	if (wled_slave_id) {
+		new_addr = addr + (wled_slave_id << 16);
+		val = REG_READ(new_addr);
+	} else {
+		new_addr = addr + (DEFAULT_SLAVE_ID << 16);
+		val = REG_READ(new_addr);
+	}
+	return val;
+}
+
 void pm8x41_wled_config_slave_id(uint8_t slave_id)
 {
 	wled_slave_id = slave_id;
@@ -57,22 +72,22 @@
 		return;
 	}
 
-	wled_reg_write(PM_WLED_MODULATION_SCHEME, wled_ctrl->mod_scheme);
+	pm8x41_wled_reg_write(PM_WLED_MODULATION_SCHEME, wled_ctrl->mod_scheme);
 
-	wled_reg_write(PM_WLED_LED1_BRIGHTNESS_LSB, (wled_ctrl->led1_brightness & 0xFF));
-	wled_reg_write(PM_WLED_LED1_BRIGHTNESS_MSB, ((wled_ctrl->led1_brightness >> 8) & 0xFF));
-	wled_reg_write(PM_WLED_LED2_BRIGHTNESS_LSB, (wled_ctrl->led2_brightness & 0xFF));
-	wled_reg_write(PM_WLED_LED2_BRIGHTNESS_MSB, ((wled_ctrl->led2_brightness >> 8) & 0xFF));
-	wled_reg_write(PM_WLED_LED3_BRIGHTNESS_LSB, (wled_ctrl->led3_brightness & 0xFF));
-	wled_reg_write(PM_WLED_LED3_BRIGHTNESS_MSB, ((wled_ctrl->led3_brightness >> 8) & 0xFF));
+	pm8x41_wled_reg_write(PM_WLED_LED1_BRIGHTNESS_LSB, (wled_ctrl->led1_brightness & 0xFF));
+	pm8x41_wled_reg_write(PM_WLED_LED1_BRIGHTNESS_MSB, ((wled_ctrl->led1_brightness >> 8) & 0xFF));
+	pm8x41_wled_reg_write(PM_WLED_LED2_BRIGHTNESS_LSB, (wled_ctrl->led2_brightness & 0xFF));
+	pm8x41_wled_reg_write(PM_WLED_LED2_BRIGHTNESS_MSB, ((wled_ctrl->led2_brightness >> 8) & 0xFF));
+	pm8x41_wled_reg_write(PM_WLED_LED3_BRIGHTNESS_LSB, (wled_ctrl->led3_brightness & 0xFF));
+	pm8x41_wled_reg_write(PM_WLED_LED3_BRIGHTNESS_MSB, ((wled_ctrl->led3_brightness >> 8) & 0xFF));
 
-	wled_reg_write(PM_WLED_MAX_DUTY_CYCLE, wled_ctrl->max_duty_cycle);
-	wled_reg_write(PM_WLED_OVP, wled_ctrl->ovp);
-	wled_reg_write(LEDn_FULL_SCALE_CURRENT(1), wled_ctrl->full_current_scale);
-	wled_reg_write(LEDn_FULL_SCALE_CURRENT(2), wled_ctrl->full_current_scale);
-	wled_reg_write(LEDn_FULL_SCALE_CURRENT(3), wled_ctrl->full_current_scale);
+	pm8x41_wled_reg_write(PM_WLED_MAX_DUTY_CYCLE, wled_ctrl->max_duty_cycle);
+	pm8x41_wled_reg_write(PM_WLED_OVP, wled_ctrl->ovp);
+	pm8x41_wled_reg_write(LEDn_FULL_SCALE_CURRENT(1), wled_ctrl->full_current_scale);
+	pm8x41_wled_reg_write(LEDn_FULL_SCALE_CURRENT(2), wled_ctrl->full_current_scale);
+	pm8x41_wled_reg_write(LEDn_FULL_SCALE_CURRENT(3), wled_ctrl->full_current_scale);
 
-	wled_reg_write(PM_WLED_FDBCK_CONTROL, wled_ctrl->fdbck);
+	pm8x41_wled_reg_write(PM_WLED_FDBCK_CONTROL, wled_ctrl->fdbck);
 	dprintf(SPEW, "WLED Configuration Success.\n");
 
 }
@@ -87,7 +102,7 @@
 			PM_WLED_LED3_SINK_MASK;
 	}
 
-	wled_reg_write(PM_WLED_CURRENT_SINK, value);
+	pm8x41_wled_reg_write(PM_WLED_CURRENT_SINK, value);
 
 	dprintf(SPEW, "WLED Sink Success\n");
 
@@ -103,7 +118,7 @@
 			PM_WLED_LED3_ILED_SYNC_MASK;
 	}
 
-	wled_reg_write(PM_WLED_ILED_SYNC_BIT, value);
+	pm8x41_wled_reg_write(PM_WLED_ILED_SYNC_BIT, value);
 
 	dprintf(SPEW, "WLED ILED Sync Success\n");
 
@@ -116,9 +131,9 @@
 	if (enable)
 		value = PM_WLED_LED_MODULATOR_EN;
 
-	wled_reg_write(PM_WLED_LED_CTNL_REG(1), value);
-	wled_reg_write(PM_WLED_LED_CTNL_REG(2), value);
-	wled_reg_write(PM_WLED_LED_CTNL_REG(3), value);
+	pm8x41_wled_reg_write(PM_WLED_LED_CTNL_REG(1), value);
+	pm8x41_wled_reg_write(PM_WLED_LED_CTNL_REG(2), value);
+	pm8x41_wled_reg_write(PM_WLED_LED_CTNL_REG(3), value);
 
 	dprintf(SPEW, "WLED LED Module Enable Success\n");
 
@@ -131,7 +146,7 @@
 	if (enable)
 		value = PM_WLED_ENABLE_MODULE_MASK;
 
-	wled_reg_write(PM_WLED_ENABLE, value);
+	pm8x41_wled_reg_write(PM_WLED_ENABLE, value);
 
 	dprintf(SPEW, "WLED Enable Success\n");
 
diff --git a/dev/qpnp_wled/include/qpnp_wled.h b/dev/qpnp_wled/include/qpnp_wled.h
new file mode 100644
index 0000000..751509d
--- /dev/null
+++ b/dev/qpnp_wled/include/qpnp_wled.h
@@ -0,0 +1,253 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+ *   * Neither the name of The Linux Foundation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bits.h>
+#include <debug.h>
+#include <reg.h>
+
+/* base addresses */
+#define QPNP_WLED_CTRL_BASE                    0xd800
+#define QPNP_WLED_SINK_BASE                    0xd900
+#define QPNP_WLED_IBB_BASE                     0xdc00
+#define QPNP_WLED_LAB_BASE                     0xde00
+
+/* ctrl registers */
+#define QPNP_WLED_EN_REG(b)                    (b + 0x46)
+#define QPNP_WLED_FDBK_OP_REG(b)               (b + 0x48)
+#define QPNP_WLED_VREF_REG(b)                  (b + 0x49)
+#define QPNP_WLED_BOOST_DUTY_REG(b)            (b + 0x4B)
+#define QPNP_WLED_SWITCH_FREQ_REG(b)           (b + 0x4C)
+#define QPNP_WLED_OVP_REG(b)                   (b + 0x4D)
+#define QPNP_WLED_ILIM_REG(b)                  (b + 0x4E)
+
+#define QPNP_WLED_EN_MASK                      0x7F
+#define QPNP_WLED_EN_SHIFT                     7
+#define QPNP_WLED_FDBK_OP_MASK                 0xF8
+#define QPNP_WLED_VREF_MASK                    0xF0
+#define QPNP_WLED_VREF_STEP_MV                 25
+#define QPNP_WLED_VREF_MIN_MV                  300
+#define QPNP_WLED_VREF_MAX_MV                  675
+#define QPNP_WLED_DFLT_VREF_MV                 350
+#define QPNP_WLED_ILIM_MASK                    0xF8
+#define QPNP_WLED_ILIM_MIN_MA                  105
+#define QPNP_WLED_ILIM_MAX_MA                  1980
+#define QPNP_WLED_ILIM_STEP_MA                 280
+#define QPNP_WLED_DFLT_ILIM_MA                 980
+#define QPNP_WLED_BOOST_DUTY_MASK              0xFC
+#define QPNP_WLED_BOOST_DUTY_STEP_NS           52
+#define QPNP_WLED_BOOST_DUTY_MIN_NS            26
+#define QPNP_WLED_BOOST_DUTY_MAX_NS            156
+#define QPNP_WLED_DEF_BOOST_DUTY_NS            104
+#define QPNP_WLED_DFLT_HYB_THRES               625
+#define QPNP_WLED_SWITCH_FREQ_MASK             0xF0
+#define QPNP_WLED_SWITCH_FREQ_800_KHZ          800
+#define QPNP_WLED_SWITCH_FREQ_1600_KHZ         1600
+#define QPNP_WLED_OVP_MASK                     0xFC
+#define QPNP_WLED_OVP_17800_MV                 17800
+#define QPNP_WLED_OVP_19400_MV                 19400
+#define QPNP_WLED_OVP_29500_MV                 29500
+#define QPNP_WLED_OVP_31000_MV                 31000
+
+/* sink registers */
+#define QPNP_WLED_CURR_SINK_REG(b)             (b + 0x46)
+#define QPNP_WLED_SYNC_REG(b)                  (b + 0x47)
+#define QPNP_WLED_MOD_REG(b)                   (b + 0x4A)
+#define QPNP_WLED_HYB_THRES_REG(b)             (b + 0x4B)
+#define QPNP_WLED_MOD_EN_REG(b, n)             (b + 0x50 + (n * 0x10))
+#define QPNP_WLED_SYNC_DLY_REG(b, n)           (QPNP_WLED_MOD_EN_REG(b, n) + 0x01)
+#define QPNP_WLED_FS_CURR_REG(b, n)            (QPNP_WLED_MOD_EN_REG(b, n) + 0x02)
+#define QPNP_WLED_CABC_REG(b, n)               (QPNP_WLED_MOD_EN_REG(b, n) + 0x06)
+#define QPNP_WLED_BRIGHT_LSB_REG(b, n)         (QPNP_WLED_MOD_EN_REG(b, n) + 0x07)
+#define QPNP_WLED_BRIGHT_MSB_REG(b, n)         (QPNP_WLED_MOD_EN_REG(b, n) + 0x08)
+
+#define QPNP_WLED_MOD_FREQ_1200_KHZ            1200
+#define QPNP_WLED_MOD_FREQ_2400_KHZ            2400
+#define QPNP_WLED_MOD_FREQ_9600_KHZ            9600
+#define QPNP_WLED_MOD_FREQ_19200_KHZ           19200
+#define QPNP_WLED_MOD_FREQ_MASK                0x3F
+#define QPNP_WLED_MOD_FREQ_SHIFT               6
+#define QPNP_WLED_PHASE_STAG_MASK              0xDF
+#define QPNP_WLED_PHASE_STAG_SHIFT             5
+#define QPNP_WLED_DIM_RES_MASK                 0xFD
+#define QPNP_WLED_DIM_RES_SHIFT                1
+#define QPNP_WLED_DIM_HYB_MASK                 0xFB
+#define QPNP_WLED_DIM_HYB_SHIFT                2
+#define QPNP_WLED_DIM_ANA_MASK                 0xFE
+#define QPNP_WLED_HYB_THRES_MASK               0xF8
+#define QPNP_WLED_HYB_THRES_MIN                78
+#define QPNP_WLED_DEF_HYB_THRES                625
+#define QPNP_WLED_HYB_THRES_MAX                10000
+#define QPNP_WLED_MOD_EN_MASK                  0x7F
+#define QPNP_WLED_MOD_EN_SHFT                  7
+#define QPNP_WLED_MOD_EN                       1
+#define QPNP_WLED_SYNC_DLY_MASK                0xF8
+#define QPNP_WLED_SYNC_DLY_MIN_US              0
+#define QPNP_WLED_SYNC_DLY_MAX_US              1400
+#define QPNP_WLED_SYNC_DLY_STEP_US             200
+#define QPNP_WLED_DEF_SYNC_DLY_US              400
+#define QPNP_WLED_FS_CURR_MASK                 0xF0
+#define QPNP_WLED_FS_CURR_MIN_UA               0
+#define QPNP_WLED_FS_CURR_MAX_UA               30000
+#define QPNP_WLED_FS_CURR_STEP_UA              2500
+#define QPNP_WLED_CABC_MASK                    0x7F
+#define QPNP_WLED_CABC_SHIFT                   7
+#define QPNP_WLED_CURR_SINK_SHIFT              4
+#define QPNP_WLED_BRIGHT_LSB_MASK              0xFF
+#define QPNP_WLED_BRIGHT_MSB_SHIFT             8
+#define QPNP_WLED_BRIGHT_MSB_MASK              0x0F
+#define QPNP_WLED_SYNC                         0x0F
+#define QPNP_WLED_SYNC_RESET                   0x00
+
+#define QPNP_WLED_SWITCH_FREQ_800_KHZ_CODE     0x0B
+#define QPNP_WLED_SWITCH_FREQ_1600_KHZ_CODE    0x05
+
+#define QPNP_WLED_DISP_SEL_REG(b)              (b + 0x44)
+#define QPNP_WLED_MODULE_RDY_REG(b)            (b + 0x45)
+#define QPNP_WLED_MODULE_EN_REG(b)             (b + 0x46)
+#define QPNP_WLED_MODULE_RDY_MASK              0x7F
+#define QPNP_WLED_MODULE_RDY_SHIFT             7
+#define QPNP_WLED_MODULE_EN_MASK               0x7F
+#define QPNP_WLED_MODULE_EN_SHIFT              7
+#define QPNP_WLED_DISP_SEL_MASK                0x7F
+#define QPNP_WLED_DISP_SEL_SHIFT               7
+
+#define QPNP_WLED_IBB_BIAS_REG(b)              (b + 0x58)
+#define QPNP_WLED_IBB_BIAS_MASK                0x7F
+#define QPNP_WLED_IBB_BIAS_SHIFT               7
+#define QPNP_WLED_IBB_PWRUP_DLY_MASK           0xCF
+#define QPNP_WLED_IBB_PWRUP_DLY_SHIFT          4
+#define QPNP_WLED_IBB_PWRUP_DLY_MIN_MS         1
+#define QPNP_WLED_IBB_PWRUP_DLY_MAX_MS         8
+
+#define QPNP_WLED_LAB_IBB_RDY_REG(b)           (b + 0x49)
+#define QPNP_WLED_LAB_FAST_PC_REG(b)           (b + 0x5E)
+#define QPNP_WLED_LAB_FAST_PC_MASK             0xFB
+#define QPNP_WLED_LAB_START_DLY_US             8
+#define QPNP_WLED_LAB_FAST_PC_SHIFT            2
+
+#define QPNP_WLED_SEC_ACCESS_REG(b)            (b + 0xD0)
+#define QPNP_WLED_SEC_UNLOCK                   0xA5
+
+#define QPNP_WLED_MAX_STRINGS                  4
+#define WLED_MAX_LEVEL_511                     511
+#define WLED_MAX_LEVEL_4095                    4095
+#define QPNP_WLED_RAMP_DLY_MS                  20
+#define QPNP_WLED_TRIGGER_NONE                 "none"
+#define QPNP_WLED_STR_SIZE                     20
+#define QPNP_WLED_MIN_MSLEEP                   20
+#define QPNP_WLED_MAX_BR_LEVEL                 1638
+
+/* output feedback mode */
+enum qpnp_wled_fdbk_op {
+       QPNP_WLED_FDBK_AUTO,
+       QPNP_WLED_FDBK_WLED1,
+       QPNP_WLED_FDBK_WLED2,
+       QPNP_WLED_FDBK_WLED3,
+       QPNP_WLED_FDBK_WLED4,
+};
+
+/* dimming modes */
+enum qpnp_wled_dim_mode {
+       QPNP_WLED_DIM_ANALOG,
+       QPNP_WLED_DIM_DIGITAL,
+       QPNP_WLED_DIM_HYBRID,
+};
+
+/* dimming curve shapes */
+enum qpnp_wled_dim_shape {
+       QPNP_WLED_DIM_SHAPE_LOG,
+       QPNP_WLED_DIM_SHAPE_LINEAR,
+       QPNP_WLED_DIM_SHAPE_SQUARE,
+};
+
+
+/**
+ *  qpnp_wled - wed data structure
+ *  @ fdbk_op - output feedback mode
+ *  @ dim_mode - dimming mode
+ *  @ dim_shape - dimming curve shape
+ *  @ ctrl_base - base address for wled ctrl
+ *  @ sink_base - base address for wled sink
+ *  @ ibb_base - base address for IBB(Inverting Buck Boost)
+ *  @ lab_base - base address for LAB(LCD/AMOLED Boost)
+ *  @ mod_freq_khz - modulator frequency in KHZ
+ *  @ hyb_thres - threshold for hybrid dimming
+ *  @ sync_dly_us - sync delay in us
+ *  @ vref_mv - ref voltage in mv
+ *  @ switch_freq_khz - switching frequency in KHZ
+ *  @ ovp_mv - over voltage protection in mv
+ *  @ ilim_ma - current limiter in ma
+ *  @ boost_duty_ns - boost duty cycle in ns
+ *  @ fs_curr_ua - full scale current in ua
+ *  @ ramp_ms - delay between ramp steps in ms
+ *  @ ramp_step - ramp step size
+ *  @ strings - supported list of strings
+ *  @ num_strings - number of strings
+ *  @ en_9b_dim_res - enable or disable 9bit dimming
+ *  @ en_phase_stag - enable or disable phase staggering
+ *  @ en_cabc - enable or disable cabc
+ *  @ disp_type_amoled - type of display: LCD/AMOLED
+ *  @ ibb_bias_active - activate display bias
+ *  @ lab_fast_precharge - fast/slow precharge
+ */
+struct qpnp_wled {
+	enum qpnp_wled_fdbk_op fdbk_op;
+	enum qpnp_wled_dim_mode dim_mode;
+	enum qpnp_wled_dim_shape dim_shape;
+	uint16_t ctrl_base;
+	uint16_t sink_base;
+	uint16_t ibb_base;
+	uint16_t lab_base;
+	uint16_t mod_freq_khz;
+	uint16_t hyb_thres;
+	uint16_t sync_dly_us;
+	uint16_t vref_mv;
+	uint16_t switch_freq_khz;
+	uint16_t ovp_mv;
+	uint16_t ilim_ma;
+	uint16_t boost_duty_ns;
+	uint16_t fs_curr_ua;
+	uint16_t ibb_pwrup_dly_ms;
+	uint16_t ramp_ms;
+	uint16_t ramp_step;
+	uint8_t strings[QPNP_WLED_MAX_STRINGS];
+	uint8_t num_strings;
+	bool en_9b_dim_res;
+	bool en_phase_stag;
+	bool en_cabc;
+	bool disp_type_amoled;
+	bool ibb_bias_active;
+	bool lab_fast_precharge;
+};
+
+/* WLED Initial Setup */
+int qpnp_wled_init();
+
+/* Enable IBB */
+int qpnp_ibb_enable();
+void qpnp_wled_enable_backlight(enable);
diff --git a/dev/qpnp_wled/qpnp_wled.c b/dev/qpnp_wled/qpnp_wled.c
new file mode 100644
index 0000000..a342197
--- /dev/null
+++ b/dev/qpnp_wled/qpnp_wled.c
@@ -0,0 +1,537 @@
+ /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+ *   * Neither the name of The Linux Foundation, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <err.h>
+#include <qpnp_wled.h>
+
+static int fls(uint16_t n)
+{
+	int i = 0;
+	for (; n; n >>= 1, i++);
+	  return i;
+}
+
+static struct qpnp_wled *gwled;
+
+static int qpnp_wled_sec_access(struct qpnp_wled *wled, uint16_t base_addr)
+{
+	int rc;
+	uint8_t reg = QPNP_WLED_SEC_UNLOCK;
+
+	pm8x41_wled_reg_write(QPNP_WLED_SEC_ACCESS_REG(base_addr), reg);
+
+	return 0;
+}
+
+/* set wled to a level of brightness */
+static int qpnp_wled_set_level(struct qpnp_wled *wled, int level)
+{
+	int i, rc;
+	uint8_t reg;
+
+	/* set brightness registers */
+	for (i = 0; i < wled->num_strings; i++) {
+		reg = level & QPNP_WLED_BRIGHT_LSB_MASK;
+		pm8x41_wled_reg_write(QPNP_WLED_BRIGHT_LSB_REG(wled->sink_base,
+						wled->strings[i]), reg);
+
+		reg = level >> QPNP_WLED_BRIGHT_MSB_SHIFT;
+		reg = reg & QPNP_WLED_BRIGHT_MSB_MASK;
+		pm8x41_wled_reg_write(QPNP_WLED_BRIGHT_MSB_REG(wled->sink_base,
+						wled->strings[i]), reg);
+	}
+
+	/* sync */
+	reg = QPNP_WLED_SYNC;
+	pm8x41_wled_reg_write(QPNP_WLED_SYNC_REG(wled->sink_base), reg);
+
+	reg = QPNP_WLED_SYNC_RESET;
+	pm8x41_wled_reg_write(QPNP_WLED_SYNC_REG(wled->sink_base), reg);
+
+	return 0;
+}
+
+static int qpnp_wled_enable(struct qpnp_wled *wled,
+				uint16_t base_addr, bool state)
+{
+	uint8_t reg;
+
+	reg = pm8x41_wled_reg_read(
+			QPNP_WLED_MODULE_EN_REG(base_addr));
+	if (reg < 0)
+		return reg;
+	reg &= QPNP_WLED_MODULE_EN_MASK;
+	reg |= (state << QPNP_WLED_MODULE_EN_SHIFT);
+	pm8x41_wled_reg_write(QPNP_WLED_MODULE_EN_REG(base_addr), reg);
+
+	return 0;
+}
+
+int qpnp_ibb_enable(bool state)
+{
+	int rc = 0;
+	uint8_t reg;
+
+	if (!gwled) {
+		dprintf(CRITICAL, "%s: wled is not initialized yet\n", __func__);
+		return ERROR;
+	}
+
+	/* enable lab */
+	if (gwled->ibb_bias_active) {
+		rc = qpnp_wled_enable(gwled, gwled->lab_base, state);
+		if (rc < 0)
+			return rc;
+			udelay(QPNP_WLED_LAB_START_DLY_US + 1);
+	} else {
+		reg = pm8x41_wled_reg_read(QPNP_WLED_LAB_IBB_RDY_REG(gwled->lab_base));
+		if (reg < 0)
+			return reg;
+
+		reg &= QPNP_WLED_MODULE_EN_MASK;
+		reg |= (state << QPNP_WLED_MODULE_EN_SHIFT);
+		pm8x41_wled_reg_write(QPNP_WLED_LAB_IBB_RDY_REG(gwled->lab_base), reg);
+	}
+
+	rc = qpnp_wled_enable(gwled, gwled->ibb_base, state);
+
+	return rc;
+}
+
+/* enable / disable wled brightness */
+void qpnp_wled_enable_backlight(int enable)
+{
+	int level, rc;
+
+	if (!gwled) {
+		dprintf(CRITICAL, "%s: wled is not initialized yet\n", __func__);
+		return ERROR;
+	}
+
+	if (enable) {
+		rc = qpnp_wled_set_level(gwled, QPNP_WLED_MAX_BR_LEVEL);
+		if (rc) {
+			dprintf(CRITICAL,"wled set level failed\n");
+			return;
+		}
+	}
+	rc = qpnp_wled_enable(gwled, gwled->ctrl_base, enable);
+
+	if (rc) {
+		dprintf(CRITICAL,"wled %sable failed\n",
+					enable ? "en" : "dis");
+		return;
+	}
+
+}
+
+static int qpnp_wled_set_display_type(struct qpnp_wled *wled, uint16_t base_addr)
+{
+	int rc;
+	uint8_t reg = 0;
+
+	/* display type */
+	reg = pm8x41_wled_reg_read(QPNP_WLED_DISP_SEL_REG(base_addr));
+	if (reg < 0)
+		return reg;
+
+	reg &= QPNP_WLED_DISP_SEL_MASK;
+	reg |= (wled->disp_type_amoled << QPNP_WLED_DISP_SEL_SHIFT);
+	pm8x41_wled_reg_write(QPNP_WLED_DISP_SEL_REG(base_addr), reg);
+
+	return 0;
+}
+
+static int qpnp_wled_module_ready(struct qpnp_wled *wled, uint16_t base_addr, bool state)
+{
+	int rc;
+	uint8_t reg;
+
+	reg = pm8x41_wled_reg_read(
+			QPNP_WLED_MODULE_RDY_REG(base_addr));
+	if (reg < 0)
+		return reg;
+	reg &= QPNP_WLED_MODULE_RDY_MASK;
+	reg |= (state << QPNP_WLED_MODULE_RDY_SHIFT);
+	pm8x41_wled_reg_write(QPNP_WLED_MODULE_RDY_REG(base_addr), reg);
+
+	return 0;
+}
+
+/* Configure WLED registers */
+static int qpnp_wled_config(struct qpnp_wled *wled)
+{
+	int rc, i, temp;
+	uint8_t reg = 0;
+
+	/* Configure display type */
+	rc = qpnp_wled_set_display_type(wled, wled->ctrl_base);
+	if (rc < 0)
+		return rc;
+
+	/* Configure the FEEDBACK OUTPUT register */
+	reg = pm8x41_wled_reg_read(
+			QPNP_WLED_FDBK_OP_REG(wled->ctrl_base));
+	if (reg < 0)
+		return reg;
+	reg &= QPNP_WLED_FDBK_OP_MASK;
+	reg |= wled->fdbk_op;
+	pm8x41_wled_reg_write(QPNP_WLED_FDBK_OP_REG(wled->ctrl_base), reg);
+
+	/* Configure the VREF register */
+	if (wled->vref_mv < QPNP_WLED_VREF_MIN_MV)
+		wled->vref_mv = QPNP_WLED_VREF_MIN_MV;
+	else if (wled->vref_mv > QPNP_WLED_VREF_MAX_MV)
+		wled->vref_mv = QPNP_WLED_VREF_MAX_MV;
+
+	reg = pm8x41_wled_reg_read(
+			QPNP_WLED_VREF_REG(wled->ctrl_base));
+	if (reg < 0)
+		return reg;
+	reg &= QPNP_WLED_VREF_MASK;
+	temp = wled->vref_mv - QPNP_WLED_VREF_MIN_MV;
+	reg |= (temp / QPNP_WLED_VREF_STEP_MV);
+	pm8x41_wled_reg_write(QPNP_WLED_VREF_REG(wled->ctrl_base), reg);
+
+	/* Configure the ILIM register */
+	if (wled->ilim_ma < QPNP_WLED_ILIM_MIN_MA)
+		wled->ilim_ma = QPNP_WLED_ILIM_MIN_MA;
+	else if (wled->ilim_ma > QPNP_WLED_ILIM_MAX_MA)
+		wled->ilim_ma = QPNP_WLED_ILIM_MAX_MA;
+
+	reg = pm8x41_wled_reg_read(
+			QPNP_WLED_ILIM_REG(wled->ctrl_base));
+	if (reg < 0)
+		return reg;
+	reg &= QPNP_WLED_ILIM_MASK;
+	reg |= (wled->ilim_ma / QPNP_WLED_ILIM_STEP_MA);
+	pm8x41_wled_reg_write(QPNP_WLED_ILIM_REG(wled->ctrl_base), reg);
+
+	/* Configure the MAX BOOST DUTY register */
+	if (wled->boost_duty_ns < QPNP_WLED_BOOST_DUTY_MIN_NS)
+		wled->boost_duty_ns = QPNP_WLED_BOOST_DUTY_MIN_NS;
+	else if (wled->boost_duty_ns > QPNP_WLED_BOOST_DUTY_MAX_NS)
+		wled->boost_duty_ns = QPNP_WLED_BOOST_DUTY_MAX_NS;
+
+	reg = pm8x41_wled_reg_read(
+			QPNP_WLED_BOOST_DUTY_REG(wled->ctrl_base));
+	if (reg < 0)
+		return reg;
+	reg &= QPNP_WLED_BOOST_DUTY_MASK;
+	reg |= (wled->boost_duty_ns / QPNP_WLED_BOOST_DUTY_STEP_NS);
+	pm8x41_wled_reg_write(QPNP_WLED_BOOST_DUTY_REG(wled->ctrl_base), reg);
+
+	/* Configure the SWITCHING FREQ register */
+	if (wled->switch_freq_khz == QPNP_WLED_SWITCH_FREQ_1600_KHZ)
+		temp = QPNP_WLED_SWITCH_FREQ_1600_KHZ_CODE;
+	else
+		temp = QPNP_WLED_SWITCH_FREQ_800_KHZ_CODE;
+
+	reg = pm8x41_wled_reg_read(
+			QPNP_WLED_SWITCH_FREQ_REG(wled->ctrl_base));
+	if (reg < 0)
+		return reg;
+	reg &= QPNP_WLED_SWITCH_FREQ_MASK;
+	reg |= temp;
+	pm8x41_wled_reg_write(QPNP_WLED_SWITCH_FREQ_REG(wled->ctrl_base), reg);
+
+	/* Configure the OVP register */
+	if (wled->ovp_mv <= QPNP_WLED_OVP_17800_MV) {
+		wled->ovp_mv = QPNP_WLED_OVP_17800_MV;
+		temp = 3;
+	} else if (wled->ovp_mv <= QPNP_WLED_OVP_19400_MV) {
+		wled->ovp_mv = QPNP_WLED_OVP_19400_MV;
+		temp = 2;
+	} else if (wled->ovp_mv <= QPNP_WLED_OVP_29500_MV) {
+		wled->ovp_mv = QPNP_WLED_OVP_29500_MV;
+		temp = 1;
+	} else {
+		wled->ovp_mv = QPNP_WLED_OVP_31000_MV;
+		temp = 0;
+	}
+
+	reg = pm8x41_wled_reg_read(
+			QPNP_WLED_OVP_REG(wled->ctrl_base));
+	if (reg < 0)
+		return reg;
+	reg &= QPNP_WLED_OVP_MASK;
+	reg |= temp;
+	pm8x41_wled_reg_write(QPNP_WLED_OVP_REG(wled->ctrl_base), reg);
+
+	/* Configure the MODULATION register */
+	if (wled->mod_freq_khz <= QPNP_WLED_MOD_FREQ_1200_KHZ) {
+		wled->mod_freq_khz = QPNP_WLED_MOD_FREQ_1200_KHZ;
+		temp = 3;
+	} else if (wled->mod_freq_khz <= QPNP_WLED_MOD_FREQ_2400_KHZ) {
+		wled->mod_freq_khz = QPNP_WLED_MOD_FREQ_2400_KHZ;
+		temp = 2;
+	} else if (wled->mod_freq_khz <= QPNP_WLED_MOD_FREQ_9600_KHZ) {
+		wled->mod_freq_khz = QPNP_WLED_MOD_FREQ_9600_KHZ;
+		temp = 1;
+	} else {
+		wled->mod_freq_khz = QPNP_WLED_MOD_FREQ_19200_KHZ;
+		temp = 0;
+	}
+	reg = pm8x41_wled_reg_read(QPNP_WLED_MOD_REG(wled->sink_base));
+	if (reg < 0)
+		return reg;
+
+	reg &= QPNP_WLED_MOD_FREQ_MASK;
+	reg |= (temp << QPNP_WLED_MOD_FREQ_SHIFT);
+
+	reg &= QPNP_WLED_PHASE_STAG_MASK;
+	reg |= (wled->en_phase_stag << QPNP_WLED_PHASE_STAG_SHIFT);
+
+	reg &= QPNP_WLED_DIM_RES_MASK;
+	reg |= (wled->en_9b_dim_res << QPNP_WLED_DIM_RES_SHIFT);
+
+	if (wled->dim_mode == QPNP_WLED_DIM_HYBRID) {
+		reg &= QPNP_WLED_DIM_HYB_MASK;
+		reg |= (1 << QPNP_WLED_DIM_HYB_SHIFT);
+	} else {
+		reg &= QPNP_WLED_DIM_HYB_MASK;
+		reg |= (0 << QPNP_WLED_DIM_HYB_SHIFT);
+		reg &= QPNP_WLED_DIM_ANA_MASK;
+		reg |= wled->dim_mode;
+	}
+
+	pm8x41_wled_reg_write(QPNP_WLED_MOD_REG(wled->sink_base), reg);
+
+	/* Configure the HYBRID THRESHOLD register */
+	if (wled->hyb_thres < QPNP_WLED_HYB_THRES_MIN)
+		wled->hyb_thres = QPNP_WLED_HYB_THRES_MIN;
+	else if (wled->hyb_thres > QPNP_WLED_HYB_THRES_MAX)
+		wled->hyb_thres = QPNP_WLED_HYB_THRES_MAX;
+
+	reg = pm8x41_wled_reg_read(
+			QPNP_WLED_HYB_THRES_REG(wled->sink_base));
+	if (reg < 0)
+		return reg;
+
+	reg &= QPNP_WLED_HYB_THRES_MASK;
+	temp = fls(wled->hyb_thres / QPNP_WLED_HYB_THRES_MIN) - 1;
+	reg |= temp;
+	pm8x41_wled_reg_write(QPNP_WLED_HYB_THRES_REG(wled->sink_base), reg);
+
+	for (i = 0; i < wled->num_strings; i++) {
+		if (wled->strings[i] >= QPNP_WLED_MAX_STRINGS) {
+			dprintf(CRITICAL,"Invalid string number\n");
+			return ERR_NOT_VALID;
+		}
+
+		/* MODULATOR */
+		reg = pm8x41_wled_reg_read(
+				QPNP_WLED_MOD_EN_REG(wled->sink_base,
+						wled->strings[i]));
+		if (reg < 0)
+			return reg;
+		reg &= QPNP_WLED_MOD_EN_MASK;
+		reg |= (QPNP_WLED_MOD_EN << QPNP_WLED_MOD_EN_SHFT);
+		pm8x41_wled_reg_write(QPNP_WLED_MOD_EN_REG(wled->sink_base,
+						wled->strings[i]), reg);
+
+		/* SYNC DELAY */
+		if (wled->sync_dly_us < QPNP_WLED_SYNC_DLY_MIN_US)
+			wled->sync_dly_us = QPNP_WLED_SYNC_DLY_MIN_US;
+		else if (wled->sync_dly_us > QPNP_WLED_SYNC_DLY_MAX_US)
+			wled->sync_dly_us = QPNP_WLED_SYNC_DLY_MAX_US;
+
+		reg = pm8x41_wled_reg_read(
+				QPNP_WLED_SYNC_DLY_REG(wled->sink_base,
+						wled->strings[i]));
+		if (reg < 0)
+			return reg;
+		reg &= QPNP_WLED_SYNC_DLY_MASK;
+		temp = wled->sync_dly_us / QPNP_WLED_SYNC_DLY_STEP_US;
+		reg |= temp;
+		pm8x41_wled_reg_write(QPNP_WLED_SYNC_DLY_REG(wled->sink_base,
+						wled->strings[i]), reg);
+
+		/* FULL SCALE CURRENT */
+		if (wled->fs_curr_ua < QPNP_WLED_FS_CURR_MIN_UA)
+			wled->fs_curr_ua = QPNP_WLED_FS_CURR_MIN_UA;
+		else if (wled->fs_curr_ua > QPNP_WLED_FS_CURR_MAX_UA)
+			wled->fs_curr_ua = QPNP_WLED_FS_CURR_MAX_UA;
+
+		reg = pm8x41_wled_reg_read(
+				QPNP_WLED_FS_CURR_REG(wled->sink_base,
+						wled->strings[i]));
+		if (reg < 0)
+			return reg;
+		reg &= QPNP_WLED_FS_CURR_MASK;
+		temp = wled->fs_curr_ua / QPNP_WLED_FS_CURR_STEP_UA;
+		reg |= temp;
+		pm8x41_wled_reg_write(QPNP_WLED_FS_CURR_REG(wled->sink_base,
+						wled->strings[i]), reg);
+
+		/* CABC */
+		reg = pm8x41_wled_reg_read(
+				QPNP_WLED_CABC_REG(wled->sink_base,
+						wled->strings[i]));
+		if (reg < 0)
+			return reg;
+		reg &= QPNP_WLED_CABC_MASK;
+		reg |= (wled->en_cabc << QPNP_WLED_CABC_SHIFT);
+		pm8x41_wled_reg_write(QPNP_WLED_CABC_REG(wled->sink_base,
+						wled->strings[i]), reg);
+
+		/* Enable CURRENT SINK */
+		reg = pm8x41_wled_reg_read(
+				QPNP_WLED_CURR_SINK_REG(wled->sink_base));
+		if (reg < 0)
+			return reg;
+		temp = wled->strings[i] + QPNP_WLED_CURR_SINK_SHIFT;
+		reg |= (1 << temp);
+		pm8x41_wled_reg_write(QPNP_WLED_CURR_SINK_REG(wled->sink_base), reg);
+	}
+
+	/* LAB fast precharge */
+	reg = pm8x41_wled_reg_read(
+			QPNP_WLED_LAB_FAST_PC_REG(wled->lab_base));
+	if (reg < 0)
+		return reg;
+	reg &= QPNP_WLED_LAB_FAST_PC_MASK;
+	reg |= (wled->lab_fast_precharge << QPNP_WLED_LAB_FAST_PC_SHIFT);
+	pm8x41_wled_reg_write(QPNP_WLED_LAB_FAST_PC_REG(wled->lab_base), reg);
+
+	/* Configure lab display type */
+	rc = qpnp_wled_set_display_type(wled, wled->lab_base);
+	if (rc < 0)
+		return rc;
+
+	/* make LAB module ready */
+	rc = qpnp_wled_module_ready(wled, wled->lab_base, true);
+	if (rc < 0)
+		return rc;
+
+	/* IBB active bias */
+	if (wled->ibb_pwrup_dly_ms < QPNP_WLED_IBB_PWRUP_DLY_MIN_MS)
+		wled->ibb_pwrup_dly_ms = QPNP_WLED_IBB_PWRUP_DLY_MIN_MS;
+	else if (wled->ibb_pwrup_dly_ms > QPNP_WLED_IBB_PWRUP_DLY_MAX_MS)
+		wled->ibb_pwrup_dly_ms = QPNP_WLED_IBB_PWRUP_DLY_MAX_MS;
+
+	reg = pm8x41_wled_reg_read(
+			QPNP_WLED_IBB_BIAS_REG(wled->ibb_base));
+	if (reg < 0)
+		return reg;
+
+	reg &= QPNP_WLED_IBB_BIAS_MASK;
+	reg |= (!wled->ibb_bias_active << QPNP_WLED_IBB_BIAS_SHIFT);
+
+	temp = fls(wled->ibb_pwrup_dly_ms) - 1;
+	reg &= QPNP_WLED_IBB_PWRUP_DLY_MASK;
+	reg |= (temp << QPNP_WLED_IBB_PWRUP_DLY_SHIFT);
+
+	rc = qpnp_wled_sec_access(wled, wled->ibb_base);
+	if (rc)
+		return rc;
+
+	pm8x41_wled_reg_write(QPNP_WLED_IBB_BIAS_REG(wled->ibb_base), reg);
+
+	/* Configure ibb display type */
+	rc = qpnp_wled_set_display_type(wled, wled->ibb_base);
+	if (rc < 0)
+		return rc;
+
+	/* make IBB module ready */
+	rc = qpnp_wled_module_ready(wled, wled->ibb_base, true);
+	if (rc < 0)
+		return rc;
+
+	return 0;
+}
+
+/* Setup wled default parameters */
+static int qpnp_wled_setup(struct qpnp_wled *wled)
+{
+	int rc, i;
+
+	wled->sink_base = QPNP_WLED_SINK_BASE;
+	wled->ctrl_base = QPNP_WLED_CTRL_BASE;
+	wled->ibb_base = QPNP_WLED_IBB_BASE;
+	wled->lab_base = QPNP_WLED_LAB_BASE;
+	wled->fdbk_op = QPNP_WLED_FDBK_AUTO;
+	wled->vref_mv = QPNP_WLED_DFLT_VREF_MV;
+	wled->switch_freq_khz = QPNP_WLED_SWITCH_FREQ_800_KHZ;
+	wled->ovp_mv = QPNP_WLED_OVP_29500_MV;
+	wled->ilim_ma = QPNP_WLED_DFLT_ILIM_MA;
+	wled->boost_duty_ns = QPNP_WLED_BOOST_DUTY_MIN_NS;
+	wled->mod_freq_khz = QPNP_WLED_MOD_FREQ_19200_KHZ;
+	wled->dim_mode = QPNP_WLED_DIM_HYBRID;
+	wled->dim_shape = QPNP_WLED_DIM_SHAPE_LINEAR;
+
+	if (wled->dim_mode == QPNP_WLED_DIM_HYBRID) {
+		wled->hyb_thres = QPNP_WLED_DFLT_HYB_THRES;
+	}
+
+	wled->sync_dly_us = 800;
+	wled->fs_curr_ua = 16000;
+	wled->en_9b_dim_res = 0;
+	wled->en_phase_stag = true;
+	wled->en_cabc = 0;
+
+	wled->num_strings = QPNP_WLED_MAX_STRINGS;
+		for (i = 0; i < wled->num_strings; i++)
+			wled->strings[i] = i;
+
+	wled->ibb_bias_active = false;
+	wled->ibb_pwrup_dly_ms = 8;
+	wled->lab_fast_precharge = false;
+	wled->disp_type_amoled = false;
+
+	return 0;
+}
+
+int qpnp_wled_init()
+{
+	int rc, i;
+	struct qpnp_wled *wled;
+
+	wled = malloc(sizeof(struct qpnp_wled));
+	if (!wled)
+		return ERR_NO_MEMORY;
+
+	memset(wled, 0, sizeof(struct qpnp_wled));
+
+	rc = qpnp_wled_setup(wled);
+	if (rc) {
+		dprintf(CRITICAL, "Setting WLED parameters failed\n");
+		return rc;
+	}
+
+	rc = qpnp_wled_config(wled);
+	if (rc) {
+		dprintf(CRITICAL, "wled config failed\n");
+		return rc;
+	}
+
+	gwled = wled;
+
+	return rc;
+}
diff --git a/dev/qpnp_wled/rules.mk b/dev/qpnp_wled/rules.mk
new file mode 100644
index 0000000..d60c07f
--- /dev/null
+++ b/dev/qpnp_wled/rules.mk
@@ -0,0 +1,6 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+INCLUDES += -I$(LOCAL_DIR)/include
+
+OBJS += \
+	$(LOCAL_DIR)/qpnp_wled.o
diff --git a/include/debug.h b/include/debug.h
index ae7119e..bcf73c5 100644
--- a/include/debug.h
+++ b/include/debug.h
@@ -74,12 +74,7 @@
 /*
 * Initialize the stack protector canary value.
 */
-static inline void __stack_chk_guard_setup()
-{
-	void *canary;
-	canary = get_canary();
-	__stack_chk_guard =  canary;
-}
+#define __stack_chk_guard_setup() do { __stack_chk_guard = get_canary(); } while(0)
 
 void __attribute__ ((noreturn))
 	__stack_chk_fail (void);
diff --git a/include/target.h b/include/target.h
index c7c05db..ba95cbb 100644
--- a/include/target.h
+++ b/include/target.h
@@ -59,6 +59,7 @@
 void target_load_ssd_keystore(void);
 bool target_is_ssd_enabled(void);
 void *target_mmc_device();
+uint32_t is_user_force_reset(void);
 
 bool target_display_panel_node(char *panel_name, char *pbuf,
 	uint16_t buf_size);
diff --git a/lib/heap/heap.c b/lib/heap/heap.c
index a3a35fb..3393081 100644
--- a/lib/heap/heap.c
+++ b/lib/heap/heap.c
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2008-2009 Travis Geiselbrecht
  * Copyright (c) 2009 Corey Tabaka
+ * Copyright (c) 2009,2014 The Linux Foundation. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining
  * a copy of this software and associated documentation files
@@ -237,6 +238,11 @@
 	if (alignment & (alignment - 1))
 		return NULL;
 
+	if(size > (size + sizeof(struct alloc_struct_begin)))
+	{
+		dprintf(CRITICAL, "invalid input size\n");
+		return NULL;
+	}
 	// we always put a size field + base pointer + magic in front of the allocation
 	size += sizeof(struct alloc_struct_begin);
 #if DEBUG_HEAP
@@ -258,6 +264,11 @@
 			alignment = 16;
 
 		// add alignment for worst case fit
+		if(size > (size + alignment))
+		{
+			dprintf(CRITICAL, "invalid input alignment\n");
+			return NULL;
+		}
 		size += alignment;
 	}
 
diff --git a/lib/libfdt/fdt_rw.c b/lib/libfdt/fdt_rw.c
index 9ed0d4d..a3f8fad 100644
--- a/lib/libfdt/fdt_rw.c
+++ b/lib/libfdt/fdt_rw.c
@@ -316,6 +316,36 @@
 	return 0;
 }
 
+int fdt_appendprop_str(void *fdt, int nodeoffset, const char *name,
+		   const void *val, int len)
+{
+	struct fdt_property *prop;
+	int err, oldlen, newlen;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen);
+	if (prop) {
+		newlen = len + oldlen;
+		err = _fdt_splice_struct(fdt, prop->data,
+					 FDT_TAGALIGN(oldlen),
+					 FDT_TAGALIGN(newlen));
+		if (err)
+			return err;
+		prop->len = cpu_to_fdt32(newlen);
+
+		/* Add space to separate the appended strings */
+		prop->data[oldlen-1] = 0x20;
+		memcpy(prop->data + oldlen, val, len);
+	} else {
+		err = _fdt_add_property(fdt, nodeoffset, name, len, &prop);
+		if (err)
+			return err;
+		memcpy(prop->data, val, len);
+	}
+	return 0;
+}
+
 int fdt_delprop(void *fdt, int nodeoffset, const char *name)
 {
 	struct fdt_property *prop;
diff --git a/lib/libfdt/libfdt.h b/lib/libfdt/libfdt.h
index 73f4975..667964c 100644
--- a/lib/libfdt/libfdt.h
+++ b/lib/libfdt/libfdt.h
@@ -1264,6 +1264,35 @@
  */
 int fdt_appendprop(void *fdt, int nodeoffset, const char *name,
 		   const void *val, int len);
+/**
+ * fdt_appendprop_str - append a string value to a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to append to
+ * @val: pointer to data to append to the property value
+ * @len: length of the data to append to the property value
+ *
+ * fdt_appendprop_str() appends the string value to the named property
+ * in the given node, creating the property if it does not already exist.
+ *
+ * This function may insert data into the blob along with a space between
+ * the the two strings and will therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_appendprop_str(void *fdt, int nodeoffset, const char *name,
+		   const void *val, int len);
 
 /**
  * fdt_appendprop_u32 - append a 32-bit integer value to a property
@@ -1374,7 +1403,7 @@
  *	-FDT_ERR_TRUNCATED, standard meanings
  */
 #define fdt_appendprop_string(fdt, nodeoffset, name, str) \
-	fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)
+	fdt_appendprop_str((fdt), (nodeoffset), (name), (str), strlen(str)+1)
 
 /**
  * fdt_delprop - delete a property
diff --git a/makefile b/makefile
index 40cb9f0..0cf7e7c 100644
--- a/makefile
+++ b/makefile
@@ -63,6 +63,7 @@
 # setup toolchain prefix
 TOOLCHAIN_PREFIX ?= arm-eabi-
 CFLAGS += -fstack-protector-all
+CFLAGS += -fno-strict-overflow
 CPPFLAGS := -fno-exceptions -fno-rtti -fno-threadsafe-statics
 #CPPFLAGS += -Weffc++
 ASMFLAGS := -DASSEMBLY
diff --git a/platform/ferrum/acpuclock.c b/platform/ferrum/acpuclock.c
new file mode 100644
index 0000000..334a1f3
--- /dev/null
+++ b/platform/ferrum/acpuclock.c
@@ -0,0 +1,93 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <err.h>
+#include <assert.h>
+#include <debug.h>
+#include <reg.h>
+#include <platform/timer.h>
+#include <platform/iomap.h>
+#include <mmc.h>
+#include <clock.h>
+#include <platform/clock.h>
+#include <blsp_qup.h>
+
+void hsusb_clock_init(void)
+{
+
+}
+
+void clock_init_mmc(uint32_t interface)
+{
+
+}
+
+/* Configure MMC clock */
+void clock_config_mmc(uint32_t interface, uint32_t freq)
+{
+
+}
+
+/* Configure UART clock based on the UART block id*/
+void clock_config_uart_dm(uint8_t id)
+{
+
+}
+
+/* Function to asynchronously reset CE.
+ * Function assumes that all the CE clocks are off.
+ */
+static void ce_async_reset(uint8_t instance)
+{
+
+}
+
+void clock_ce_enable(uint8_t instance)
+{
+
+}
+
+void clock_ce_disable(uint8_t instance)
+{
+
+}
+
+void clock_config_ce(uint8_t instance)
+{
+	/* Need to enable the clock before disabling since the clk_disable()
+	 * has a check to default to nop when the clk_enable() is not called
+	 * on that particular clock.
+	 */
+	clock_ce_enable(instance);
+
+	clock_ce_disable(instance);
+
+	ce_async_reset(instance);
+
+	clock_ce_enable(instance);
+}
diff --git a/platform/ferrum/ferrum-clock.c b/platform/ferrum/ferrum-clock.c
new file mode 100644
index 0000000..7ae8a5f
--- /dev/null
+++ b/platform/ferrum/ferrum-clock.c
@@ -0,0 +1,543 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <reg.h>
+#include <err.h>
+#include <clock.h>
+#include <clock_pll.h>
+#include <clock_lib2.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+
+
+/* Mux source select values */
+#define cxo_source_val    0
+#define gpll0_source_val  1
+#define cxo_mm_source_val 0
+#define gpll0_mm_source_val 1
+struct clk_freq_tbl rcg_dummy_freq = F_END;
+
+
+/* Clock Operations */
+static struct clk_ops clk_ops_branch =
+{
+	.enable     = clock_lib2_branch_clk_enable,
+	.disable    = clock_lib2_branch_clk_disable,
+	.set_rate   = clock_lib2_branch_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg_mnd =
+{
+	.enable     = clock_lib2_rcg_enable,
+	.set_rate   = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg =
+{
+	.enable     = clock_lib2_rcg_enable,
+	.set_rate   = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_cxo =
+{
+	.enable     = cxo_clk_enable,
+	.disable    = cxo_clk_disable,
+};
+
+static struct clk_ops clk_ops_pll_vote =
+{
+	.enable     = pll_vote_clk_enable,
+	.disable    = pll_vote_clk_disable,
+	.auto_off   = pll_vote_clk_disable,
+	.is_enabled = pll_vote_clk_is_enabled,
+};
+
+static struct clk_ops clk_ops_vote =
+{
+	.enable     = clock_lib2_vote_clk_enable,
+	.disable    = clock_lib2_vote_clk_disable,
+};
+
+/* Clock Sources */
+static struct fixed_clk cxo_clk_src =
+{
+	.c = {
+		.rate     = 19200000,
+		.dbg_name = "cxo_clk_src",
+		.ops      = &clk_ops_cxo,
+	},
+};
+
+static struct pll_vote_clk gpll0_clk_src =
+{
+	.en_reg       = (void *) APCS_GPLL_ENA_VOTE,
+	.en_mask      = BIT(0),
+	.status_reg   = (void *) GPLL0_STATUS,
+	.status_mask  = BIT(17),
+	.parent       = &cxo_clk_src.c,
+
+	.c = {
+		.rate     = 800000000,
+		.dbg_name = "gpll0_clk_src",
+		.ops      = &clk_ops_pll_vote,
+	},
+};
+
+/* SDCC Clocks */
+static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] =
+{
+	F(   144000,    cxo,  16,   3,  25),
+	F(   400000,    cxo,  12,   1,   4),
+	F( 20000000,  gpll0,  10,   1,   4),
+	F( 25000000,  gpll0,  16,   1,   2),
+	F( 50000000,  gpll0,  16,   0,   0),
+	F(100000000,  gpll0,   8,   0,   0),
+	F(177770000,  gpll0, 4.5,   0,   0),
+	F(200000000,  gpll0,   4,   0,   0),
+	F_END
+};
+
+static struct rcg_clk sdcc1_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) SDCC1_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) SDCC1_CFG_RCGR,
+	.m_reg        = (uint32_t *) SDCC1_M,
+	.n_reg        = (uint32_t *) SDCC1_N,
+	.d_reg        = (uint32_t *) SDCC1_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_sdcc1_2_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "sdc1_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+/* BLSP1_QUP2 Clocks */
+static struct clk_freq_tbl ftbl_gcc_blsp1_qup2_i2c_apps_clk_src[] =
+{
+	F(      96000,    cxo,  10,   1,  2),
+	F(    4800000,    cxo,   4,   0,  0),
+	F(    9600000,    cxo,   2,   0,  0),
+	F(   16000000,  gpll0,  10,   1,  5),
+	F(   19200000,  gpll0,   1,   0,  0),
+	F(   25000000,  gpll0,  16,   1,  2),
+	F(   50000000,  gpll0,  16,   0,  0),
+	F_END
+};
+
+static struct branch_clk gcc_sdcc1_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) SDCC1_APPS_CBCR,
+	.parent       = &sdcc1_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_sdcc1_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk gcc_sdcc1_ahb_clk =
+{
+	.cbcr_reg     = (uint32_t *) SDCC1_AHB_CBCR,
+	.has_sibling  = 1,
+
+	.c = {
+		.dbg_name = "gcc_sdcc1_ahb_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct rcg_clk sdcc2_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) SDCC2_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) SDCC2_CFG_RCGR,
+	.m_reg        = (uint32_t *) SDCC2_M,
+	.n_reg        = (uint32_t *) SDCC2_N,
+	.d_reg        = (uint32_t *) SDCC2_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_sdcc1_2_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "sdc2_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_sdcc2_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) SDCC2_APPS_CBCR,
+	.parent       = &sdcc2_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_sdcc2_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk gcc_sdcc2_ahb_clk =
+{
+	.cbcr_reg     = (uint32_t *) SDCC2_AHB_CBCR,
+	.has_sibling  = 1,
+
+	.c = {
+		.dbg_name = "gcc_sdcc2_ahb_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+/* UART Clocks */
+static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] =
+{
+	F( 3686400,  gpll0,    1,  72,  15625),
+	F( 7372800,  gpll0,    1, 144,  15625),
+	F(14745600,  gpll0,    1, 288,  15625),
+	F(16000000,  gpll0,   10,   1,      5),
+	F(19200000,    cxo,    1,   0,      0),
+	F(24000000,  gpll0,    1,   3,    100),
+	F(25000000,  gpll0,   16,   1,      2),
+	F(32000000,  gpll0,    1,   1,     25),
+	F(40000000,  gpll0,    1,   1,     20),
+	F(46400000,  gpll0,    1,  29,    500),
+	F(48000000,  gpll0,    1,   3,     50),
+	F(51200000,  gpll0,    1,   8,    125),
+	F(56000000,  gpll0,    1,   7,    100),
+	F(58982400,  gpll0,    1,1152,  15625),
+	F(60000000,  gpll0,    1,   3,     40),
+	F_END
+};
+
+static struct rcg_clk blsp1_uart2_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR,
+	.m_reg        = (uint32_t *) BLSP1_UART2_APPS_M,
+	.n_reg        = (uint32_t *) BLSP1_UART2_APPS_N,
+	.d_reg        = (uint32_t *) BLSP1_UART2_APPS_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "blsp1_uart2_apps_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_blsp1_uart2_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) BLSP1_UART2_APPS_CBCR,
+	.parent       = &blsp1_uart2_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp1_uart2_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct vote_clk gcc_blsp1_ahb_clk = {
+	.cbcr_reg     = (uint32_t *) BLSP1_AHB_CBCR,
+	.vote_reg     = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+	.en_mask      = BIT(10),
+
+	.c = {
+		.dbg_name = "gcc_blsp1_ahb_clk",
+		.ops      = &clk_ops_vote,
+	},
+};
+
+/* USB Clocks */
+static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] =
+{
+	F(80000000,  gpll0,   10,   0,   0),
+	F_END
+};
+
+static struct rcg_clk usb_hs_system_clk_src =
+{
+	.cmd_reg      = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR,
+
+	.set_rate     = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl     = ftbl_gcc_usb_hs_system_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "usb_hs_system_clk",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct branch_clk gcc_usb_hs_system_clk =
+{
+	.cbcr_reg     = (uint32_t *) USB_HS_SYSTEM_CBCR,
+	.parent       = &usb_hs_system_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_usb_hs_system_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk gcc_usb_hs_ahb_clk =
+{
+	.cbcr_reg     = (uint32_t *) USB_HS_AHB_CBCR,
+	.has_sibling  = 1,
+
+	.c = {
+		.dbg_name = "gcc_usb_hs_ahb_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+/* Display clocks */
+static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = {
+	F_MM(19200000,    cxo,   1,   0,   0),
+	F_END
+};
+
+static struct clk_freq_tbl ftbl_mdp_clk[] = {
+	F_MM( 80000000,  gpll0,   10,    0,    0),
+	F_MM( 100000000, gpll0,   8,    0,    0),
+	F_MM( 200000000, gpll0,   4,    0,    0),
+	F_MM( 320000000, gpll0,   2.5,    0,    0),
+	F_END
+};
+
+static struct rcg_clk dsi_esc0_clk_src = {
+	.cmd_reg  = (uint32_t *) DSI_ESC0_CMD_RCGR,
+	.cfg_reg  = (uint32_t *) DSI_ESC0_CFG_RCGR,
+	.set_rate = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl = ftbl_mdss_esc0_1_clk,
+
+	.c        = {
+		.dbg_name = "dsi_esc0_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = {
+	F_MM(19200000,    cxo,   1,   0,   0),
+	F_END
+};
+
+static struct rcg_clk vsync_clk_src = {
+	.cmd_reg  = (uint32_t *) VSYNC_CMD_RCGR,
+	.cfg_reg  = (uint32_t *) VSYNC_CFG_RCGR,
+	.set_rate = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl = ftbl_mdss_vsync_clk,
+
+	.c        = {
+		.dbg_name = "vsync_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct branch_clk mdss_esc0_clk = {
+	.cbcr_reg    = (uint32_t *) DSI_ESC0_CBCR,
+	.parent      = &dsi_esc0_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mdss_esc0_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mdss_axi_clk = {
+	.cbcr_reg    = (uint32_t *) MDP_AXI_CBCR,
+	.has_sibling = 1,
+
+	.c           = {
+		.dbg_name = "mdss_axi_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mdp_ahb_clk = {
+	.cbcr_reg    = (uint32_t *) MDP_AHB_CBCR,
+	.has_sibling = 1,
+
+	.c           = {
+		.dbg_name = "mdp_ahb_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct rcg_clk mdss_mdp_clk_src = {
+	.cmd_reg      = (uint32_t *) MDP_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) MDP_CFG_RCGR,
+	.set_rate     = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl     = ftbl_mdp_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c            = {
+		.dbg_name = "mdss_mdp_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct branch_clk mdss_mdp_clk = {
+	.cbcr_reg    = (uint32_t *) MDP_CBCR,
+	.parent      = &mdss_mdp_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mdss_mdp_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mdss_vsync_clk = {
+	.cbcr_reg    = MDSS_VSYNC_CBCR,
+	.parent      = &vsync_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mdss_vsync_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
+	F(160000000,  gpll0,   5,   0,   0),
+	F_END
+};
+
+static struct rcg_clk ce1_clk_src = {
+	.cmd_reg      = (uint32_t *) GCC_CRYPTO_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) GCC_CRYPTO_CFG_RCGR,
+	.set_rate     = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl     = ftbl_gcc_ce1_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "ce1_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct vote_clk gcc_ce1_clk = {
+	.cbcr_reg      = (uint32_t *) GCC_CRYPTO_CBCR,
+	.vote_reg      = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+	.en_mask       = BIT(2),
+
+	.c = {
+		.dbg_name  = "gcc_ce1_clk",
+		.ops       = &clk_ops_vote,
+	},
+};
+
+static struct vote_clk gcc_ce1_ahb_clk = {
+	.cbcr_reg     = (uint32_t *) GCC_CRYPTO_AHB_CBCR,
+	.vote_reg     = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+	.en_mask      = BIT(0),
+
+	.c = {
+		.dbg_name = "gcc_ce1_ahb_clk",
+		.ops      = &clk_ops_vote,
+	},
+};
+
+static struct vote_clk gcc_ce1_axi_clk = {
+	.cbcr_reg     = (uint32_t *) GCC_CRYPTO_AXI_CBCR,
+	.vote_reg     = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+	.en_mask      = BIT(1),
+
+	.c = {
+		.dbg_name = "gcc_ce1_axi_clk",
+		.ops      = &clk_ops_vote,
+	},
+};
+
+
+static struct rcg_clk gcc_blsp1_qup2_i2c_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) GCC_BLSP1_QUP2_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) GCC_BLSP1_QUP2_CFG_RCGR,
+	.set_rate     = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl     = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "gcc_blsp1_qup2_i2c_apps_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
+	.cbcr_reg = GCC_BLSP1_QUP2_APPS_CBCR,
+	.parent   = &gcc_blsp1_qup2_i2c_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp1_qup2_i2c_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+/* Clock lookup table */
+static struct clk_lookup msm_clocks_ferrum[] =
+{
+	CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
+	CLK_LOOKUP("sdc1_core_clk",  gcc_sdcc1_apps_clk.c),
+
+	CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c),
+	CLK_LOOKUP("sdc2_core_clk",  gcc_sdcc2_apps_clk.c),
+
+	CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
+	CLK_LOOKUP("uart2_core_clk",  gcc_blsp1_uart2_apps_clk.c),
+
+	CLK_LOOKUP("usb_iface_clk",  gcc_usb_hs_ahb_clk.c),
+	CLK_LOOKUP("usb_core_clk",   gcc_usb_hs_system_clk.c),
+
+	CLK_LOOKUP("mdp_ahb_clk",          mdp_ahb_clk.c),
+	CLK_LOOKUP("mdss_esc0_clk",        mdss_esc0_clk.c),
+	CLK_LOOKUP("mdss_axi_clk",         mdss_axi_clk.c),
+	CLK_LOOKUP("mdss_vsync_clk",       mdss_vsync_clk.c),
+	CLK_LOOKUP("mdss_mdp_clk_src",     mdss_mdp_clk_src.c),
+	CLK_LOOKUP("mdss_mdp_clk",         mdss_mdp_clk.c),
+
+	CLK_LOOKUP("ce1_ahb_clk",  gcc_ce1_ahb_clk.c),
+	CLK_LOOKUP("ce1_axi_clk",  gcc_ce1_axi_clk.c),
+	CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c),
+	CLK_LOOKUP("ce1_src_clk",  ce1_clk_src.c),
+
+	CLK_LOOKUP("blsp1_qup2_ahb_iface_clk", gcc_blsp1_ahb_clk.c),
+	CLK_LOOKUP("gcc_blsp1_qup2_i2c_apps_clk_src", gcc_blsp1_qup2_i2c_apps_clk_src.c),
+	CLK_LOOKUP("gcc_blsp1_qup2_i2c_apps_clk", gcc_blsp1_qup2_i2c_apps_clk.c),
+};
+
+void platform_clock_init(void)
+{
+	clk_init(msm_clocks_ferrum, ARRAY_SIZE(msm_clocks_ferrum));
+}
diff --git a/platform/ferrum/gpio.c b/platform/ferrum/gpio.c
new file mode 100644
index 0000000..5a9889c
--- /dev/null
+++ b/platform/ferrum/gpio.c
@@ -0,0 +1,64 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <platform/gpio.h>
+#include <blsp_qup.h>
+
+void gpio_tlmm_config(uint32_t gpio, uint8_t func,
+			uint8_t dir, uint8_t pull,
+			uint8_t drvstr, uint32_t enable)
+{
+	uint32_t val = 0;
+	val |= pull;
+	val |= func << 2;
+	val |= drvstr << 6;
+	val |= enable << 9;
+	writel(val, (uint32_t *)GPIO_CONFIG_ADDR(gpio));
+	return;
+}
+
+void gpio_set(uint32_t gpio, uint32_t dir)
+{
+	writel(dir, (uint32_t *)GPIO_IN_OUT_ADDR(gpio));
+	return;
+}
+
+/* Configure gpio for blsp uart 2 */
+void gpio_config_uart_dm(uint8_t id)
+{
+	/* configure rx gpio */
+	gpio_tlmm_config(5, 2, GPIO_INPUT, GPIO_NO_PULL,
+				GPIO_8MA, GPIO_DISABLE);
+
+	/* configure tx gpio */
+	gpio_tlmm_config(4, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+				GPIO_8MA, GPIO_DISABLE);
+}
diff --git a/platform/ferrum/include/platform/clock.h b/platform/ferrum/include/platform/clock.h
new file mode 100644
index 0000000..ab23e03
--- /dev/null
+++ b/platform/ferrum/include/platform/clock.h
@@ -0,0 +1,44 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FERRUM_CLOCK_H
+#define __FERRUM_CLOCK_H
+
+#include <clock.h>
+#include <clock_lib2.h>
+
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
+
+void platform_clock_init(void);
+
+void clock_init_mmc(uint32_t interface);
+void clock_config_mmc(uint32_t interface, uint32_t freq);
+void clock_config_uart_dm(uint8_t id);
+void hsusb_clock_init(void);
+void clock_config_ce(uint8_t instance);
+#endif
diff --git a/platform/ferrum/include/platform/gpio.h b/platform/ferrum/include/platform/gpio.h
new file mode 100644
index 0000000..0114b3e
--- /dev/null
+++ b/platform/ferrum/include/platform/gpio.h
@@ -0,0 +1,59 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_FERRUM_GPIO_H
+#define __PLATFORM_FERRUM_GPIO_H
+
+
+/* GPIO TLMM: Direction */
+#define GPIO_INPUT      0
+#define GPIO_OUTPUT     1
+
+/* GPIO TLMM: Pullup/Pulldown */
+#define GPIO_NO_PULL    0
+#define GPIO_PULL_DOWN  1
+#define GPIO_KEEPER     2
+#define GPIO_PULL_UP    3
+
+/* GPIO TLMM: Drive Strength */
+#define GPIO_2MA        0
+#define GPIO_4MA        1
+#define GPIO_6MA        2
+#define GPIO_8MA        3
+#define GPIO_10MA       4
+#define GPIO_12MA       5
+#define GPIO_14MA       6
+#define GPIO_16MA       7
+
+/* GPIO TLMM: Status */
+#define GPIO_ENABLE     0
+#define GPIO_DISABLE    1
+
+
+void gpio_config_uart_dm(uint8_t id);
+#endif
diff --git a/platform/ferrum/include/platform/iomap.h b/platform/ferrum/include/platform/iomap.h
new file mode 100644
index 0000000..5ac39ac
--- /dev/null
+++ b/platform/ferrum/include/platform/iomap.h
@@ -0,0 +1,117 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PLATFORM_FERRUM_IOMAP_H_
+#define _PLATFORM_FERRUM_IOMAP_H_
+
+#define MSM_IOMAP_BASE              0x00000000
+#define MSM_IOMAP_END               0x08000000
+
+#define SDRAM_START_ADDR            0x80000000
+
+#define MSM_SHARED_BASE             0x86300000
+
+#define APPS_SS_BASE                0x0B000000
+
+#define MSM_GIC_DIST_BASE           APPS_SS_BASE
+#define MSM_GIC_CPU_BASE            (APPS_SS_BASE + 0x2000)
+#define APPS_APCS_QTMR_AC_BASE      (APPS_SS_BASE + 0x00020000)
+#define APPS_APCS_F0_QTMR_V1_BASE   (APPS_SS_BASE + 0x00021000)
+#define QTMR_BASE                   APPS_APCS_F0_QTMR_V1_BASE
+
+#define PERIPH_SS_BASE              0x07800000
+
+#define MSM_SDC1_BASE               (PERIPH_SS_BASE + 0x00024000)
+#define MSM_SDC1_SDHCI_BASE         (PERIPH_SS_BASE + 0x00024900)
+#define MSM_SDC2_BASE               (PERIPH_SS_BASE + 0x00064000)
+#define MSM_SDC2_SDHCI_BASE         (PERIPH_SS_BASE + 0x00064900)
+
+/* SDHCI */
+#define SDCC_MCI_HC_MODE            (0x00000078)
+#define SDCC_HC_PWRCTL_STATUS_REG   (0x000000DC)
+#define SDCC_HC_PWRCTL_MASK_REG     (0x000000E0)
+#define SDCC_HC_PWRCTL_CLEAR_REG    (0x000000E4)
+#define SDCC_HC_PWRCTL_CTL_REG      (0x000000E8)
+
+#define BLSP1_UART0_BASE            (PERIPH_SS_BASE + 0x000AF000)
+#define BLSP1_UART1_BASE            (PERIPH_SS_BASE + 0x000B0000)
+#define MSM_USB_BASE                (PERIPH_SS_BASE + 0x000D9000)
+
+#define CLK_CTL_BASE                0x1800000
+
+#define SPMI_BASE                   0x02000000
+#define SPMI_GENI_BASE              (SPMI_BASE + 0xA000)
+#define SPMI_PIC_BASE               (SPMI_BASE +  0x01800000)
+
+#define TLMM_BASE_ADDR              0x1000000
+#define GPIO_CONFIG_ADDR(x)         (TLMM_BASE_ADDR + (x)*0x1000)
+#define GPIO_IN_OUT_ADDR(x)         (TLMM_BASE_ADDR + 0x00000004 + (x)*0x1000)
+
+#define MPM2_MPM_CTRL_BASE          0x004A0000
+#define MPM2_MPM_PS_HOLD            0x004AB000
+
+/* CRYPTO ENGINE */
+#define  MSM_CE1_BASE               0x073A000
+#define  MSM_CE1_BAM_BASE           0x0704000
+
+
+/* GPLL */
+#define GPLL0_STATUS                (CLK_CTL_BASE + 0x21024)
+#define APCS_GPLL_ENA_VOTE          (CLK_CTL_BASE + 0x45000)
+#define APCS_CLOCK_BRANCH_ENA_VOTE  (CLK_CTL_BASE + 0x45004)
+
+/* SDCC */
+#define SDC1_HDRV_PULL_CTL          (TLMM_BASE_ADDR + 0x10A000)
+#define SDCC1_BCR                   (CLK_CTL_BASE + 0x42000) /* block reset*/
+#define SDCC1_APPS_CBCR             (CLK_CTL_BASE + 0x42018) /* branch ontrol */
+#define SDCC1_AHB_CBCR              (CLK_CTL_BASE + 0x4201C)
+#define SDCC1_CMD_RCGR              (CLK_CTL_BASE + 0x42004) /* cmd */
+#define SDCC1_CFG_RCGR              (CLK_CTL_BASE + 0x42008) /* cfg */
+#define SDCC1_M                     (CLK_CTL_BASE + 0x4200C) /* m */
+#define SDCC1_N                     (CLK_CTL_BASE + 0x42010) /* n */
+#define SDCC1_D                     (CLK_CTL_BASE + 0x42014) /* d */
+
+
+/* UART */
+#define BLSP1_AHB_CBCR              (CLK_CTL_BASE + 0x1008)
+#define BLSP1_UART2_APPS_CBCR       (CLK_CTL_BASE + 0x302C)
+#define BLSP1_UART2_APPS_CMD_RCGR   (CLK_CTL_BASE + 0x3034)
+#define BLSP1_UART2_APPS_CFG_RCGR   (CLK_CTL_BASE + 0x3038)
+#define BLSP1_UART2_APPS_M          (CLK_CTL_BASE + 0x303C)
+#define BLSP1_UART2_APPS_N          (CLK_CTL_BASE + 0x3040)
+#define BLSP1_UART2_APPS_D          (CLK_CTL_BASE + 0x3044)
+
+
+/* USB */
+#define USB_HS_BCR                  (CLK_CTL_BASE + 0x41000)
+#define USB_HS_SYSTEM_CBCR          (CLK_CTL_BASE + 0x41004)
+#define USB_HS_AHB_CBCR             (CLK_CTL_BASE + 0x41008)
+#define USB_HS_SYSTEM_CMD_RCGR      (CLK_CTL_BASE + 0x41010)
+#define USB_HS_SYSTEM_CFG_RCGR      (CLK_CTL_BASE + 0x41014)
+
+#endif
diff --git a/platform/ferrum/include/platform/irqs.h b/platform/ferrum/include/platform/irqs.h
new file mode 100644
index 0000000..47e7f04
--- /dev/null
+++ b/platform/ferrum/include/platform/irqs.h
@@ -0,0 +1,66 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __IRQS_FERRUM_H
+#define __IRQS_FERRUM_H
+
+/* MSM ACPU Interrupt Numbers */
+
+/* 0-15:  STI/SGI (software triggered/generated interrupts)
+ * 16-31: PPI (private peripheral interrupts)
+ * 32+:   SPI (shared peripheral interrupts)
+ */
+int qtmr_irq();
+
+#define GIC_PPI_START                          16
+#define GIC_SPI_START                          32
+
+#define INT_QTMR_NON_SECURE_PHY_TIMER_EXP      (GIC_PPI_START + 3)
+#define INT_QTMR_VIRTUAL_TIMER_EXP             (GIC_PPI_START + 4)
+
+#define INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP      (GIC_SPI_START + 8)
+
+#define USB1_HS_BAM_IRQ                        (GIC_SPI_START + 135)
+#define USB1_HS_IRQ                            (GIC_SPI_START + 134)
+
+#define SDCC1_PWRCTL_IRQ                       (GIC_SPI_START + 138)
+#define SDCC2_PWRCTL_IRQ                       (GIC_SPI_START + 221)
+
+/* Retrofit universal macro names */
+#define INT_USB_HS                             USB1_HS_IRQ
+
+#define EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ         (GIC_SPI_START + 190)
+
+#define NR_MSM_IRQS                            256
+#define NR_GPIO_IRQS                           173
+#define NR_BOARD_IRQS                          0
+
+#define NR_IRQS                                (NR_MSM_IRQS + NR_GPIO_IRQS + \
+                                               NR_BOARD_IRQS)
+
+#endif /* __IRQS_FERRUM_H */
diff --git a/platform/ferrum/platform.c b/platform/ferrum/platform.c
new file mode 100644
index 0000000..1895fe6
--- /dev/null
+++ b/platform/ferrum/platform.c
@@ -0,0 +1,52 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <qgic.h>
+#include <qtimer.h>
+#include <mmu.h>
+#include <arch/arm/mmu.h>
+#include <smem.h>
+
+void platform_early_init(void)
+{
+	qgic_init();
+	qtimer_init();
+}
+
+void platform_init(void)
+{
+	dprintf(INFO, "platform_init()\n");
+}
+
+void platform_uninit(void)
+{
+	qtimer_uninit();
+}
diff --git a/platform/ferrum/rules.mk b/platform/ferrum/rules.mk
new file mode 100644
index 0000000..da6f955
--- /dev/null
+++ b/platform/ferrum/rules.mk
@@ -0,0 +1,25 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+ARCH    := arm
+#Compiling this as cortex-a8 until the compiler supports krait
+ARM_CPU := cortex-a8
+CPU     := generic
+
+DEFINES += ARM_CPU_CORE_A7
+
+MMC_SLOT         := 1
+
+DEFINES += PERIPH_BLK_BLSP=1
+DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
+           MMC_SLOT=$(MMC_SLOT)
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
+
+OBJS += \
+       $(LOCAL_DIR)/platform.o \
+       $(LOCAL_DIR)/acpuclock.o \
+       $(LOCAL_DIR)/gpio.o
+
+LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
+
+include platform/msm_shared/rules.mk
diff --git a/platform/fsm9010/acpuclock.c b/platform/fsm9010/acpuclock.c
new file mode 100644
index 0000000..a8a8f54
--- /dev/null
+++ b/platform/fsm9010/acpuclock.c
@@ -0,0 +1,345 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <err.h>
+#include <assert.h>
+#include <debug.h>
+#include <reg.h>
+#include <platform/timer.h>
+#include <platform/iomap.h>
+#include <mmc.h>
+#include <clock.h>
+#include <platform/clock.h>
+#include <blsp_qup.h>
+
+void hsusb_clock_init(void)
+{
+	int ret;
+	struct clk *iclk, *cclk;
+
+	ret = clk_get_set_enable("usb_iface_clk", 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	ret = clk_get_set_enable("usb_core_clk", 75000000, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	mdelay(20);
+
+	iclk = clk_get("usb_iface_clk");
+	cclk = clk_get("usb_core_clk");
+
+	clk_disable(iclk);
+	clk_disable(cclk);
+
+	mdelay(20);
+
+	/* Start the block reset for usb */
+	writel(1, USB_HS_BCR);
+
+	mdelay(20);
+
+	/* Take usb block out of reset */
+	writel(0, USB_HS_BCR);
+
+	mdelay(20);
+
+	ret = clk_enable(iclk);
+
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	ret = clk_enable(cclk);
+
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+}
+
+void clock_init_mmc(uint32_t interface)
+{
+	char clk_name[64];
+	int ret;
+
+	snprintf(clk_name, sizeof(clk_name), "sdc%u_iface_clk", interface);
+
+	/* enable interface clock */
+	ret = clk_get_set_enable(clk_name, 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set sdc1_iface_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+}
+
+/* Configure MMC clock */
+void clock_config_mmc(uint32_t interface, uint32_t freq)
+{
+	int ret;
+	char clk_name[64];
+
+	snprintf(clk_name, sizeof(clk_name), "sdc%u_core_clk", interface);
+
+	/* Disalbe MCI_CLK before changing the sdcc clock */
+#ifndef MMC_SDHCI_SUPPORT
+	mmc_boot_mci_clk_disable();
+#endif
+
+	if(freq == MMC_CLK_400KHZ)
+	{
+		ret = clk_get_set_enable(clk_name, 400000, 1);
+	}
+	else if(freq == MMC_CLK_20MHZ)
+	{
+		ret = clk_get_set_enable(clk_name, 20000000, 1);
+	}
+	else if(freq == MMC_CLK_25MHZ)
+	{
+		ret = clk_get_set_enable(clk_name, 25000000, 1);
+	}
+	else if(freq == MMC_CLK_50MHZ)
+	{
+		ret = clk_get_set_enable(clk_name, 50000000, 1);
+	}
+	else if(freq == MMC_CLK_96MHZ)
+	{
+		ret = clk_get_set_enable(clk_name, 100000000, 1);
+	}
+	else if(freq == MMC_CLK_200MHZ)
+	{
+		ret = clk_get_set_enable(clk_name, 200000000, 1);
+	}
+	else
+	{
+		dprintf(CRITICAL, "sdc frequency (%d) is not supported\n", freq);
+		ASSERT(0);
+	}
+
+
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set sdc1_core_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	/* Enalbe MCI clock */
+#ifndef MMC_SDHCI_SUPPORT
+	mmc_boot_mci_clk_enable();
+#endif
+}
+
+/* Configure UART clock based on the UART block id*/
+void clock_config_uart_dm(uint8_t id)
+{
+	int ret;
+	char str[256];
+
+	sprintf(str, "uart%d_iface_clk", id);
+	ret = clk_get_set_enable(str, 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set uart2_iface_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	sprintf(str, "uart%d_core_clk", id);
+	ret = clk_get_set_enable(str, 7372800, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set uart1_core_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+}
+
+/* Function to asynchronously reset CE.
+ * Function assumes that all the CE clocks are off.
+ */
+static void ce_async_reset(uint8_t instance)
+{
+	if (instance == 1)
+	{
+		/* TODO: Add support for instance 1. */
+		dprintf(CRITICAL, "CE instance not supported instance = %d", instance);
+		ASSERT(0);
+	}
+	else if (instance == 2)
+	{
+		/* Start the block reset for CE */
+		writel(1, GCC_CE2_BCR);
+
+		udelay(2);
+
+		/* Take CE block out of reset */
+		writel(0, GCC_CE2_BCR);
+
+		udelay(2);
+	}
+	else
+	{
+		dprintf(CRITICAL, "CE instance not supported instance = %d", instance);
+		ASSERT(0);
+	}
+}
+
+void clock_ce_enable(uint8_t instance)
+{
+	int ret;
+	char clk_name[64];
+
+	snprintf(clk_name, sizeof(clk_name), "ce%u_src_clk", instance);
+	ret = clk_get_set_enable(clk_name, 100000000, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set ce_src_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	snprintf(clk_name, sizeof(clk_name), "ce%u_core_clk", instance);
+	ret = clk_get_set_enable(clk_name, 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set ce_core_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	snprintf(clk_name, sizeof(clk_name), "ce%u_ahb_clk", instance);
+	ret = clk_get_set_enable(clk_name, 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set ce_ahb_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	snprintf(clk_name, sizeof(clk_name), "ce%u_axi_clk", instance);
+	ret = clk_get_set_enable(clk_name, 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set ce_axi_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	/* Wait for 48 * #pipes cycles.
+	 * This is necessary as immediately after an access control reset (boot up)
+	 * or a debug re-enable, the Crypto core sequentially clears its internal
+	 * pipe key storage memory. If pipe key initialization writes are attempted
+	 * during this time, they may be overwritten by the internal clearing logic.
+	 */
+	udelay(1);
+}
+
+void clock_ce_disable(uint8_t instance)
+{
+	struct clk *ahb_clk;
+	struct clk *cclk;
+	struct clk *axi_clk;
+	struct clk *src_clk;
+	char clk_name[64];
+
+	snprintf(clk_name, sizeof(clk_name), "ce%u_src_clk", instance);
+	src_clk = clk_get(clk_name);
+
+	snprintf(clk_name, sizeof(clk_name), "ce%u_ahb_clk", instance);
+	ahb_clk = clk_get(clk_name);
+
+	snprintf(clk_name, sizeof(clk_name), "ce%u_axi_clk", instance);
+	axi_clk = clk_get(clk_name);
+
+	snprintf(clk_name, sizeof(clk_name), "ce%u_core_clk", instance);
+	cclk    = clk_get(clk_name);
+
+	clk_disable(ahb_clk);
+	clk_disable(axi_clk);
+	clk_disable(cclk);
+	clk_disable(src_clk);
+
+	/* Some delay for the clocks to stabalize. */
+	udelay(1);
+}
+
+void clock_config_ce(uint8_t instance)
+{
+	/* Need to enable the clock before disabling since the clk_disable()
+	 * has a check to default to nop when the clk_enable() is not called
+	 * on that particular clock.
+	 */
+	clock_ce_enable(instance);
+
+	clock_ce_disable(instance);
+
+	ce_async_reset(instance);
+
+	clock_ce_enable(instance);
+
+}
+
+void clock_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id)
+{
+	uint8_t ret = 0;
+	char clk_name[64];
+
+	struct clk *qup_clk;
+
+	snprintf(clk_name, sizeof(clk_name), "blsp%u_ahb_clk", blsp_id);
+
+	ret = clk_get_set_enable(clk_name, 0 , 1);
+
+	if (ret) {
+		dprintf(CRITICAL, "Failed to enable %s clock\n", clk_name);
+		return;
+	}
+
+	snprintf(clk_name, sizeof(clk_name), "blsp%u_qup%u_i2c_apps_clk",
+		blsp_id, (qup_id + 1));
+
+	qup_clk = clk_get(clk_name);
+
+	if (!qup_clk) {
+		dprintf(CRITICAL, "Failed to get %s\n", clk_name);
+		return;
+	}
+
+	ret = clk_enable(qup_clk);
+
+	if (ret) {
+		dprintf(CRITICAL, "Failed to enable %s\n", clk_name);
+		return;
+	}
+}
diff --git a/platform/fsm9010/fsm9010-clock.c b/platform/fsm9010/fsm9010-clock.c
new file mode 100644
index 0000000..a3d03e4
--- /dev/null
+++ b/platform/fsm9010/fsm9010-clock.c
@@ -0,0 +1,499 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <reg.h>
+#include <err.h>
+#include <clock.h>
+#include <clock_pll.h>
+#include <clock_lib2.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+
+
+/* Mux source select values */
+#define cxo_source_val    0
+#define gpll0_source_val  1
+#define cxo_mm_source_val 0
+#define mmpll0_mm_source_val 1
+#define mmpll1_mm_source_val 2
+#define mmpll3_mm_source_val 3
+#define gpll0_mm_source_val 5
+
+struct clk_freq_tbl rcg_dummy_freq = F_END;
+
+
+/* Clock Operations */
+static struct clk_ops clk_ops_branch =
+{
+	.enable     = clock_lib2_branch_clk_enable,
+	.disable    = clock_lib2_branch_clk_disable,
+	.set_rate   = clock_lib2_branch_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg_mnd =
+{
+	.enable     = clock_lib2_rcg_enable,
+	.set_rate   = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg =
+{
+	.enable     = clock_lib2_rcg_enable,
+	.set_rate   = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_cxo =
+{
+	.enable     = cxo_clk_enable,
+	.disable    = cxo_clk_disable,
+};
+
+static struct clk_ops clk_ops_pll_vote =
+{
+	.enable     = pll_vote_clk_enable,
+	.disable    = pll_vote_clk_disable,
+	.auto_off   = pll_vote_clk_disable,
+	.is_enabled = pll_vote_clk_is_enabled,
+};
+
+static struct clk_ops clk_ops_vote =
+{
+	.enable     = clock_lib2_vote_clk_enable,
+	.disable    = clock_lib2_vote_clk_disable,
+};
+
+/* Clock Sources */
+static struct fixed_clk cxo_clk_src =
+{
+	.c = {
+		.rate     = 19200000,
+		.dbg_name = "cxo_clk_src",
+		.ops      = &clk_ops_cxo,
+	},
+};
+
+static struct pll_vote_clk gpll0_clk_src =
+{
+	.en_reg       = (void *) APCS_GPLL_ENA_VOTE,
+	.en_mask      = BIT(0),
+	.status_reg   = (void *) GPLL0_STATUS,
+	.status_mask  = BIT(17),
+	.parent       = &cxo_clk_src.c,
+
+	.c = {
+		.rate     = 600000000,
+		.dbg_name = "gpll0_clk_src",
+		.ops      = &clk_ops_pll_vote,
+	},
+};
+
+/* SDCC Clocks */
+static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] =
+{
+	F(   144000,    cxo,  16,   3,  25),
+	F(   400000,    cxo,  12,   1,   4),
+	F( 20000000,  gpll0,  15,   1,   2),
+	F( 25000000,  gpll0,  12,   1,   2),
+	F( 50000000,  gpll0,  12,   0,   0),
+	F(100000000,  gpll0,   6,   0,   0),
+	F(200000000,  gpll0,   3,   0,   0),
+	F_END
+};
+
+static struct rcg_clk sdcc1_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) SDCC1_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) SDCC1_CFG_RCGR,
+	.m_reg        = (uint32_t *) SDCC1_M,
+	.n_reg        = (uint32_t *) SDCC1_N,
+	.d_reg        = (uint32_t *) SDCC1_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_sdcc1_2_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "sdc1_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_sdcc1_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) SDCC1_APPS_CBCR,
+	.parent       = &sdcc1_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_sdcc1_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk gcc_sdcc1_ahb_clk =
+{
+	.cbcr_reg     = (uint32_t *) SDCC1_AHB_CBCR,
+	.has_sibling  = 1,
+
+	.c = {
+		.dbg_name = "gcc_sdcc1_ahb_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+/* UART Clocks */
+static struct clk_freq_tbl ftbl_gcc_blsp1_uart1_4_apps_clk[] =
+{
+	F( 3686400,  gpll0,    1,  96,  15625),
+	F( 7372800,  gpll0,    1, 192,  15625),
+	F(14745600,  gpll0,    1, 384,  15625),
+	F(16000000,  gpll0,    5,   2,     15),
+	F(19200000,    cxo,    1,   0,      0),
+	F(24000000,  gpll0,    5,   1,      5),
+	F(32000000,  gpll0,    1,   4,     75),
+	F(40000000,  gpll0,   15,   0,      0),
+	F(46400000,  gpll0,    1,  29,    375),
+	F(48000000,  gpll0, 12.5,   0,      0),
+	F(51200000,  gpll0,    1,  32,    375),
+	F(56000000,  gpll0,    1,   7,     75),
+	F(58982400,  gpll0,    1, 1536, 15625),
+	F(60000000,  gpll0,   10,   0,      0),
+	F_END
+};
+
+static struct rcg_clk blsp1_uart0_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) BLSP1_UART0_APPS_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) BLSP1_UART0_APPS_CFG_RCGR,
+	.m_reg        = (uint32_t *) BLSP1_UART0_APPS_M,
+	.n_reg        = (uint32_t *) BLSP1_UART0_APPS_N,
+	.d_reg        = (uint32_t *) BLSP1_UART0_APPS_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_blsp1_uart1_4_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "blsp1_uart0_apps_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_blsp1_uart0_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) BLSP1_UART0_APPS_CBCR,
+	.parent       = &blsp1_uart0_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp1_uart0_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct rcg_clk blsp1_uart1_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) BLSP1_UART1_APPS_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) BLSP1_UART1_APPS_CFG_RCGR,
+	.m_reg        = (uint32_t *) BLSP1_UART1_APPS_M,
+	.n_reg        = (uint32_t *) BLSP1_UART1_APPS_N,
+	.d_reg        = (uint32_t *) BLSP1_UART1_APPS_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_blsp1_uart1_4_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "blsp1_uart1_apps_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_blsp1_uart1_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) BLSP1_UART1_APPS_CBCR,
+	.parent       = &blsp1_uart1_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp1_uart1_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct rcg_clk blsp1_uart2_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR,
+	.m_reg        = (uint32_t *) BLSP1_UART2_APPS_M,
+	.n_reg        = (uint32_t *) BLSP1_UART2_APPS_N,
+	.d_reg        = (uint32_t *) BLSP1_UART2_APPS_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_blsp1_uart1_4_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "blsp1_uart2_apps_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_blsp1_uart2_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) BLSP1_UART2_APPS_CBCR,
+	.parent       = &blsp1_uart2_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp1_uart2_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct rcg_clk blsp1_uart3_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) BLSP1_UART3_APPS_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) BLSP1_UART3_APPS_CFG_RCGR,
+	.m_reg        = (uint32_t *) BLSP1_UART3_APPS_M,
+	.n_reg        = (uint32_t *) BLSP1_UART3_APPS_N,
+	.d_reg        = (uint32_t *) BLSP1_UART3_APPS_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_blsp1_uart1_4_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "blsp1_uart3_apps_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_blsp1_uart3_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) BLSP1_UART3_APPS_CBCR,
+	.parent       = &blsp1_uart3_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp1_uart3_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct vote_clk gcc_blsp1_ahb_clk = {
+	.cbcr_reg     = (uint32_t *) BLSP1_AHB_CBCR,
+	.vote_reg     = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+	.en_mask      = BIT(17),
+
+	.c = {
+		.dbg_name = "gcc_blsp1_ahb_clk",
+		.ops      = &clk_ops_vote,
+	},
+};
+
+/* USB Clocks */
+static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] =
+{
+	F(75000000,  gpll0,   8,   0,   0),
+	F_END
+};
+
+static struct rcg_clk usb_hs_system_clk_src =
+{
+	.cmd_reg      = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR,
+
+	.set_rate     = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl     = ftbl_gcc_usb_hs_system_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "usb_hs_system_clk",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct branch_clk gcc_usb_hs_system_clk =
+{
+	.cbcr_reg     = (uint32_t *) USB_HS_SYSTEM_CBCR,
+	.parent       = &usb_hs_system_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_usb_hs_system_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk gcc_usb_hs_ahb_clk =
+{
+	.cbcr_reg     = (uint32_t *) USB_HS_AHB_CBCR,
+	.has_sibling  = 1,
+
+	.c = {
+		.dbg_name = "gcc_usb_hs_ahb_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+/* CE Clocks */
+static struct clk_freq_tbl ftbl_gcc_ce2_clk[] = {
+	F( 50000000,  gpll0,  12,   0,   0),
+	F(100000000,  gpll0,   6,   0,   0),
+	F_END
+};
+
+static struct rcg_clk ce2_clk_src = {
+	.cmd_reg      = (uint32_t *) GCC_CE2_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) GCC_CE2_CFG_RCGR,
+	.set_rate     = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl     = ftbl_gcc_ce2_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "ce2_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct vote_clk gcc_ce2_clk = {
+	.cbcr_reg = (uint32_t *) GCC_CE2_CBCR,
+	.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+	.en_mask = BIT(2),
+
+	.c = {
+		.dbg_name = "gcc_ce2_clk",
+		.ops = &clk_ops_vote,
+	},
+};
+
+static struct vote_clk gcc_ce2_ahb_clk = {
+	.cbcr_reg = (uint32_t *) GCC_CE2_AHB_CBCR,
+	.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+	.en_mask = BIT(0),
+
+	.c = {
+		.dbg_name = "gcc_ce2_ahb_clk",
+		.ops = &clk_ops_vote,
+	},
+};
+
+static struct vote_clk gcc_ce2_axi_clk = {
+	.cbcr_reg = (uint32_t *) GCC_CE2_AXI_CBCR,
+	.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+	.en_mask = BIT(1),
+
+	.c = {
+		.dbg_name = "gcc_ce2_axi_clk",
+		.ops = &clk_ops_vote,
+	},
+};
+
+static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
+	F( 50000000,  gpll0,  12,   0,   0),
+	F(100000000,  gpll0,   6,   0,   0),
+	F_END
+};
+
+static struct rcg_clk ce1_clk_src = {
+	.cmd_reg      = (uint32_t *) GCC_CE1_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) GCC_CE1_CFG_RCGR,
+	.set_rate     = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl     = ftbl_gcc_ce1_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "ce1_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct vote_clk gcc_ce1_clk = {
+	.cbcr_reg = (uint32_t *) GCC_CE1_CBCR,
+	.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+	.en_mask = BIT(5),
+
+	.c = {
+		.dbg_name = "gcc_ce1_clk",
+		.ops = &clk_ops_vote,
+	},
+};
+
+static struct vote_clk gcc_ce1_ahb_clk = {
+	.cbcr_reg = (uint32_t *) GCC_CE1_AHB_CBCR,
+	.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+	.en_mask = BIT(3),
+
+	.c = {
+		.dbg_name = "gcc_ce1_ahb_clk",
+		.ops = &clk_ops_vote,
+	},
+};
+
+static struct vote_clk gcc_ce1_axi_clk = {
+	.cbcr_reg = (uint32_t *) GCC_CE1_AXI_CBCR,
+	.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+	.en_mask = BIT(4),
+
+	.c = {
+		.dbg_name = "gcc_ce1_axi_clk",
+		.ops = &clk_ops_vote,
+	},
+};
+
+
+/* Clock lookup table */
+static struct clk_lookup msm_clocks_fsm9010[] =
+{
+	CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
+	CLK_LOOKUP("sdc1_core_clk",  gcc_sdcc1_apps_clk.c),
+
+	CLK_LOOKUP("uart0_iface_clk", gcc_blsp1_ahb_clk.c),
+	CLK_LOOKUP("uart0_core_clk",  gcc_blsp1_uart0_apps_clk.c),
+	CLK_LOOKUP("uart1_iface_clk", gcc_blsp1_ahb_clk.c),
+	CLK_LOOKUP("uart1_core_clk",  gcc_blsp1_uart1_apps_clk.c),
+	CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
+	CLK_LOOKUP("uart2_core_clk",  gcc_blsp1_uart2_apps_clk.c),
+	CLK_LOOKUP("uart3_iface_clk", gcc_blsp1_ahb_clk.c),
+	CLK_LOOKUP("uart3_core_clk",  gcc_blsp1_uart3_apps_clk.c),
+
+	CLK_LOOKUP("usb_iface_clk",  gcc_usb_hs_ahb_clk.c),
+	CLK_LOOKUP("usb_core_clk",   gcc_usb_hs_system_clk.c),
+
+	CLK_LOOKUP("ce2_ahb_clk",  gcc_ce2_ahb_clk.c),
+	CLK_LOOKUP("ce2_axi_clk",  gcc_ce2_axi_clk.c),
+	CLK_LOOKUP("ce2_core_clk", gcc_ce2_clk.c),
+	CLK_LOOKUP("ce2_src_clk",  ce2_clk_src.c),
+
+	CLK_LOOKUP("ce1_ahb_clk",  gcc_ce1_ahb_clk.c),
+	CLK_LOOKUP("ce1_axi_clk",  gcc_ce1_axi_clk.c),
+	CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c),
+	CLK_LOOKUP("ce1_src_clk",  ce1_clk_src.c),
+};
+
+
+void platform_clock_init(void)
+{
+	clk_init(msm_clocks_fsm9010, ARRAY_SIZE(msm_clocks_fsm9010));
+}
diff --git a/platform/fsm9010/gpio.c b/platform/fsm9010/gpio.c
new file mode 100644
index 0000000..e4d38c3
--- /dev/null
+++ b/platform/fsm9010/gpio.c
@@ -0,0 +1,81 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ *  * Neither the name of The Linux Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <platform/gpio.h>
+#include <gsbi.h>
+#include <blsp_qup.h>
+
+void gpio_tlmm_config(uint32_t gpio, uint8_t func,
+		      uint8_t dir, uint8_t pull,
+		      uint8_t drvstr, uint32_t enable)
+{
+	uint32_t val = 0;
+	val |= pull;
+	val |= func << 2;
+	val |= drvstr << 6;
+	val |= enable << 9;
+	writel(val, (unsigned int *)GPIO_CONFIG_ADDR(gpio));
+	return;
+}
+
+void gpio_set(uint32_t gpio, uint32_t dir)
+{
+	writel(dir, (unsigned int *)GPIO_IN_OUT_ADDR(gpio));
+	return;
+}
+
+void gpio_config_uart_dm(uint8_t id)
+{
+	static struct {
+		unsigned int gpio_tx;
+		unsigned int gpio_rx;
+	} gpio_table[] = {
+		{ 12, 13 },
+		{ 4, 5 },
+		{ 8, 6 },
+		{ 10, 11 },
+	};
+
+	if (id >= ARRAY_SIZE(gpio_table))
+		return;
+
+	/* configure rx gpio */
+	gpio_tlmm_config(gpio_table[id].gpio_rx, 2, GPIO_INPUT, GPIO_NO_PULL,
+				GPIO_8MA, GPIO_DISABLE);
+
+	/* configure tx gpio */
+	gpio_tlmm_config(gpio_table[id].gpio_tx, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+				GPIO_8MA, GPIO_DISABLE);
+}
+
+void gpio_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id)
+{
+}
diff --git a/platform/fsm9010/include/platform/clock.h b/platform/fsm9010/include/platform/clock.h
new file mode 100644
index 0000000..2690f53
--- /dev/null
+++ b/platform/fsm9010/include/platform/clock.h
@@ -0,0 +1,47 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSM9010_CLOCK_H
+#define __FSM9010_CLOCK_H
+
+#include <clock.h>
+#include <clock_lib2.h>
+
+#define UART_DM_CLK_RX_TX_BIT_RATE 0x99
+
+void platform_clock_init(void);
+
+void clock_init_mmc(uint32_t interface);
+void clock_config_mmc(uint32_t interface, uint32_t freq);
+void clock_config_uart_dm(uint8_t id);
+void hsusb_clock_init(void);
+void clock_config_ce(uint8_t instance);
+void clock_ce_enable(uint8_t instance);
+void clock_ce_disable(uint8_t instance);
+
+#endif
diff --git a/platform/fsm9010/include/platform/gpio.h b/platform/fsm9010/include/platform/gpio.h
new file mode 100644
index 0000000..ace30dd
--- /dev/null
+++ b/platform/fsm9010/include/platform/gpio.h
@@ -0,0 +1,60 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ *  * Neither the name of The Linux Foundation, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_FSM9010_GPIO_H
+#define __PLATFORM_FSM9010_GPIO_H
+
+#include <gpio.h>
+
+/* GPIO TLMM: Direction */
+#define GPIO_INPUT      0
+#define GPIO_OUTPUT     1
+
+/* GPIO TLMM: Pullup/Pulldown */
+#define GPIO_NO_PULL    0
+#define GPIO_PULL_DOWN  1
+#define GPIO_KEEPER     2
+#define GPIO_PULL_UP    3
+
+/* GPIO TLMM: Drive Strength */
+#define GPIO_2MA        0
+#define GPIO_4MA        1
+#define GPIO_6MA        2
+#define GPIO_8MA        3
+#define GPIO_10MA       4
+#define GPIO_12MA       5
+#define GPIO_14MA       6
+#define GPIO_16MA       7
+
+/* GPIO TLMM: Status */
+#define GPIO_ENABLE     0
+#define GPIO_DISABLE    1
+
+void gpio_config_uart_dm(uint8_t id);
+void gpio_config_blsp_i2c(uint8_t, uint8_t);
+#endif
diff --git a/platform/fsm9010/include/platform/iomap.h b/platform/fsm9010/include/platform/iomap.h
new file mode 100644
index 0000000..65f46fa
--- /dev/null
+++ b/platform/fsm9010/include/platform/iomap.h
@@ -0,0 +1,179 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PLATFORM_FSM9010_IOMAP_H_
+#define _PLATFORM_FSM9010_IOMAP_H_
+
+#define MSM_IOMAP_BASE              0xF9000000
+#define MSM_IOMAP_END               0xFEFFFFFF
+
+#define SDRAM_START_ADDR            0x00000000
+#define SDRAM_SEC_BANK_START_ADDR   0x10000000
+
+#define MSM_SHARED_BASE             0x0FA00000
+
+#define RPM_MSG_RAM_BASE            0xFC42B000
+#define SYSTEM_IMEM_BASE            0xFE800000
+#define MSM_SHARED_IMEM_BASE        0xFE805000
+
+#define RESTART_REASON_ADDR             (RPM_MSG_RAM_BASE     + 0x65C)
+#define RESTART_REASON_ADDR_V2          (MSM_SHARED_IMEM_BASE + 0x65C)
+#define DLOAD_MODE_ADDR_V2              (MSM_SHARED_IMEM_BASE + 0x0)
+#define EMERGENCY_DLOAD_MODE_ADDR_V2    (MSM_SHARED_IMEM_BASE + 0xFE0)
+
+#define APPS_SS_BASE                0xF9000000
+
+#define MSM_GIC_DIST_BASE           APPS_SS_BASE
+#define MSM_GIC_CPU_BASE            (APPS_SS_BASE + 0x2000)
+#define APPS_APCS_QTMR_AC_BASE      (APPS_SS_BASE + 0x00020000)
+#define APPS_APCS_F0_QTMR_V1_BASE   (APPS_SS_BASE + 0x00021000)
+#define QTMR_BASE                   APPS_APCS_F0_QTMR_V1_BASE
+#define PERIPH_SS_BASE              0xF9800000
+
+#define MSM_SDC1_BAM_BASE           (PERIPH_SS_BASE + 0x00004000)
+#define MSM_SDC1_BASE               (PERIPH_SS_BASE + 0x00024000)
+#define MSM_SDC1_DML_BASE           (PERIPH_SS_BASE + 0x00024800)
+#define MSM_SDC1_SDHCI_BASE         (PERIPH_SS_BASE + 0x00024900)
+
+/* BLSP1_UART[0:5] */
+#define BLSP1_UART0_BASE            (PERIPH_SS_BASE + 0x0011D000)
+#define BLSP1_UART1_BASE            (PERIPH_SS_BASE + 0x0011E000)
+#define BLSP1_UART2_BASE            (PERIPH_SS_BASE + 0x0011F000)
+#define BLSP1_UART3_BASE            (PERIPH_SS_BASE + 0x00120000)
+
+#define MSM_USB_BASE                (PERIPH_SS_BASE + 0x00200000)
+
+#define CLK_CTL_BASE                0xFC400000
+
+#define GCC_WDOG_DEBUG              (CLK_CTL_BASE +  0x00001780)
+
+#define USB_HS_BCR                  (CLK_CTL_BASE + 0x480)
+
+#define SPMI_BASE                   0xFC4C0000
+#define SPMI_GENI_BASE              (SPMI_BASE + 0xA000)
+#define SPMI_PIC_BASE               (SPMI_BASE + 0xB000)
+
+#define MSM_CE2_BAM_BASE            0xFD444000
+#define MSM_CE2_BASE                0xFD45A000
+
+#define TLMM_BASE_ADDR              0xFD510000
+#define GPIO_CONFIG_ADDR(x)         (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
+#define GPIO_IN_OUT_ADDR(x)         (TLMM_BASE_ADDR + 0x1004 + (x)*0x10)
+
+#define MPM2_MPM_CTRL_BASE                   0xFC4A1000
+#define MPM2_MPM_PS_HOLD                     0xFC4AB000
+#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL    0xFC4A3000
+
+/* CE 1 */
+#define  GCC_CE1_BCR                (CLK_CTL_BASE + 0x1040)
+#define  GCC_CE1_CMD_RCGR           (CLK_CTL_BASE + 0x1050)
+#define  GCC_CE1_CFG_RCGR           (CLK_CTL_BASE + 0x1054)
+#define  GCC_CE1_CBCR               (CLK_CTL_BASE + 0x1044)
+#define  GCC_CE1_AXI_CBCR           (CLK_CTL_BASE + 0x1048)
+#define  GCC_CE1_AHB_CBCR           (CLK_CTL_BASE + 0x104C)
+
+/* CE 2 */
+#define  GCC_CE2_BCR                (CLK_CTL_BASE + 0x1080)
+#define  GCC_CE2_CMD_RCGR           (CLK_CTL_BASE + 0x1090)
+#define  GCC_CE2_CFG_RCGR           (CLK_CTL_BASE + 0x1094)
+#define  GCC_CE2_CBCR               (CLK_CTL_BASE + 0x1084)
+#define  GCC_CE2_AXI_CBCR           (CLK_CTL_BASE + 0x1088)
+#define  GCC_CE2_AHB_CBCR           (CLK_CTL_BASE + 0x108C)
+
+/* GPLL */
+#define GPLL0_STATUS                (CLK_CTL_BASE + 0x001C)
+#define APCS_GPLL_ENA_VOTE          (CLK_CTL_BASE + 0x1480)
+#define APCS_CLOCK_BRANCH_ENA_VOTE  (CLK_CTL_BASE + 0x1484)
+
+/* SDCC 1 */
+#define SDCC1_BCR                   (CLK_CTL_BASE + 0x4C0) /* block reset */
+#define SDCC1_APPS_CBCR             (CLK_CTL_BASE + 0x4C4) /* branch control */
+#define SDCC1_AHB_CBCR              (CLK_CTL_BASE + 0x4C8)
+#define SDCC1_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x4CC)
+#define SDCC1_CMD_RCGR              (CLK_CTL_BASE + 0x4D0) /* cmd */
+#define SDCC1_CFG_RCGR              (CLK_CTL_BASE + 0x4D4) /* cfg */
+#define SDCC1_M                     (CLK_CTL_BASE + 0x4D8) /* m */
+#define SDCC1_N                     (CLK_CTL_BASE + 0x4DC) /* n */
+#define SDCC1_D                     (CLK_CTL_BASE + 0x4E0) /* d */
+
+/* UART
+   BLSP1_UART[0:3]
+*/
+#define BLSP1_AHB_CBCR              (CLK_CTL_BASE + 0x5C4)
+
+#define BLSP1_UART0_APPS_CBCR       (CLK_CTL_BASE + 0x684)
+#define BLSP1_UART0_APPS_CMD_RCGR   (CLK_CTL_BASE + 0x68C)
+#define BLSP1_UART0_APPS_CFG_RCGR   (CLK_CTL_BASE + 0x690)
+#define BLSP1_UART0_APPS_M          (CLK_CTL_BASE + 0x694)
+#define BLSP1_UART0_APPS_N          (CLK_CTL_BASE + 0x698)
+#define BLSP1_UART0_APPS_D          (CLK_CTL_BASE + 0x69C)
+
+#define BLSP1_UART1_APPS_CBCR       (CLK_CTL_BASE + 0x704)
+#define BLSP1_UART1_APPS_CMD_RCGR   (CLK_CTL_BASE + 0x70C)
+#define BLSP1_UART1_APPS_CFG_RCGR   (CLK_CTL_BASE + 0x710)
+#define BLSP1_UART1_APPS_M          (CLK_CTL_BASE + 0x714)
+#define BLSP1_UART1_APPS_N          (CLK_CTL_BASE + 0x718)
+#define BLSP1_UART1_APPS_D          (CLK_CTL_BASE + 0x71C)
+
+#define BLSP1_UART2_APPS_CBCR       (CLK_CTL_BASE + 0x784)
+#define BLSP1_UART2_APPS_CMD_RCGR   (CLK_CTL_BASE + 0x78C)
+#define BLSP1_UART2_APPS_CFG_RCGR   (CLK_CTL_BASE + 0x790)
+#define BLSP1_UART2_APPS_M          (CLK_CTL_BASE + 0x794)
+#define BLSP1_UART2_APPS_N          (CLK_CTL_BASE + 0x798)
+#define BLSP1_UART2_APPS_D          (CLK_CTL_BASE + 0x79C)
+
+#define BLSP1_UART3_APPS_CBCR       (CLK_CTL_BASE + 0x804)
+#define BLSP1_UART3_APPS_CMD_RCGR   (CLK_CTL_BASE + 0x80C)
+#define BLSP1_UART3_APPS_CFG_RCGR   (CLK_CTL_BASE + 0x810)
+#define BLSP1_UART3_APPS_M          (CLK_CTL_BASE + 0x814)
+#define BLSP1_UART3_APPS_N          (CLK_CTL_BASE + 0x818)
+#define BLSP1_UART3_APPS_D          (CLK_CTL_BASE + 0x81C)
+
+/* USB */
+#define USB_HS_SYSTEM_CBCR          (CLK_CTL_BASE + 0x484)
+#define USB_HS_AHB_CBCR             (CLK_CTL_BASE + 0x488)
+#define USB_HS_SYSTEM_CMD_RCGR      (CLK_CTL_BASE + 0x490)
+#define USB_HS_SYSTEM_CFG_RCGR      (CLK_CTL_BASE + 0x494)
+
+/* I2C */
+#define BLSP_QUP_BASE(blsp_id, qup_id)   ((blsp_id == 1) ? \
+                                         (PERIPH_SS_BASE + 0x00123000 \
+                                         + (qup_id * 0x1000)) :\
+                                         (PERIPH_SS_BASE + 0x00163000 + \
+                                         (qup_id * 0x1000)))
+
+/* DRV strength for sdcc */
+#define SDC1_HDRV_PULL_CTL           (TLMM_BASE_ADDR + 0x00002044)
+
+/* SDHCI */
+#define SDCC_MCI_HC_MODE            (0x00000078)
+#define SDCC_HC_PWRCTL_STATUS_REG   (0x000000DC)
+#define SDCC_HC_PWRCTL_MASK_REG     (0x000000E0)
+#define SDCC_HC_PWRCTL_CLEAR_REG    (0x000000E4)
+#define SDCC_HC_PWRCTL_CTL_REG      (0x000000E8)
+#endif
diff --git a/platform/fsm9010/include/platform/irqs.h b/platform/fsm9010/include/platform/irqs.h
new file mode 100644
index 0000000..6b4900f
--- /dev/null
+++ b/platform/fsm9010/include/platform/irqs.h
@@ -0,0 +1,69 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+ *   * Neither the name of The Linux Foundation, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef __IRQS_FSM9010_H
+#define __IRQS_FSM9010_H
+
+/* MSM ACPU Interrupt Numbers */
+
+/* 0-15:  STI/SGI (software triggered/generated interrupts)
+ * 16-31: PPI (private peripheral interrupts)
+ * 32+:   SPI (shared peripheral interrupts)
+ */
+
+#define GIC_PPI_START                          16
+#define GIC_SPI_START                          32
+
+#define INT_QTMR_NON_SECURE_PHY_TIMER_EXP      (GIC_PPI_START + 3)
+#define INT_QTMR_VIRTUAL_TIMER_EXP             (GIC_PPI_START + 4)
+
+#define INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP      (GIC_SPI_START + 8)
+
+#define USB1_HS_BAM_IRQ                        (GIC_SPI_START + 135)
+#define USB1_HS_IRQ                            (GIC_SPI_START + 134)
+#define USB1_IRQ                               (GIC_SPI_START + 142)
+
+/* Retrofit universal macro names */
+#define INT_USB_HS                             USB1_HS_IRQ
+
+#define EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ         (GIC_SPI_START + 190)
+
+#define NR_MSM_IRQS                            256
+#define NR_GPIO_IRQS                           90
+#define NR_BOARD_IRQS                          0
+
+#define NR_IRQS                                (NR_MSM_IRQS + NR_GPIO_IRQS + \
+                                               NR_BOARD_IRQS)
+
+#define BLSP_QUP_IRQ(blsp_id, qup_id)          ((blsp_id == 1) ? \
+                                               ((GIC_SPI_START + 95) + qup_id):\
+                                               ((GIC_SPI_START + 101) + qup_id))
+
+#define SDCC1_PWRCTL_IRQ                       (GIC_SPI_START + 138)
+#endif	/* __IRQS_FSM9010_H */
diff --git a/platform/fsm9010/platform.c b/platform/fsm9010/platform.c
new file mode 100644
index 0000000..61a10e0
--- /dev/null
+++ b/platform/fsm9010/platform.c
@@ -0,0 +1,167 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <qgic.h>
+#include <qtimer.h>
+#include <platform/clock.h>
+#include <mmu.h>
+#include <arch/arm/mmu.h>
+#include <smem.h>
+#include <board.h>
+#include <boot_stats.h>
+
+#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
+
+/* LK memory - cacheable, write through */
+#define LK_MEMORY         (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+                           MMU_MEMORY_AP_READ_WRITE)
+
+/* Peripherals - non-shared device */
+#define IOMAP_MEMORY      (MMU_MEMORY_TYPE_DEVICE_SHARED | \
+                           MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+/* IMEM memory - cacheable, write through */
+#define IMEM_MEMORY       (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+                           MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+static mmu_section_t mmu_section_table[] = {
+/*   Physical addr,    Virtual addr,     Size (in MB),   Flags */
+	{MEMBASE,          MEMBASE,          (MEMSIZE / MB), LK_MEMORY},
+	{MSM_IOMAP_BASE,   MSM_IOMAP_BASE,   MSM_IOMAP_SIZE, IOMAP_MEMORY},
+	/* IMEM  needs a seperate entry in the table as it's length is only 0x8000. */
+	{SYSTEM_IMEM_BASE, SYSTEM_IMEM_BASE, 1,              IMEM_MEMORY},
+};
+
+/* Boot timestamps */
+#define BS_INFO_OFFSET     (0x6B0)
+#define BS_INFO_ADDR       (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET)
+
+void platform_early_init(void)
+{
+	board_init();
+	platform_clock_init();
+	qgic_init();
+	qtimer_init();
+}
+
+void platform_init(void)
+{
+	dprintf(INFO, "platform_init()\n");
+}
+
+uint32_t platform_get_sclk_count(void)
+{
+	return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
+}
+
+addr_t get_bs_info_addr()
+{
+	return ((addr_t) BS_INFO_ADDR);
+}
+
+void platform_uninit(void)
+{
+	qtimer_uninit();
+}
+
+int platform_use_identity_mmu_mappings(void)
+{
+	/* Use only the mappings specified in this file. */
+	return 0;
+}
+
+addr_t platform_get_virt_to_phys_mapping(addr_t virt_addr)
+{
+	/* Return same address as we are using 1-1 mapping. */
+	return virt_addr;
+}
+
+addr_t platform_get_phys_to_virt_mapping(addr_t phys_addr)
+{
+	/* Return same address as we are using 1-1 mapping. */
+	return phys_addr;
+}
+
+
+/* Setup memory for this platform */
+void platform_init_mmu_mappings(void)
+{
+	uint32_t i;
+	uint32_t sections;
+	ram_partition ptn_entry;
+	uint32_t table_size = ARRAY_SIZE(mmu_section_table);
+	uint32_t len = 0;
+
+	ASSERT(smem_ram_ptable_init_v1());
+
+	len = smem_get_ram_ptable_len();
+
+	/* Configure the MMU page entries for SDRAM and IMEM memory read
+	   from the smem ram table */
+	for (i = 0; i < len; i++)
+	{
+		smem_get_ram_ptable_entry(&ptn_entry, i);
+		if ((ptn_entry.type == SYS_MEMORY) &&
+		    ((ptn_entry.category == SDRAM) ||
+		     (ptn_entry.category == IMEM)))
+		{
+			/* Check to ensure that start address is 1MB aligned */
+			ASSERT((ptn_entry.start & (MB-1)) == 0);
+
+			sections = ptn_entry.size / MB;
+			while(sections--)
+			{
+				arm_mmu_map_section(
+					(ptn_entry.start + sections * MB),
+					(ptn_entry.start + sections * MB),
+					(MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH |
+					 MMU_MEMORY_AP_READ_WRITE |
+					 MMU_MEMORY_XN));
+			}
+		}
+	}
+
+	/* Configure the MMU page entries for memory read from the
+	   mmu_section_table */
+	for (i = 0; i < table_size; i++)
+	{
+		sections = mmu_section_table[i].num_of_sections;
+
+		while (sections--)
+		{
+			arm_mmu_map_section(mmu_section_table[i].paddress +
+					    sections * MB,
+					    mmu_section_table[i].vaddress +
+					    sections * MB,
+					    mmu_section_table[i].flags);
+		}
+	}
+}
diff --git a/platform/fsm9010/rules.mk b/platform/fsm9010/rules.mk
new file mode 100644
index 0000000..70a1230
--- /dev/null
+++ b/platform/fsm9010/rules.mk
@@ -0,0 +1,32 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+ARCH    := arm
+ARM_CPU := cortex-a8
+CPU     := generic
+
+DEFINES += ARM_CPU_CORE_A7
+
+MMC_SLOT         := 1
+
+DEFINES += PERIPH_BLK_BLSP=1
+DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
+	   MMC_SLOT=$(MMC_SLOT)
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
+
+# Disabling stack-protection for lk
+# as it's not yet supported by bootloader's libc
+CFLAGS += -fno-stack-protector
+
+DEVS += fbcon
+MODULES += dev/fbcon
+
+OBJS += \
+	$(LOCAL_DIR)/platform.o \
+	$(LOCAL_DIR)/acpuclock.o \
+	$(LOCAL_DIR)/fsm9010-clock.o \
+	$(LOCAL_DIR)/gpio.o
+
+LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
+
+include platform/msm_shared/rules.mk
diff --git a/platform/msm8916/acpuclock.c b/platform/msm8916/acpuclock.c
index 5b08c53..bcc65f0 100644
--- a/platform/msm8916/acpuclock.c
+++ b/platform/msm8916/acpuclock.c
@@ -263,15 +263,20 @@
 }
 
 /* Disable all the branch clocks needed by the DSI controller */
-void gcc_dsi_clocks_disable(void)
+void gcc_dsi_clocks_disable(uint8_t dual_dsi)
 {
 	clk_disable(clk_get("mdss_esc0_clk"));
 	writel(0x0, DSI_PIXEL0_CBCR);
 	writel(0x0, DSI_BYTE0_CBCR);
+	if (dual_dsi) {
+		clk_disable(clk_get("mdss_esc1_clk"));
+		writel(0x0, DSI_PIXEL1_CBCR);
+		writel(0x0, DSI_BYTE1_CBCR);
+	}
 }
 
 /* Configure all the branch clocks needed by the DSI controller */
-void gcc_dsi_clocks_enable(uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d)
+void gcc_dsi_clocks_enable(uint8_t dual_dsi, uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d)
 {
 	int ret;
 
@@ -296,6 +301,30 @@
 		dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret);
 		ASSERT(0);
 	}
+
+	if (dual_dsi) {
+		/* Configure Byte clock -autopll- This will not change becasue
+		byte clock does not need any divider*/
+		writel(0x100, DSI_BYTE1_CFG_RCGR);
+		writel(0x1, DSI_BYTE1_CMD_RCGR);
+		writel(0x1, DSI_BYTE1_CBCR);
+
+		/* Configure Pixel clock */
+		writel(0x100, DSI_PIXEL1_CFG_RCGR);
+		writel(0x1, DSI_PIXEL1_CMD_RCGR);
+		writel(0x1, DSI_PIXEL1_CBCR);
+
+		writel(pclk0_m, DSI_PIXEL1_M);
+		writel(pclk0_n, DSI_PIXEL1_N);
+		writel(pclk0_d, DSI_PIXEL1_D);
+
+		/* Configure ESC clock */
+		ret = clk_get_set_enable("mdss_esc1_clk", 0, 1);
+		if (ret) {
+			dprintf(CRITICAL, "failed to set esc1_clk ret = %d\n", ret);
+			ASSERT(0);
+		}
+	}
 }
 
 /* Function to asynchronously reset CE.
diff --git a/platform/msm8916/include/platform/clock.h b/platform/msm8916/include/platform/clock.h
index bcbbc2e..4b0a5ef 100644
--- a/platform/msm8916/include/platform/clock.h
+++ b/platform/msm8916/include/platform/clock.h
@@ -65,6 +65,19 @@
 #define DSI_PIXEL0_N                    REG_MM(0x4D00C)
 #define DSI_PIXEL0_D                    REG_MM(0x4D010)
 
+#define DSI_BYTE1_CMD_RCGR              REG_MM(0x4D0B0)
+#define DSI_BYTE1_CFG_RCGR              REG_MM(0x4D0B4)
+#define DSI_BYTE1_CBCR                  REG_MM(0x4D0A0)
+#define DSI_ESC1_CMD_RCGR               REG_MM(0x4D0A8)
+#define DSI_ESC1_CFG_RCGR               REG_MM(0x4D0AC)
+#define DSI_ESC1_CBCR                   REG_MM(0x4D09C)
+#define DSI_PIXEL1_CMD_RCGR             REG_MM(0x4D0B8)
+#define DSI_PIXEL1_CFG_RCGR             REG_MM(0x4D0BC)
+#define DSI_PIXEL1_CBCR                 REG_MM(0x4D0A4)
+#define DSI_PIXEL1_M                    REG_MM(0x4D0C0)
+#define DSI_PIXEL1_N                    REG_MM(0x4D0C4)
+#define DSI_PIXEL1_D                    REG_MM(0x4D0C8)
+
 void platform_clock_init(void);
 
 void clock_init_mmc(uint32_t interface);
diff --git a/platform/msm8916/include/platform/iomap.h b/platform/msm8916/include/platform/iomap.h
index f4537a9..9596622 100644
--- a/platform/msm8916/include/platform/iomap.h
+++ b/platform/msm8916/include/platform/iomap.h
@@ -146,9 +146,9 @@
 /* MDSS */
 #define MIPI_DSI_BASE               (0x1A98000)
 #define MIPI_DSI0_BASE              MIPI_DSI_BASE
-#define MIPI_DSI1_BASE              MIPI_DSI_BASE
+#define MIPI_DSI1_BASE              (0x1AA0000)
 #define DSI0_PHY_BASE               (0x1A98500)
-#define DSI1_PHY_BASE               DSI0_PHY_BASE
+#define DSI1_PHY_BASE               (0x1AA0500)
 #define DSI0_PLL_BASE               (0x1A98300)
 #define DSI1_PLL_BASE               DSI0_PLL_BASE
 #define REG_DSI(off)                (MIPI_DSI_BASE + 0x04 + (off))
@@ -176,6 +176,17 @@
 #define MDP_CLK_CTRL4                           REG_MDP(0x013B0)
 #define MDP_CLK_CTRL5                           REG_MDP(0x013B8)
 
+#define MDP_INTF_0_BASE                         REG_MDP(0x11F00)
+#define MDP_INTF_1_BASE                         REG_MDP(0x12700)
+#define MDP_INTF_2_BASE                         REG_MDP(0x12F00)
+
+#define MDP_REG_SPLIT_DISPLAY_EN                REG_MDP(0x12f4)
+#define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL    REG_MDP(0x12F8)
+#define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL    REG_MDP(0x13F0)
+
+#define MDP_REG_PPB0_CNTL                       REG_MDP(0x1420)
+#define MDP_REG_PPB0_CONFIG                     REG_MDP(0x1424)
+
 #define MMSS_MDP_SMP_ALLOC_W_BASE               REG_MDP(0x1080)
 #define MMSS_MDP_SMP_ALLOC_R_BASE               REG_MDP(0x1130)
 
diff --git a/platform/msm8916/msm8916-clock.c b/platform/msm8916/msm8916-clock.c
index f99a0fb..d4289c1 100644
--- a/platform/msm8916/msm8916-clock.c
+++ b/platform/msm8916/msm8916-clock.c
@@ -343,6 +343,11 @@
 	F_END
 };
 
+static struct clk_freq_tbl ftbl_mdss_esc1_1_clk[] = {
+	F_MM(19200000,    cxo,   1,   0,   0),
+	F_END
+};
+
 static struct clk_freq_tbl ftbl_mdp_clk[] = {
 	F( 80000000,  gpll0,   10,    0,    0),
 	F( 100000000, gpll0,    8,    0,    0),
@@ -376,6 +381,18 @@
 	},
 };
 
+static struct rcg_clk dsi_esc1_clk_src = {
+	.cmd_reg  = (uint32_t *) DSI_ESC1_CMD_RCGR,
+	.cfg_reg  = (uint32_t *) DSI_ESC1_CFG_RCGR,
+	.set_rate = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl = ftbl_mdss_esc1_1_clk,
+
+	.c        = {
+		.dbg_name = "dsi_esc1_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
 static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = {
 	F_MM(19200000,    cxo,   1,   0,   0),
 	F_END
@@ -404,6 +421,17 @@
 	},
 };
 
+static struct branch_clk mdss_esc1_clk = {
+	.cbcr_reg    = (uint32_t *) DSI_ESC1_CBCR,
+	.parent      = &dsi_esc1_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mdss_esc1_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
 static struct branch_clk mdss_axi_clk = {
 	.cbcr_reg    = (uint32_t *) MDP_AXI_CBCR,
 	.has_sibling = 1,
@@ -551,6 +579,7 @@
 
 	CLK_LOOKUP("mdp_ahb_clk",          mdp_ahb_clk.c),
 	CLK_LOOKUP("mdss_esc0_clk",        mdss_esc0_clk.c),
+	CLK_LOOKUP("mdss_esc1_clk",        mdss_esc1_clk.c),
 	CLK_LOOKUP("mdss_axi_clk",         mdss_axi_clk.c),
 	CLK_LOOKUP("mdss_vsync_clk",       mdss_vsync_clk.c),
 	CLK_LOOKUP("mdss_mdp_clk_src",     mdss_mdp_clk_src.c),
diff --git a/platform/msm8994/acpuclock.c b/platform/msm8994/acpuclock.c
index c80d76d..cd990f2 100644
--- a/platform/msm8994/acpuclock.c
+++ b/platform/msm8994/acpuclock.c
@@ -93,6 +93,12 @@
 		ASSERT(0);
 	}
 
+	ret = clk_get_set_enable("usb_phy_cfg_ahb2phy_clk", 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to enable usb_phy_cfg_ahb2phy_clk = %d\n", ret);
+		ASSERT(0);
+	}
 }
 
 void clock_init_mmc(uint32_t interface)
@@ -284,3 +290,183 @@
 
 	return;
 }
+
+void mdp_gdsc_ctrl(uint8_t enable)
+{
+	uint32_t reg = 0;
+	reg = readl(MDP_GDSCR);
+	if (enable) {
+		if (!(reg & GDSC_POWER_ON_BIT)) {
+			reg &=  ~(BIT(0) | GDSC_EN_FEW_WAIT_MASK);
+			reg |= GDSC_EN_FEW_WAIT_256_MASK;
+			writel(reg, MDP_GDSCR);
+			while(!(readl(MDP_GDSCR) & (GDSC_POWER_ON_BIT)));
+		} else {
+			dprintf(INFO, "MDP GDSC already enabled\n");
+		}
+	} else {
+		reg |= BIT(0);
+		writel(reg, MDP_GDSCR);
+		while(readl(MDP_GDSCR) & (GDSC_POWER_ON_BIT));
+	}
+}
+
+/* Configure MDP clock */
+void mdp_clock_enable(void)
+{
+	int ret;
+
+	/* Set MDP clock to 240MHz */
+	ret = clk_get_set_enable("mdp_ahb_clk", 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set mdp_ahb_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	ret = clk_get_set_enable("mdss_mdp_clk_src", 240000000, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set mdp_clk_src ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	ret = clk_get_set_enable("mdss_vsync_clk", 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set mdss vsync clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	ret = clk_get_set_enable("mdss_mdp_clk", 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set mdp_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	ret = clk_get_set_enable("mdss_mdp_lut_clk", 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set lut_mdp clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+}
+
+void mdp_clock_disable()
+{
+	clk_disable(clk_get("mdss_vsync_clk"));
+	clk_disable(clk_get("mdss_mdp_clk"));
+	clk_disable(clk_get("mdss_mdp_lut_clk"));
+	clk_disable(clk_get("mdss_mdp_clk_src"));
+	clk_disable(clk_get("mdp_ahb_clk"));
+
+}
+
+void mmss_bus_clock_enable(void)
+{
+	int ret;
+	/* Configure MMSSNOC AXI clock */
+	ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	/* Configure S0 AXI clock */
+	ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	/* Configure AXI clock */
+	ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+}
+
+void mmss_bus_clock_disable(void)
+{
+	/* Disable MDSS AXI clock */
+	clk_disable(clk_get("mdss_axi_clk"));
+
+	/* Disable MMSSNOC S0AXI clock */
+	clk_disable(clk_get("mmss_s0_axi_clk"));
+
+	/* Disable MMSSNOC AXI clock */
+	clk_disable(clk_get("mmss_mmssnoc_axi_clk"));
+}
+
+void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi,
+			uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d)
+{
+	int ret;
+
+	/* Configure Byte clock -autopll- This will not change because
+	byte clock does not need any divider*/
+	writel(0x100, DSI_BYTE0_CFG_RCGR);
+	writel(0x1, DSI_BYTE0_CMD_RCGR);
+	writel(0x1, DSI_BYTE0_CBCR);
+
+	/* Configure Pixel clock */
+	writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
+	writel(0x1, DSI_PIXEL0_CMD_RCGR);
+	writel(0x1, DSI_PIXEL0_CBCR);
+
+	writel(pclk0_m, DSI_PIXEL0_M);
+	writel(pclk0_n, DSI_PIXEL0_N);
+	writel(pclk0_d, DSI_PIXEL0_D);
+
+	/* Configure ESC clock */
+	ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	if (dual_dsi) {
+		/* Configure Byte 1 clock */
+		writel(0x100, DSI_BYTE1_CFG_RCGR);
+		writel(0x1, DSI_BYTE1_CMD_RCGR);
+		writel(0x1, DSI_BYTE1_CBCR);
+
+		/* Configure Pixel clock */
+		writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL1_CFG_RCGR);
+		writel(0x1, DSI_PIXEL1_CMD_RCGR);
+		writel(0x1, DSI_PIXEL1_CBCR);
+
+		writel(pclk0_m, DSI_PIXEL1_M);
+		writel(pclk0_n, DSI_PIXEL1_N);
+		writel(pclk0_d, DSI_PIXEL1_D);
+
+		/* Configure ESC clock */
+		ret = clk_get_set_enable("mdss_esc1_clk", 0, 1);
+		if(ret)
+		{
+			dprintf(CRITICAL, "failed to set esc1_clk ret = %d\n", ret);
+			ASSERT(0);
+		}
+	}
+}
+
+void mmss_dsi_clock_disable(uint32_t dual_dsi)
+{
+	/* Disable ESC clock */
+	clk_disable(clk_get("mdss_esc0_clk"));
+	writel(0x0, DSI_BYTE0_CBCR);
+	writel(0x0, DSI_PIXEL0_CBCR);
+
+	if (dual_dsi) {
+		/* Disable ESC clock */
+		clk_disable(clk_get("mdss_esc1_clk"));
+		writel(0x0, DSI_BYTE1_CBCR);
+		writel(0x0, DSI_PIXEL1_CBCR);
+	}
+}
diff --git a/platform/msm8994/include/platform/clock.h b/platform/msm8994/include/platform/clock.h
index bad5743..c50fef7 100644
--- a/platform/msm8994/include/platform/clock.h
+++ b/platform/msm8994/include/platform/clock.h
@@ -34,6 +34,71 @@
 
 #define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
 
+#define REG_MM(off)                     (MSM_MMSS_CLK_CTL_BASE + (off))
+
+#define MDP_GDSCR                       REG_MM(0x2304)
+#define GDSC_POWER_ON_BIT               BIT(31)
+#define GDSC_POWER_ON_STATUS_BIT        BIT(29)
+#define GDSC_EN_FEW_WAIT_MASK           (0x0F << 16)
+#define GDSC_EN_FEW_WAIT_256_MASK       BIT(19)
+
+#define VSYNC_CMD_RCGR                  REG_MM(0x2080)
+#define VSYNC_CFG_RCGR                  REG_MM(0x2084)
+#define MDSS_VSYNC_CBCR                 REG_MM(0x2328)
+#define MDP_CMD_RCGR                    REG_MM(0x2040)
+#define MDP_CFG_RCGR                    REG_MM(0x2044)
+#define MDP_CBCR                        REG_MM(0x231C)
+#define MDP_LUT_CBCR                    REG_MM(0x2320)
+#define MDP_AHB_CBCR                    REG_MM(0x2308)
+
+#define MDP_AXI_CMD_RCGR                REG_MM(0x5040)
+#define MDP_AXI_CFG_RCGR                REG_MM(0x5044)
+
+#define MDP_AXI_CBCR                    REG_MM(0x2310)
+#define MMSS_S0_AXI_CBCR                REG_MM(0x5064)
+#define MMSS_MMSSNOC_AXI_CBCR           REG_MM(0x506C)
+
+#define DSI_BYTE0_CMD_RCGR              REG_MM(0x2120)
+#define DSI_BYTE0_CFG_RCGR              REG_MM(0x2124)
+#define DSI_BYTE0_CBCR                  REG_MM(0x233C)
+#define DSI_ESC0_CMD_RCGR               REG_MM(0x2160)
+#define DSI_ESC0_CFG_RCGR               REG_MM(0x2164)
+#define DSI_ESC0_CBCR                   REG_MM(0x2344)
+#define DSI_PIXEL0_CMD_RCGR             REG_MM(0x2000)
+#define DSI_PIXEL0_CFG_RCGR             REG_MM(0x2004)
+#define DSI_PIXEL0_CBCR                 REG_MM(0x2314)
+#define DSI_PIXEL0_M                    REG_MM(0x2008)
+#define DSI_PIXEL0_N                    REG_MM(0x200C)
+#define DSI_PIXEL0_D                    REG_MM(0x2010)
+
+#define DSI0_PHY_PLL_OUT                BIT(8)
+#define PIXEL_SRC_DIV_1_5               BIT(1)
+
+#define DSI_BYTE1_CMD_RCGR              REG_MM(0x2140)
+#define DSI_BYTE1_CFG_RCGR              REG_MM(0x2144)
+#define DSI_BYTE1_CBCR                  REG_MM(0x2340)
+#define DSI_ESC1_CMD_RCGR               REG_MM(0x2180)
+#define DSI_ESC1_CFG_RCGR               REG_MM(0x2184)
+#define DSI_ESC1_CBCR                   REG_MM(0x2348)
+#define DSI_PIXEL1_CMD_RCGR             REG_MM(0x2020)
+#define DSI_PIXEL1_CFG_RCGR             REG_MM(0x2024)
+#define DSI_PIXEL1_CBCR                 REG_MM(0x2318)
+#define DSI_PIXEL1_M                    REG_MM(0x2028)
+#define DSI_PIXEL1_N                    REG_MM(0x202C)
+#define DSI_PIXEL1_D                    REG_MM(0x2030)
+
+#define MDSS_EDPPIXEL_CBCR              REG_MM(0x232C)
+#define MDSS_EDPLINK_CBCR               REG_MM(0x2330)
+#define MDSS_EDPAUX_CBCR                REG_MM(0x2334)
+#define EDPPIXEL_M                      REG_MM(0x20A8)
+#define EDPPIXEL_N                      REG_MM(0x20AC)
+#define EDPPIXEL_D                      REG_MM(0x20B0)
+#define EDPPIXEL_CFG_RCGR               REG_MM(0x20A4)
+#define EDPPIXEL_CMD_RCGR               REG_MM(0x20A0)
+#define EDPLINK_CFG_RCGR                REG_MM(0x20C4)
+#define EDPLINK_CMD_RCGR                REG_MM(0x20C0)
+#define EDPAUX_CFG_RCGR                 REG_MM(0x20E4)
+#define EDPAUX_CMD_RCGR                 REG_MM(0x20E0)
 
 void platform_clock_init(void);
 
diff --git a/platform/msm8994/include/platform/iomap.h b/platform/msm8994/include/platform/iomap.h
index fd51de5..aade4bd 100644
--- a/platform/msm8994/include/platform/iomap.h
+++ b/platform/msm8994/include/platform/iomap.h
@@ -52,6 +52,7 @@
 #define APCS_KPSS_WDT_BASE          (KPSS_BASE + 0x00017000)
 #define KPSS_APCS_QTMR_AC_BASE      (KPSS_BASE + 0x00020000)
 #define KPSS_APCS_F0_QTMR_V1_BASE   (KPSS_BASE + 0x00021000)
+#define APCS_ALIAS0_IPC_INTERRUPT   (KPSS_BASE + 0x0000D008)
 #define QTMR_BASE                   KPSS_APCS_F0_QTMR_V1_BASE
 
 #define PERIPH_SS_BASE              0xF9800000
@@ -81,6 +82,11 @@
 #define QUSB2_PHY_BASE              (PERIPH_SS_BASE + 0x00339000)
 
 #define QUSB2PHY_PORT_POWERDOWN     (QUSB2_PHY_BASE + 0x000000B4)
+#define QUSB2PHY_PORT_UTMI_CTRL2    (QUSB2_PHY_BASE + 0x000000C4)
+#define QUSB2PHY_PORT_TUNE1         (QUSB2_PHY_BASE + 0x00000080)
+#define QUSB2PHY_PORT_TUNE2         (QUSB2_PHY_BASE + 0x00000084)
+#define QUSB2PHY_PORT_TUNE3         (QUSB2_PHY_BASE + 0x00000088)
+#define QUSB2PHY_PORT_TUNE4         (QUSB2_PHY_BASE + 0x0000008C)
 
 #define MSM_USB30_BASE              0xF9200000
 #define MSM_USB30_QSCRATCH_BASE     0xF92F8800
@@ -207,4 +213,128 @@
 #define TCSR_PHSS_USB2_PHY_SEL               0xFD4AB000
 #define PLATFORM_QMP_OFFSET                  0x8
 
+#define SMEM_TARG_INFO_ADDR                  0xFE805FF0
+
+/* MDSS */
+#define MSM_MMSS_CLK_CTL_BASE       0xFD8C0000
+#define MIPI_DSI_BASE               (0xFD998000)
+#define MIPI_DSI0_BASE              (MIPI_DSI_BASE)
+#define MIPI_DSI1_BASE              (0xFD9A0000)
+#define DSI0_PHY_BASE               (0xFD998500)
+#define DSI1_PHY_BASE               (0xFD9A0500)
+#define DSI0_PLL_BASE               (0xFD998300)
+#define DSI1_PLL_BASE               (0xFD9A0300)
+#define REG_DSI(off)                (MIPI_DSI_BASE + 0x04 + (off))
+
+#define MDP_BASE                    (0xfd900000)
+
+#define REG_MDP(off)                (MDP_BASE + (off))
+#define MDP_HW_REV                              REG_MDP(0x1000)
+#define MDP_INTR_EN                             REG_MDP(0x1010)
+#define MDP_INTR_CLEAR                          REG_MDP(0x1018)
+#define MDP_HIST_INTR_EN                        REG_MDP(0x101C)
+
+#define MDP_DISP_INTF_SEL                       REG_MDP(0x1004)
+#define MDP_VIDEO_INTF_UNDERFLOW_CTL            REG_MDP(0x12E0)
+#define MDP_UPPER_NEW_ROI_PRIOR_RO_START        REG_MDP(0x11EC)
+#define MDP_LOWER_NEW_ROI_PRIOR_TO_START        REG_MDP(0x13F8)
+
+#define MDP_INTF_0_TIMING_ENGINE_EN             REG_MDP(0x6b000)
+#define MDP_INTF_1_TIMING_ENGINE_EN             REG_MDP(0x6b800)
+
+#define MDP_CTL_0_BASE              		REG_MDP(0x2000)
+#define MDP_CTL_1_BASE              		REG_MDP(0x2200)
+
+#define MDP_REG_SPLIT_DISPLAY_EN                REG_MDP(0x12F4)
+#define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL    REG_MDP(0x12F8)
+#define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL    REG_MDP(0x13F0)
+
+/* can not find following two registers */
+#define MDP_REG_PPB0_CNTL                       REG_MDP(0x1420)
+#define MDP_REG_PPB0_CONFIG                     REG_MDP(0x1424)
+
+#define MDP_INTF_0_BASE                         REG_MDP(0x6b000)
+#define MDP_INTF_1_BASE                         REG_MDP(0x6b800)
+#define MDP_INTF_2_BASE                         REG_MDP(0x6c000)
+
+
+#define MDP_CLK_CTRL0                           REG_MDP(0x12AC)
+#define MDP_CLK_CTRL1                           REG_MDP(0x12B4)
+#define MDP_CLK_CTRL2                           REG_MDP(0x12BC)
+#define MDP_CLK_CTRL3                           REG_MDP(0x13A8)
+#define MDP_CLK_CTRL4                           REG_MDP(0x13B0)
+#define MDP_CLK_CTRL5                           REG_MDP(0x13B8)
+#define MDP_CLK_CTRL6                           REG_MDP(0x12C4)
+#define MDP_CLK_CTRL7                           REG_MDP(0x13D0)
+
+#define MMSS_MDP_SMP_ALLOC_W_BASE               REG_MDP(0x1080)
+#define MMSS_MDP_SMP_ALLOC_R_BASE               REG_MDP(0x1130)
+
+#define MDP_QOS_REMAPPER_CLASS_0                REG_MDP(0x13d8)
+#define MDP_QOS_REMAPPER_CLASS_1                REG_MDP(0x13dc)
+
+#define VBIF_VBIF_DDR_FORCE_CLK_ON              REG_MDP(0xc8004)
+#define VBIF_VBIF_DDR_OUT_MAX_BURST             REG_MDP(0xc80D8)
+#define VBIF_VBIF_DDR_ARB_CTRL                  REG_MDP(0xc80F0)
+#define VBIF_VBIF_DDR_RND_RBN_QOS_ARB           REG_MDP(0xc8124)
+#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0        REG_MDP(0xc8160)
+#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1        REG_MDP(0xc8164)
+#define VBIF_VBIF_DDR_OUT_AOOO_AXI_EN           REG_MDP(0xc8178)
+#define VBIF_VBIF_DDR_OUT_AX_AOOO               REG_MDP(0xc817C)
+#define VBIF_VBIF_IN_RD_LIM_CONF0               REG_MDP(0xc80B0)
+#define VBIF_VBIF_IN_RD_LIM_CONF1               REG_MDP(0xc80B4)
+#define VBIF_VBIF_IN_RD_LIM_CONF2               REG_MDP(0xc80B8)
+#define VBIF_VBIF_IN_RD_LIM_CONF3               REG_MDP(0xc80BC)
+#define VBIF_VBIF_IN_WR_LIM_CONF0               REG_MDP(0xc80C0)
+#define VBIF_VBIF_IN_WR_LIM_CONF1               REG_MDP(0xc80C4)
+#define VBIF_VBIF_IN_WR_LIM_CONF2               REG_MDP(0xc80C8)
+#define VBIF_VBIF_IN_WR_LIM_CONF3               REG_MDP(0xc80CC)
+#define VBIF_VBIF_ABIT_SHORT                    REG_MDP(0xc8070)
+#define VBIF_VBIF_ABIT_SHORT_CONF               REG_MDP(0xc8074)
+#define VBIF_VBIF_GATE_OFF_WRREQ_EN             REG_MDP(0xc80A8)
+
+#define MDP_VP_0_VIG_0_BASE                     REG_MDP(0x5000)
+#define MDP_VP_0_VIG_1_BASE                     REG_MDP(0x7000)
+#define MDP_VP_0_RGB_0_BASE                     REG_MDP(0x15000)
+#define MDP_VP_0_RGB_1_BASE                     REG_MDP(0x17000)
+#define MDP_VP_0_DMA_0_BASE                     REG_MDP(0x25000)
+#define MDP_VP_0_DMA_1_BASE                     REG_MDP(0x27000)
+#define MDP_VP_0_MIXER_0_BASE                   REG_MDP(0x45000)
+#define MDP_VP_0_MIXER_1_BASE                   REG_MDP(0x46000)
+
+#define DMA_CMD_OFFSET              0x048
+#define DMA_CMD_LENGTH              0x04C
+
+#define INT_CTRL                    0x110
+#define CMD_MODE_DMA_SW_TRIGGER     0x090
+
+#define EOT_PACKET_CTRL             0x0CC
+#define MISR_CMD_CTRL               0x0A0
+#define MISR_VIDEO_CTRL             0x0A4
+#define VIDEO_MODE_CTRL             0x010
+#define HS_TIMER_CTRL               0x0BC
+
+#define SOFT_RESET                  0x118
+#define CLK_CTRL                    0x11C
+#define TRIG_CTRL                   0x084
+#define CTRL                        0x004
+#define COMMAND_MODE_DMA_CTRL       0x03C
+#define COMMAND_MODE_MDP_CTRL       0x040
+#define COMMAND_MODE_MDP_DCS_CMD_CTRL   0x044
+#define COMMAND_MODE_MDP_STREAM0_CTRL   0x058
+#define COMMAND_MODE_MDP_STREAM0_TOTAL  0x05C
+#define COMMAND_MODE_MDP_STREAM1_CTRL   0x060
+#define COMMAND_MODE_MDP_STREAM1_TOTAL  0x064
+#define ERR_INT_MASK0               0x10C
+
+#define LANE_SWAP_CTL               0x0B0
+#define TIMING_CTL                  0x0C4
+
+#define VIDEO_MODE_ACTIVE_H         0x024
+#define VIDEO_MODE_ACTIVE_V         0x028
+#define VIDEO_MODE_TOTAL            0x02C
+#define VIDEO_MODE_HSYNC            0x030
+#define VIDEO_MODE_VSYNC            0x034
+#define VIDEO_MODE_VSYNC_VPOS       0x038
+
 #endif
diff --git a/platform/msm8994/include/platform/irqs.h b/platform/msm8994/include/platform/irqs.h
index 25383cb..05bb473 100644
--- a/platform/msm8994/include/platform/irqs.h
+++ b/platform/msm8994/include/platform/irqs.h
@@ -55,6 +55,8 @@
 
 #define UFS_IRQ                                (GIC_SPI_START + 265)
 
+#define SMD_IRQ                                (GIC_SPI_START + 168)
+
 /* Retrofit universal macro names */
 #define INT_USB_HS                             USB1_HS_IRQ
 
diff --git a/platform/msm8994/msm8994-clock.c b/platform/msm8994/msm8994-clock.c
index 68343bf..033a88d 100644
--- a/platform/msm8994/msm8994-clock.c
+++ b/platform/msm8994/msm8994-clock.c
@@ -45,6 +45,8 @@
 #define mmpll1_mm_source_val 2
 #define mmpll3_mm_source_val 3
 #define gpll0_mm_source_val 5
+#define edppll_270_mm_source_val 4
+#define edppll_350_mm_source_val 4
 
 struct clk_freq_tbl rcg_dummy_freq = F_END;
 
@@ -486,6 +488,273 @@
 	},
 };
 
+/* Display clocks */
+static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = {
+	F_MM(19200000,    cxo,   1,   0,   0),
+	F_END
+};
+
+static struct clk_freq_tbl ftbl_mdss_esc1_1_clk[] = {
+	F_MM(19200000,    cxo,   1,   0,   0),
+	F_END
+};
+
+static struct clk_freq_tbl ftbl_mmss_axi_clk[] = {
+	F_MM(19200000,     cxo,     1,   0,   0),
+	F_MM(100000000,  gpll0,     6,   0,   0),
+	F_END
+};
+
+static struct clk_freq_tbl ftbl_mdp_clk[] = {
+	F_MM( 75000000,  gpll0,   8,   0,   0),
+	F_MM( 240000000,  gpll0,   2.5,   0,   0),
+	F_END
+};
+
+static struct rcg_clk dsi_esc0_clk_src = {
+	.cmd_reg  = (uint32_t *) DSI_ESC0_CMD_RCGR,
+	.cfg_reg  = (uint32_t *) DSI_ESC0_CFG_RCGR,
+	.set_rate = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl = ftbl_mdss_esc0_1_clk,
+
+	.c        = {
+		.dbg_name = "dsi_esc0_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct rcg_clk dsi_esc1_clk_src = {
+	.cmd_reg  = (uint32_t *) DSI_ESC1_CMD_RCGR,
+	.cfg_reg  = (uint32_t *) DSI_ESC1_CFG_RCGR,
+	.set_rate = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl = ftbl_mdss_esc1_1_clk,
+
+	.c        = {
+		.dbg_name = "dsi_esc1_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = {
+	F_MM(19200000,    cxo,   1,   0,   0),
+	F_END
+};
+
+static struct rcg_clk vsync_clk_src = {
+	.cmd_reg  = (uint32_t *) VSYNC_CMD_RCGR,
+	.cfg_reg  = (uint32_t *) VSYNC_CFG_RCGR,
+	.set_rate = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl = ftbl_mdss_vsync_clk,
+
+	.c        = {
+		.dbg_name = "vsync_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct rcg_clk mdp_axi_clk_src = {
+	.cmd_reg  = (uint32_t *) MDP_AXI_CMD_RCGR,
+	.cfg_reg  = (uint32_t *) MDP_AXI_CFG_RCGR,
+	.set_rate = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl = ftbl_mmss_axi_clk,
+
+	.c        = {
+		.dbg_name = "mdp_axi_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct branch_clk mdss_esc0_clk = {
+	.cbcr_reg    = (uint32_t *) DSI_ESC0_CBCR,
+	.parent      = &dsi_esc0_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mdss_esc0_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mdss_esc1_clk = {
+	.cbcr_reg    = (uint32_t *) DSI_ESC1_CBCR,
+	.parent      = &dsi_esc1_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mdss_esc1_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mdss_axi_clk = {
+	.cbcr_reg    = (uint32_t *) MDP_AXI_CBCR,
+	.parent      = &mdp_axi_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mdss_axi_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mmss_mmssnoc_axi_clk = {
+	.cbcr_reg    = (uint32_t *) MMSS_MMSSNOC_AXI_CBCR,
+	.parent      = &mdp_axi_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mmss_mmssnoc_axi_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mmss_s0_axi_clk = {
+	.cbcr_reg    = (uint32_t *) MMSS_S0_AXI_CBCR,
+	.parent      = &mdp_axi_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mmss_s0_axi_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mdp_ahb_clk = {
+	.cbcr_reg    = (uint32_t *) MDP_AHB_CBCR,
+	.has_sibling = 1,
+
+	.c           = {
+		.dbg_name = "mdp_ahb_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct rcg_clk mdss_mdp_clk_src = {
+	.cmd_reg      = (uint32_t *) MDP_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) MDP_CFG_RCGR,
+	.set_rate     = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl     = ftbl_mdp_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c            = {
+		.dbg_name = "mdss_mdp_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct branch_clk mdss_mdp_clk = {
+	.cbcr_reg    = (uint32_t *) MDP_CBCR,
+	.parent      = &mdss_mdp_clk_src.c,
+	.has_sibling = 1,
+
+	.c           = {
+		.dbg_name = "mdss_mdp_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mdss_mdp_lut_clk = {
+	.cbcr_reg    = MDP_LUT_CBCR,
+	.parent      = &mdss_mdp_clk_src.c,
+	.has_sibling = 1,
+
+	.c           = {
+		.dbg_name = "mdss_mdp_lut_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mdss_vsync_clk = {
+	.cbcr_reg    = MDSS_VSYNC_CBCR,
+	.parent      = &vsync_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mdss_vsync_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct clk_freq_tbl ftbl_mdss_edpaux_clk[] = {
+	F_MM(19200000,    cxo,   1,   0,   0),
+	F_END
+};
+
+static struct rcg_clk edpaux_clk_src = {
+	.cmd_reg  = (uint32_t *) EDPAUX_CMD_RCGR,
+	.set_rate = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl = ftbl_mdss_edpaux_clk,
+
+	.c        = {
+		.dbg_name = "edpaux_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct branch_clk mdss_edpaux_clk = {
+	.cbcr_reg    = MDSS_EDPAUX_CBCR,
+	.parent      = &edpaux_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mdss_edpaux_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct clk_freq_tbl ftbl_mdss_edplink_clk[] = {
+	F_MDSS(162000000, edppll_270,   2,   0,   0),
+	F_MDSS(270000000, edppll_270,  11,   0,   0),
+	F_END
+};
+
+static struct rcg_clk edplink_clk_src = {
+	.cmd_reg = (uint32_t *)EDPLINK_CMD_RCGR,
+	.set_rate = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl = ftbl_mdss_edplink_clk,
+	.current_freq = &rcg_dummy_freq,
+	.c = {
+		.dbg_name = "edplink_clk_src",
+		.ops = &clk_ops_rcg,
+	},
+};
+
+static struct clk_freq_tbl ftbl_mdss_edppixel_clk[] = {
+	F_MDSS(138500000, edppll_350,   2,   0,   0),
+	F_MDSS(350000000, edppll_350,  11,   0,   0),
+	F_END
+};
+
+static struct rcg_clk edppixel_clk_src = {
+	.cmd_reg = (uint32_t *)EDPPIXEL_CMD_RCGR,
+	.set_rate = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl = ftbl_mdss_edppixel_clk,
+	.current_freq = &rcg_dummy_freq,
+	.c = {
+		.dbg_name = "edppixel_clk_src",
+		.ops = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk mdss_edplink_clk = {
+	.cbcr_reg = (uint32_t *)MDSS_EDPLINK_CBCR,
+	.has_sibling = 0,
+	.parent = &edplink_clk_src.c,
+	.c = {
+		.dbg_name = "mdss_edplink_clk",
+		.ops = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mdss_edppixel_clk = {
+	.cbcr_reg = (uint32_t *)MDSS_EDPPIXEL_CBCR,
+	.has_sibling = 0,
+	.parent = &edppixel_clk_src.c,
+	.c = {
+		.dbg_name = "mdss_edppixel_clk",
+		.ops = &clk_ops_branch,
+	},
+};
 
 /* Clock lookup table */
 static struct clk_lookup msm_8994_clocks[] =
@@ -510,6 +779,22 @@
 	CLK_LOOKUP("usb30_phy_reset",     gcc_usb30_phy_reset.c),
 
 	CLK_LOOKUP("usb_phy_cfg_ahb2phy_clk",     gcc_usb_phy_cfg_ahb2phy_clk.c),
+
+	/* mdss clocks */
+	CLK_LOOKUP("mdp_ahb_clk",          mdp_ahb_clk.c),
+	CLK_LOOKUP("mdss_esc0_clk",        mdss_esc0_clk.c),
+	CLK_LOOKUP("mdss_esc1_clk",        mdss_esc1_clk.c),
+	CLK_LOOKUP("mdss_axi_clk",         mdss_axi_clk.c),
+	CLK_LOOKUP("mmss_mmssnoc_axi_clk", mmss_mmssnoc_axi_clk.c),
+	CLK_LOOKUP("mmss_s0_axi_clk",      mmss_s0_axi_clk.c),
+	CLK_LOOKUP("mdss_vsync_clk",       mdss_vsync_clk.c),
+	CLK_LOOKUP("mdss_mdp_clk_src",     mdss_mdp_clk_src.c),
+	CLK_LOOKUP("mdss_mdp_clk",         mdss_mdp_clk.c),
+	CLK_LOOKUP("mdss_mdp_lut_clk",     mdss_mdp_lut_clk.c),
+
+	CLK_LOOKUP("edp_pixel_clk",        mdss_edppixel_clk.c),
+	CLK_LOOKUP("edp_link_clk",         mdss_edplink_clk.c),
+	CLK_LOOKUP("edp_aux_clk",          mdss_edpaux_clk.c),
 };
 
 void platform_clock_init(void)
diff --git a/platform/msm_shared/board.c b/platform/msm_shared/board.c
index 581477d..fdc8553 100644
--- a/platform/msm_shared/board.c
+++ b/platform/msm_shared/board.c
@@ -34,6 +34,7 @@
 
 static struct board_data board = {UNKNOWN,
 	0,
+	0,
 	HW_PLATFORM_UNKNOWN,
 	HW_PLATFORM_SUBTYPE_UNKNOWN,
 	LINUX_MACHTYPE_UNKNOWN,
@@ -49,6 +50,7 @@
 	unsigned int board_info_len = 0;
 	unsigned ret = 0;
 	unsigned format = 0;
+	unsigned pmic_type = 0;
 	uint8_t i;
 	uint16_t format_major = 0;
 	uint16_t format_minor = 0;
@@ -130,7 +132,21 @@
 			for (i = 0; i < SMEM_V8_SMEM_MAX_PMIC_DEVICES; i++) {
 				board.pmic_info[i].pmic_type = board_info_v8.pmic_info[i].pmic_type;
 				board.pmic_info[i].pmic_version = board_info_v8.pmic_info[i].pmic_version;
+
+				/*
+				 * fill in pimc_board_info with pmic type and pmic version information
+				 * bit no  		  	    |31  24   | 23  16 	    | 15   8 	     |7		  0|
+				 * pimc_board_info = |Unused | Major version | Minor version|PMIC_MODEL|
+				 *
+				 */
+				pmic_type = board_info_v8.pmic_info[i].pmic_type == PMIC_IS_INVALID? 0 : board_info_v8.pmic_info[i].pmic_type;
+
+				board.pmic_info[i].pmic_target = (((board_info_v8.pmic_info[i].pmic_version >> 16) & 0xff) << 16) |
+					   ((board_info_v8.pmic_info[i].pmic_version & 0xff) << 8) | (pmic_type & 0xff);
 			}
+
+			if (format_minor == 0x9)
+				board.foundry_id = board_info_v8.foundry_id;
 		}
 
 		/* HLOS subtype
@@ -179,6 +195,11 @@
 	return board.platform_subtype;
 }
 
+uint32_t board_foundry_id(void)
+{
+	return board.foundry_id;
+}
+
 uint8_t board_pmic_info(struct board_pmic_data *info, uint8_t num_ent)
 {
 	uint8_t i;
@@ -186,12 +207,21 @@
 	for (i = 0; i < num_ent && i < SMEM_MAX_PMIC_DEVICES; i++) {
 		info->pmic_type = board.pmic_info[i].pmic_type;
 		info->pmic_version = board.pmic_info[i].pmic_version;
+		info->pmic_target = board.pmic_info[i].pmic_target;
 		info++;
 	}
 
 	return (i--);
 }
 
+uint32_t board_pmic_target(uint8_t num_ent)
+{
+	if (num_ent < SMEM_MAX_PMIC_DEVICES) {
+		return board.pmic_info[num_ent].pmic_target;
+	}
+	return 0;
+}
+
 uint32_t board_soc_version()
 {
 	return board.platform_version;
diff --git a/platform/msm_shared/boot_device.c b/platform/msm_shared/boot_device.c
index 31f68a2..556ca85 100644
--- a/platform/msm_shared/boot_device.c
+++ b/platform/msm_shared/boot_device.c
@@ -75,7 +75,7 @@
 			sprintf(buf, "%x.sdhci", ((struct mmc_device *)dev)->host.base);
 			break;
 		case BOOT_UFS:
-			sprintf(buf, "%x.ufs", ((struct ufs_dev *)dev)->base);
+			sprintf(buf, "%x.ufshc", ((struct ufs_dev *)dev)->base);
 			break;
 		default:
 			dprintf(CRITICAL,"ERROR: Unexpected boot_device val=%x",val);
diff --git a/platform/msm_shared/dev_tree.c b/platform/msm_shared/dev_tree.c
index 19b5e74..bd24628 100644
--- a/platform/msm_shared/dev_tree.c
+++ b/platform/msm_shared/dev_tree.c
@@ -35,6 +35,8 @@
 #include <string.h>
 #include <platform.h>
 #include <board.h>
+#include <list.h>
+#include <kernel/thread.h>
 
 struct dt_entry_v1
 {
@@ -46,8 +48,9 @@
 };
 
 static struct dt_mem_node_info mem_node;
-
-static int platform_dt_match(struct dt_entry *cur_dt_entry, uint32_t target_variant_id, uint32_t subtype_mask);
+static int platform_dt_absolute_match(struct dt_entry *cur_dt_entry, struct dt_entry_node *dt_list);
+static struct dt_entry *platform_dt_match_best(struct dt_entry_node *dt_list);
+static int update_dtb_entry_node(struct dt_entry_node *dt_list, uint32_t dtb_info);
 extern int target_is_emmc_boot(void);
 extern uint32_t target_dev_tree_mem(void *fdt, uint32_t memory_node_offset);
 /* TODO: This function needs to be moved to target layer to check violations
@@ -58,29 +61,66 @@
 /* Returns soc version if platform id and hardware id matches
    otherwise return 0xFFFFFFFF */
 #define INVALID_SOC_REV_ID 0XFFFFFFFF
-static uint32_t dev_tree_compatible(void *dtb)
+
+/* Add function to allocate dt entry list, used for recording
+*  the entry which conform to platform_dt_absolute_match()
+*/
+static struct dt_entry_node *dt_entry_list_init(void)
+{
+	struct dt_entry_node *dt_node_member = NULL;
+
+	dt_node_member = (struct dt_entry_node *)
+		malloc(sizeof(struct dt_entry_node));
+
+	ASSERT(dt_node_member);
+
+	list_clear_node(&dt_node_member->node);
+	dt_node_member->dt_entry_m = (struct dt_entry *)
+			malloc(sizeof(struct dt_entry));
+	ASSERT(dt_node_member->dt_entry_m);
+
+	memset(dt_node_member->dt_entry_m ,0 ,sizeof(struct dt_entry));
+	return dt_node_member;
+}
+
+static void insert_dt_entry_in_queue(struct dt_entry_node *dt_list, struct dt_entry_node *dt_node_member)
+{
+	list_add_tail(&dt_list->node, &dt_node_member->node);
+}
+
+static void dt_entry_list_delete(struct dt_entry_node *dt_node_member)
+{
+	if (list_in_list(&dt_node_member->node)) {
+			list_delete(&dt_node_member->node);
+			free(dt_node_member->dt_entry_m);
+			free(dt_node_member);
+	}
+}
+
+static int dev_tree_compatible(void *dtb, uint32_t dtb_size, struct dt_entry_node *dtb_list)
 {
 	int root_offset;
 	const void *prop = NULL;
 	const char *plat_prop = NULL;
 	const char *board_prop = NULL;
+	const char *pmic_prop = NULL;
 	char *model = NULL;
-	struct dt_entry cur_dt_entry;
-	struct dt_entry *dt_entry_v2 = NULL;
+	struct dt_entry *cur_dt_entry;
+	struct dt_entry *dt_entry_array = NULL;
 	struct board_id *board_data = NULL;
 	struct plat_id *platform_data = NULL;
+	struct pmic_id *pmic_data = NULL;
 	int len;
 	int len_board_id;
 	int len_plat_id;
 	int min_plat_id_len = 0;
-	uint32_t target_variant_id;
+	int len_pmic_id;
 	uint32_t dtb_ver;
 	uint32_t num_entries = 0;
-	uint32_t i, j, k;
-	uint32_t found = 0;
+	uint32_t i, j, k, n;
 	uint32_t msm_data_count;
 	uint32_t board_data_count;
-	uint32_t soc_rev;
+	uint32_t pmic_data_count;
 
 	root_offset = fdt_path_offset(dtb, "/");
 	if (root_offset < 0)
@@ -92,19 +132,32 @@
 		ASSERT(model);
 		strlcpy(model, prop, len);
 	} else {
-		model[0] = '\0';
+		dprintf(INFO, "model does not exist in device tree\n");
 	}
-
-	/* Find the board-id prop from DTB , if board-id is present then
-	 * the DTB is version 2 */
+	/* Find the pmic-id prop from DTB , if pmic-id is present then
+	* the DTB is version 3, otherwise find the board-id prop from DTB ,
+	* if board-id is present then the DTB is version 2 */
+	pmic_prop = (const char *)fdt_getprop(dtb, root_offset, "qcom,pmic-id", &len_pmic_id);
 	board_prop = (const char *)fdt_getprop(dtb, root_offset, "qcom,board-id", &len_board_id);
-	if (board_prop)
-	{
+	if (pmic_prop && (len_pmic_id > 0) && board_prop && (len_board_id > 0)) {
+		if ((len_pmic_id % PMIC_ID_SIZE) || (len_board_id % BOARD_ID_SIZE))
+		{
+			dprintf(CRITICAL, "qcom,pmic-id(%d) or qcom,board-id(%d) in device tree is not a multiple of (%d %d)\n",
+				len_pmic_id, len_board_id, PMIC_ID_SIZE, BOARD_ID_SIZE);
+			return false;
+		}
+		dtb_ver = DEV_TREE_VERSION_V3;
+		min_plat_id_len = PLAT_ID_SIZE;
+	} else if (board_prop && len_board_id > 0) {
+		if (len_board_id % BOARD_ID_SIZE)
+		{
+			dprintf(CRITICAL, "qcom,board-id in device tree is (%d) not a multiple of (%d)\n",
+				len_board_id, BOARD_ID_SIZE);
+			return false;
+		}
 		dtb_ver = DEV_TREE_VERSION_V2;
 		min_plat_id_len = PLAT_ID_SIZE;
-	}
-	else
-	{
+	} else {
 		dtb_ver = DEV_TREE_VERSION_V1;
 		min_plat_id_len = DT_ENTRY_V1_SIZE;
 	}
@@ -126,80 +179,145 @@
 	 * y: variant_id
 	 * z: SOC rev
 	 */
-	if (dtb_ver == DEV_TREE_VERSION_V1)
-	{
-		while (len_plat_id)
-		{
-			cur_dt_entry.platform_id = fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->platform_id);
-			cur_dt_entry.variant_id = fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->variant_id);
-			cur_dt_entry.soc_rev = fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->soc_rev);
-			cur_dt_entry.board_hw_subtype = board_hardware_subtype();
+	if (dtb_ver == DEV_TREE_VERSION_V1) {
+		cur_dt_entry = (struct dt_entry *)
+				malloc(sizeof(struct dt_entry));
 
-			target_variant_id = board_hardware_id();
+		if (!cur_dt_entry) {
+			dprintf(CRITICAL, "Out of memory\n");
+			return false;
+		}
+		memset(cur_dt_entry, 0, sizeof(struct dt_entry));
+
+		while (len_plat_id) {
+			cur_dt_entry->platform_id = fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->platform_id);
+			cur_dt_entry->variant_id = fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->variant_id);
+			cur_dt_entry->soc_rev = fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->soc_rev);
+			cur_dt_entry->board_hw_subtype =
+				fdt32_to_cpu(((const struct dt_entry_v1 *)plat_prop)->variant_id) >> 0x18;
+			cur_dt_entry->pmic_rev[0] = board_pmic_target(0);
+			cur_dt_entry->pmic_rev[1] = board_pmic_target(1);
+			cur_dt_entry->pmic_rev[2] = board_pmic_target(2);
+			cur_dt_entry->pmic_rev[3] = board_pmic_target(3);
+			cur_dt_entry->offset = (uint32_t)dtb;
+			cur_dt_entry->size = dtb_size;
 
 			dprintf(SPEW, "Found an appended flattened device tree (%s - %u %u 0x%x)\n",
 				*model ? model : "unknown",
-				cur_dt_entry.platform_id, cur_dt_entry.variant_id, cur_dt_entry.soc_rev);
+				cur_dt_entry->platform_id, cur_dt_entry->variant_id, cur_dt_entry->soc_rev);
 
-			if (platform_dt_match(&cur_dt_entry, target_variant_id, 0) == 1)
-			{
+			if (platform_dt_absolute_match(cur_dt_entry, dtb_list)) {
+				dprintf(SPEW, "Device tree exact match the board: <%u %u 0x%x> != <%u %u 0x%x>\n",
+					cur_dt_entry->platform_id,
+					cur_dt_entry->variant_id,
+					cur_dt_entry->soc_rev,
+					board_platform_id(),
+					board_hardware_id(),
+					board_soc_version());
+
+			} else {
 				dprintf(SPEW, "Device tree's msm_id doesn't match the board: <%u %u 0x%x> != <%u %u 0x%x>\n",
-							  cur_dt_entry.platform_id,
-							  cur_dt_entry.variant_id,
-							  cur_dt_entry.soc_rev,
-							  board_platform_id(),
-							  board_hardware_id(),
-							  board_soc_version());
+					cur_dt_entry->platform_id,
+					cur_dt_entry->variant_id,
+					cur_dt_entry->soc_rev,
+					board_platform_id(),
+					board_hardware_id(),
+					board_soc_version());
 				plat_prop += DT_ENTRY_V1_SIZE;
 				len_plat_id -= DT_ENTRY_V1_SIZE;
 				continue;
 			}
-			else
-			{
-				found = 1;
-				break;
-			}
 		}
+		free(cur_dt_entry);
+
 	}
 	/*
-	 * If DTB Version is '2' then we have split DTB with board & msm data
-	 * populated saperately in board-id & msm-id prop respectively.
+	 * If DTB Version is '3' then we have split DTB with board & msm data & pmic
+	 * populated saperately in board-id & msm-id & pmic-id prop respectively.
 	 * Extract the data & prepare a look up table
 	 */
-	else if (dtb_ver == DEV_TREE_VERSION_V2)
-	{
+	else if (dtb_ver == DEV_TREE_VERSION_V2 || dtb_ver == DEV_TREE_VERSION_V3) {
 		board_data_count = (len_board_id / BOARD_ID_SIZE);
 		msm_data_count = (len_plat_id / PLAT_ID_SIZE);
+		/* If dtb version is v2.0, the pmic_data_count will be <= 0 */
+		pmic_data_count = (len_pmic_id / PMIC_ID_SIZE);
 
-		/* If we are using dtb v2.0, then we have split board & msm data in the DTB */
+		/* If we are using dtb v3.0, then we have split board, msm & pmic data in the DTB
+		*  If we are using dtb v2.0, then we have split board & msmdata in the DTB
+		*/
 		board_data = (struct board_id *) malloc(sizeof(struct board_id) * (len_board_id / BOARD_ID_SIZE));
 		ASSERT(board_data);
 		platform_data = (struct plat_id *) malloc(sizeof(struct plat_id) * (len_plat_id / PLAT_ID_SIZE));
 		ASSERT(platform_data);
+		if (dtb_ver == DEV_TREE_VERSION_V3) {
+			pmic_data = (struct pmic_id *) malloc(sizeof(struct pmic_id) * (len_pmic_id / PMIC_ID_SIZE));
+			ASSERT(pmic_data);
+		}
 		i = 0;
 
 		/* Extract board data from DTB */
-		for(i = 0 ; i < board_data_count; i++)
-		{
+		for(i = 0 ; i < board_data_count; i++) {
 			board_data[i].variant_id = fdt32_to_cpu(((struct board_id *)board_prop)->variant_id);
 			board_data[i].platform_subtype = fdt32_to_cpu(((struct board_id *)board_prop)->platform_subtype);
+			/* For V2/V3 version of DTBs we have platform version field as part
+			 * of variant ID, in such case the subtype will be mentioned as 0x0
+			 * As the qcom, board-id = <0xSSPMPmPH, 0x0>
+			 * SS -- Subtype
+			 * PM -- Platform major version
+			 * Pm -- Platform minor version
+			 * PH -- Platform hardware CDP/MTP
+			 * In such case to make it compatible with LK algorithm move the subtype
+			 * from variant_id to subtype field
+			 */
+			if (board_data[i].platform_subtype == 0)
+				board_data[i].platform_subtype =
+					fdt32_to_cpu(((struct board_id *)board_prop)->variant_id) >> 0x18;
+
 			len_board_id -= sizeof(struct board_id);
 			board_prop += sizeof(struct board_id);
 		}
 
 		/* Extract platform data from DTB */
-		for(i = 0 ; i < msm_data_count; i++)
-		{
+		for(i = 0 ; i < msm_data_count; i++) {
 			platform_data[i].platform_id = fdt32_to_cpu(((struct plat_id *)plat_prop)->platform_id);
 			platform_data[i].soc_rev = fdt32_to_cpu(((struct plat_id *)plat_prop)->soc_rev);
 			len_plat_id -= sizeof(struct plat_id);
 			plat_prop += sizeof(struct plat_id);
 		}
 
-		/* We need to merge board & platform data into dt entry structure */
-		num_entries = msm_data_count * board_data_count;
-		dt_entry_v2 = (struct dt_entry*) malloc(sizeof(struct dt_entry) * num_entries);
-		ASSERT(dt_entry_v2);
+		if (dtb_ver == DEV_TREE_VERSION_V3 && pmic_prop) {
+			/* Extract pmic data from DTB */
+			for(i = 0 ; i < pmic_data_count; i++) {
+				pmic_data[i].pmic_version[0]= fdt32_to_cpu(((struct pmic_id *)pmic_prop)->pmic_version[0]);
+				pmic_data[i].pmic_version[1]= fdt32_to_cpu(((struct pmic_id *)pmic_prop)->pmic_version[1]);
+				pmic_data[i].pmic_version[2]= fdt32_to_cpu(((struct pmic_id *)pmic_prop)->pmic_version[2]);
+				pmic_data[i].pmic_version[3]= fdt32_to_cpu(((struct pmic_id *)pmic_prop)->pmic_version[3]);
+				len_pmic_id -= sizeof(struct pmic_id);
+				pmic_prop += sizeof(struct pmic_id);
+			}
+
+			/* We need to merge board & platform data into dt entry structure */
+			num_entries = msm_data_count * board_data_count * pmic_data_count;
+		} else {
+			/* We need to merge board & platform data into dt entry structure */
+			num_entries = msm_data_count * board_data_count;
+		}
+
+		if ((((uint64_t)msm_data_count * (uint64_t)board_data_count * (uint64_t)pmic_data_count) !=
+			msm_data_count * board_data_count * pmic_data_count) ||
+			(((uint64_t)msm_data_count * (uint64_t)board_data_count) != msm_data_count * board_data_count)) {
+
+			free(board_data);
+			free(platform_data);
+			if (pmic_data)
+				free(pmic_data);
+			if (model)
+				free(model);
+			return false;
+		}
+
+		dt_entry_array = (struct dt_entry*) malloc(sizeof(struct dt_entry) * num_entries);
+		ASSERT(dt_entry_array);
 
 		/* If we have '<X>; <Y>; <Z>' as platform data & '<A>; <B>; <C>' as board data.
 		 * Then dt entry should look like
@@ -209,78 +327,78 @@
 		 */
 		i = 0;
 		k = 0;
-		for (i = 0; i < msm_data_count; i++)
-		{
-			for (j = 0; j < board_data_count; j++)
-			{
-				dt_entry_v2[k].platform_id = platform_data[i].platform_id;
-				dt_entry_v2[k].soc_rev = platform_data[i].soc_rev;
-				dt_entry_v2[k].variant_id = board_data[j].variant_id;
-				dt_entry_v2[k].board_hw_subtype = board_data[j].platform_subtype;
-				k++;
+		n = 0;
+		for (i = 0; i < msm_data_count; i++) {
+			for (j = 0; j < board_data_count; j++) {
+				if (dtb_ver == DEV_TREE_VERSION_V3 && pmic_prop) {
+					for (n = 0; n < pmic_data_count; n++) {
+						dt_entry_array[k].platform_id = platform_data[i].platform_id;
+						dt_entry_array[k].soc_rev = platform_data[i].soc_rev;
+						dt_entry_array[k].variant_id = board_data[j].variant_id;
+						dt_entry_array[k].board_hw_subtype = board_data[j].platform_subtype;
+						dt_entry_array[k].pmic_rev[0]= pmic_data[n].pmic_version[0];
+						dt_entry_array[k].pmic_rev[1]= pmic_data[n].pmic_version[1];
+						dt_entry_array[k].pmic_rev[2]= pmic_data[n].pmic_version[2];
+						dt_entry_array[k].pmic_rev[3]= pmic_data[n].pmic_version[3];
+						dt_entry_array[k].offset = (uint32_t)dtb;
+						dt_entry_array[k].size = dtb_size;
+						k++;
+					}
+
+				} else {
+					dt_entry_array[k].platform_id = platform_data[i].platform_id;
+					dt_entry_array[k].soc_rev = platform_data[i].soc_rev;
+					dt_entry_array[k].variant_id = board_data[j].variant_id;
+					dt_entry_array[k].board_hw_subtype = board_data[j].platform_subtype;
+					dt_entry_array[k].pmic_rev[0]= board_pmic_target(0);
+					dt_entry_array[k].pmic_rev[1]= board_pmic_target(1);
+					dt_entry_array[k].pmic_rev[2]= board_pmic_target(2);
+					dt_entry_array[k].pmic_rev[3]= board_pmic_target(3);
+					dt_entry_array[k].offset = (uint32_t)dtb;
+					dt_entry_array[k].size = dtb_size;
+					k++;
+				}
 			}
 		}
 
-		/* Now find the matching entry in the merged list */
-		if (board_hardware_id() == HW_PLATFORM_QRD)
-			target_variant_id = board_target_id();
-		else
-			target_variant_id = board_hardware_id() | ((board_hardware_subtype() & 0xff) << 24);
-
-		for (i=0 ;i < num_entries; i++)
-		{
+		for (i=0 ;i < num_entries; i++) {
 			dprintf(SPEW, "Found an appended flattened device tree (%s - %u %u %u 0x%x)\n",
 				*model ? model : "unknown",
-				dt_entry_v2[i].platform_id, dt_entry_v2[i].variant_id, dt_entry_v2[i].board_hw_subtype, dt_entry_v2[i].soc_rev);
+				dt_entry_array[i].platform_id, dt_entry_array[i].variant_id, dt_entry_array[i].board_hw_subtype, dt_entry_array[i].soc_rev);
 
-			if (platform_dt_match(&dt_entry_v2[i], target_variant_id, 0xff) == 1)
-			{
+			if (platform_dt_absolute_match(&(dt_entry_array[i]), dtb_list)) {
+				dprintf(SPEW, "Device tree exact match the board: <%u %u %u 0x%x> == <%u %u %u 0x%x>\n",
+					dt_entry_array[i].platform_id,
+					dt_entry_array[i].variant_id,
+					dt_entry_array[i].soc_rev,
+					dt_entry_array[i].board_hw_subtype,
+					board_platform_id(),
+					board_hardware_id(),
+					board_hardware_subtype(),
+					board_soc_version());
+
+			} else {
 				dprintf(SPEW, "Device tree's msm_id doesn't match the board: <%u %u %u 0x%x> != <%u %u %u 0x%x>\n",
-							  dt_entry_v2[i].platform_id,
-							  dt_entry_v2[i].variant_id,
-							  dt_entry_v2[i].soc_rev,
-							  dt_entry_v2[i].board_hw_subtype,
-							  board_platform_id(),
-							  board_hardware_id(),
-							  board_hardware_subtype(),
-							  board_soc_version());
-				continue;
-			}
-			else
-			{
-				/* If found a match, return the cur_dt_entry */
-				found = 1;
-				cur_dt_entry = dt_entry_v2[i];
-				break;
+					dt_entry_array[i].platform_id,
+					dt_entry_array[i].variant_id,
+					dt_entry_array[i].soc_rev,
+					dt_entry_array[i].board_hw_subtype,
+					board_platform_id(),
+					board_hardware_id(),
+					board_hardware_subtype(),
+					board_soc_version());
 			}
 		}
+
+		free(board_data);
+		free(platform_data);
+		if (pmic_data)
+			free(pmic_data);
+		free(dt_entry_array);
 	}
-
-	if (!found)
-	{
-		soc_rev =  INVALID_SOC_REV_ID;
-		goto end;
-	}
-	else
-		soc_rev = cur_dt_entry.soc_rev;
-
-	dprintf(INFO, "Device tree's msm_id matches the board: <%u %u %u 0x%x> == <%u %u %u 0x%x>\n",
-		cur_dt_entry.platform_id,
-		cur_dt_entry.variant_id,
-		cur_dt_entry.board_hw_subtype,
-		cur_dt_entry.soc_rev,
-		board_platform_id(),
-		board_hardware_id(),
-		board_hardware_subtype(),
-		board_soc_version());
-
-end:
-	free(board_data);
-	free(platform_data);
-	free(dt_entry_v2);
-	free(model);
-
-	return soc_rev;
+	if (model)
+		free(model);
+	return true;
 }
 
 /*
@@ -298,16 +416,33 @@
 {
 	void *kernel_end = kernel + kernel_size;
 	uint32_t app_dtb_offset = 0;
-	void *dtb;
+	void *dtb = NULL;
 	void *bestmatch_tag = NULL;
+	struct dt_entry *best_match_dt_entry = NULL;
 	uint32_t bestmatch_tag_size;
-	uint32_t bestmatch_soc_rev_id = INVALID_SOC_REV_ID;
+	struct dt_entry_node *dt_entry_queue = NULL;
+	struct dt_entry_node *dt_node_tmp1 = NULL;
+	struct dt_entry_node *dt_node_tmp2 = NULL;
+
+
+	/* Initialize the dtb entry node*/
+	dt_entry_queue = (struct dt_entry_node *)
+				malloc(sizeof(struct dt_entry_node));
+
+	if (!dt_entry_queue) {
+		dprintf(CRITICAL, "Out of memory\n");
+		return NULL;
+	}
+	list_initialize(&dt_entry_queue->node);
+
 
 	memcpy((void*) &app_dtb_offset, (void*) (kernel + DTB_OFFSET), sizeof(uint32_t));
 
+	if (((uintptr_t)kernel + (uintptr_t)app_dtb_offset) < (uintptr_t)kernel) {
+		return NULL;
+	}
 	dtb = kernel + app_dtb_offset;
-	while (dtb + sizeof(struct fdt_header) < kernel_end) {
-		uint32_t dtb_soc_rev_id;
+	while (((uintptr_t)dtb + sizeof(struct fdt_header)) < (uintptr_t)kernel_end) {
 		struct fdt_header dtb_hdr;
 		uint32_t dtb_size;
 
@@ -315,7 +450,8 @@
 		 * and operate on it separately */
 		memcpy(&dtb_hdr, dtb, sizeof(struct fdt_header));
 		if (fdt_check_header((const void *)&dtb_hdr) != 0 ||
-		    (dtb + fdt_totalsize((const void *)&dtb_hdr) > kernel_end))
+		    ((uintptr_t)dtb + (uintptr_t)fdt_totalsize((const void *)&dtb_hdr) < (uintptr_t)dtb) ||
+			((uintptr_t)dtb + (uintptr_t)fdt_totalsize((const void *)&dtb_hdr) > (uintptr_t)kernel_end))
 			break;
 		dtb_size = fdt_totalsize(&dtb_hdr);
 
@@ -324,34 +460,36 @@
 			return NULL;
 		}
 
-		/* now that we know we have a valid DTB, we need to copy
-		 * it somewhere aligned, like tags */
-		memcpy(tags, dtb, dtb_size);
-
-		dtb_soc_rev_id = dev_tree_compatible(tags);
-		if (dtb_soc_rev_id == board_soc_version()) {
-			/* clear out the old DTB magic so kernel doesn't find it */
-			*((uint32_t *)(kernel + app_dtb_offset)) = 0;
-			return tags;
-		} else if ((dtb_soc_rev_id != INVALID_SOC_REV_ID) &&
-				   (dtb_soc_rev_id < board_soc_version())) {
-			/* if current bestmatch is less than new dtb_soc_rev_id then update
-			   bestmatch_tag */
-			if((bestmatch_soc_rev_id == INVALID_SOC_REV_ID) ||
-			   (bestmatch_soc_rev_id < dtb_soc_rev_id)) {
-				bestmatch_tag = dtb;
-				bestmatch_tag_size = dtb_size;
-				bestmatch_soc_rev_id = dtb_soc_rev_id;
-			}
-		}
+		dev_tree_compatible(dtb, dtb_size, dt_entry_queue);
 
 		/* goto the next device tree if any */
 		dtb += dtb_size;
 	}
 
+	best_match_dt_entry = platform_dt_match_best(dt_entry_queue);
+	if (best_match_dt_entry){
+		bestmatch_tag = (void *)best_match_dt_entry->offset;
+		bestmatch_tag_size = best_match_dt_entry->size;
+		dprintf(INFO, "Best match DTB tags %u/%08x/0x%08x/%x/%x/%x/%x/%x/%x/%x\n",
+			best_match_dt_entry->platform_id, best_match_dt_entry->variant_id,
+			best_match_dt_entry->board_hw_subtype, best_match_dt_entry->soc_rev,
+			best_match_dt_entry->pmic_rev[0], best_match_dt_entry->pmic_rev[1],
+			best_match_dt_entry->pmic_rev[2], best_match_dt_entry->pmic_rev[3],
+			best_match_dt_entry->offset, best_match_dt_entry->size);
+		dprintf(INFO, "Using pmic info 0x%0x/0x%x/0x%x/0x%0x for device 0x%0x/0x%x/0x%x/0x%0x\n",
+			best_match_dt_entry->pmic_rev[0], best_match_dt_entry->pmic_rev[1],
+			best_match_dt_entry->pmic_rev[2], best_match_dt_entry->pmic_rev[3],
+			board_pmic_target(0), board_pmic_target(1),
+			board_pmic_target(2), board_pmic_target(3));
+	}
+	/* free queue's memory */
+	list_for_every_entry(&dt_entry_queue->node, dt_node_tmp1, dt_node, node) {
+		dt_node_tmp2 = dt_node_tmp1->node.prev;
+		dt_entry_list_delete(dt_node_tmp1);
+		dt_node_tmp1 = dt_node_tmp2;
+	}
+
 	if(bestmatch_tag) {
-		dprintf(INFO,"DTB found with bestmatch soc rev id 0x%x.Board soc rev id 0x%x\n",
-				bestmatch_soc_rev_id, board_soc_version());
 		memcpy(tags, bestmatch_tag, bestmatch_tag_size);
 		/* clear out the old DTB magic so kernel doesn't find it */
 		*((uint32_t *)(kernel + app_dtb_offset)) = 0;
@@ -378,6 +516,8 @@
 	if (table->version == DEV_TREE_VERSION_V1) {
 		dt_entry_size = sizeof(struct dt_entry_v1);
 	} else if (table->version == DEV_TREE_VERSION_V2) {
+		dt_entry_size = sizeof(struct dt_entry_v2);
+	} else if (table->version == DEV_TREE_VERSION_V3) {
 		dt_entry_size = sizeof(struct dt_entry);
 	} else {
 		dprintf(CRITICAL, "ERROR: Unsupported version (%d) in DT table \n",
@@ -398,65 +538,350 @@
 	return 0;
 }
 
-static int platform_dt_match(struct dt_entry *cur_dt_entry, uint32_t target_variant_id, uint32_t subtype_mask)
+static int platform_dt_absolute_match(struct dt_entry *cur_dt_entry, struct dt_entry_node *dt_list)
 {
-	/*
-	 * 1. Check if cur_dt_entry has platform_hw_version major & minor present?
-	 * 2. If present, calculate cur_dt_target_id for the current platform as:
-	 * 3. bit no |31  24 | 23   16| 15   8 |7         0|
-	 * 4.        |subtype| major  | minor  |hw_platform|
-	 */
-	uint32_t cur_dt_target_id ;
 	uint32_t cur_dt_hlos_subtype;
+	uint32_t cur_dt_hw_platform;
+	uint32_t cur_dt_hw_subtype;
+	uint32_t cur_dt_msm_id;
+	dt_node *dt_node_tmp = NULL;
 
-	/*
-	 * if variant_id has platform_hw_ver has major = 0xff and minor = 0xff,
-	 * ignore the major & minor versions from the DTB entry
-	 */
-	if ((cur_dt_entry->variant_id & 0xffff00) == 0xffff00)
-		cur_dt_target_id  = (cur_dt_entry->variant_id & 0xff0000ff) | (target_variant_id & 0xffff00);
-	/*
-	 * We have a valid platform_hw_version major & minor numbers in the board-id, so
-	 * use the board-id from the DTB.
-	 * Note: For some QRD platforms the format used is qcom, board-id = <0xMVmVPT 0xPS>
-	 * where: MV: platform major ver, mV: platform minor ver, PT: platform type
-	 * PS: platform subtype, so we need to put PS @ bit 24-31 to be backward compatible.
-	 */
-	else
-		cur_dt_target_id = cur_dt_entry->variant_id | ((cur_dt_entry->board_hw_subtype & subtype_mask & 0xff) << 24);
+	/* Platform-id
+	* bit no |31	 24|23	16|15	0|
+	*        |reserved|foundry-id|msm-id|
+	*/
+	cur_dt_msm_id = (cur_dt_entry->platform_id & 0x0000ffff);
+	cur_dt_hw_platform = (cur_dt_entry->variant_id & 0x000000ff);
+	cur_dt_hw_subtype = (cur_dt_entry->board_hw_subtype);
+
+
 	/* Determine the bits 23:8 to check the DT with the DDR Size */
 	cur_dt_hlos_subtype = (cur_dt_entry->board_hw_subtype & 0xffff00);
 
-	/* 1. must match the platform_id, platform_hw_id, platform_version
-	*  2. soc rev number equal then return 0
-	*  3. dt soc rev number less than cdt return -1
-	*  4. otherwise return 1
+	/* 1. must match the msm_id, platform_hw_id, platform_subtype and DDR size
+	*  soc, board major/minor, pmic major/minor must less than board info
+	*  2. find the matched DTB then return 1
+	*  3. otherwise return 0
 	*/
+	if((cur_dt_msm_id == (board_platform_id() & 0x0000ffff)) &&
+		(cur_dt_hw_platform == board_hardware_id()) &&
+		(cur_dt_hw_subtype == board_hardware_subtype()) &&
+		(cur_dt_hlos_subtype == target_get_hlos_subtype()) &&
+		(cur_dt_entry->soc_rev <= board_soc_version()) &&
+		((cur_dt_entry->variant_id & 0x00ffff00) <= (board_target_id() & 0x00ffff00)) &&
+		((cur_dt_entry->pmic_rev[0] & 0x00ffff00) <= (board_pmic_target(0) & 0x00ffff00)) &&
+		((cur_dt_entry->pmic_rev[1] & 0x00ffff00) <= (board_pmic_target(1) & 0x00ffff00)) &&
+		((cur_dt_entry->pmic_rev[2] & 0x00ffff00) <= (board_pmic_target(2) & 0x00ffff00)) &&
+		((cur_dt_entry->pmic_rev[3] & 0x00ffff00) <= (board_pmic_target(3) & 0x00ffff00))) {
 
-	if((cur_dt_entry->platform_id == board_platform_id()) &&
-		(cur_dt_target_id == target_variant_id) &&
-		(cur_dt_hlos_subtype == target_get_hlos_subtype())) {
+		dt_node_tmp = dt_entry_list_init();
+		memcpy((char*)dt_node_tmp->dt_entry_m,(char*)cur_dt_entry, sizeof(struct dt_entry));
 
-		if(cur_dt_entry->soc_rev == board_soc_version()) {
+		dprintf(SPEW, "Add DTB entry %u/%08x/0x%08x/%x/%x/%x/%x/%x/%x/%x\n",
+			dt_node_tmp->dt_entry_m->platform_id, dt_node_tmp->dt_entry_m->variant_id,
+			dt_node_tmp->dt_entry_m->board_hw_subtype, dt_node_tmp->dt_entry_m->soc_rev,
+			dt_node_tmp->dt_entry_m->pmic_rev[0], dt_node_tmp->dt_entry_m->pmic_rev[1],
+			dt_node_tmp->dt_entry_m->pmic_rev[2], dt_node_tmp->dt_entry_m->pmic_rev[3],
+			dt_node_tmp->dt_entry_m->offset, dt_node_tmp->dt_entry_m->size);
+
+		insert_dt_entry_in_queue(dt_list, dt_node_tmp);
+		return 1;
+	}
+	return 0;
+}
+
+static int platform_dt_absolute_compat_match(struct dt_entry_node *dt_list, uint32_t dtb_info) {
+	struct dt_entry_node *dt_node_tmp1 = NULL;
+	struct dt_entry_node *dt_node_tmp2 = NULL;
+	uint32_t current_info = 0;
+	uint32_t board_info = 0;
+	uint32_t best_info = 0;
+	uint32_t current_pmic_model[4] = {0, 0, 0, 0};
+	uint32_t board_pmic_model[4] = {0, 0, 0, 0};
+	uint32_t best_pmic_model[4] = {0, 0, 0, 0};
+	uint32_t delete_current_dt = 0;
+	uint32_t i;
+
+	/* start to select the exact entry
+	* default to exact match 0, if find current DTB entry info is the same as board info,
+	* then exact match board info.
+	*/
+	list_for_every_entry(&dt_list->node, dt_node_tmp1, dt_node, node) {
+		if (!dt_node_tmp1){
+			dprintf(SPEW, "Current node is the end\n");
+			break;
+		}
+		switch(dtb_info) {
+		case DTB_FOUNDRY:
+			current_info = ((dt_node_tmp1->dt_entry_m->platform_id) & 0x00ff0000);
+			board_info = board_foundry_id();
+			break;
+		case DTB_PMIC_MODEL:
+			for (i = 0; i < 4; i++) {
+				current_pmic_model[i] = (dt_node_tmp1->dt_entry_m->pmic_rev[i] & 0xff);
+				board_pmic_model[i] = (board_pmic_target(i) & 0xff);
+			}
+			break;
+		default:
+			dprintf(CRITICAL, "ERROR: Unsupported version (%d) in dt node check \n",
+					dtb_info);
 			return 0;
-		} else if(cur_dt_entry->soc_rev < board_soc_version()) {
-			return -1;
+		}
+
+		if (dtb_info == DTB_PMIC_MODEL) {
+			if ((current_pmic_model[0] == board_pmic_model[0]) &&
+				(current_pmic_model[1] == board_pmic_model[1]) &&
+				(current_pmic_model[2] == board_pmic_model[2]) &&
+				(current_pmic_model[3] == board_pmic_model[3])) {
+
+				for (i = 0; i < 4; i++) {
+					best_pmic_model[i] = current_pmic_model[i];
+				}
+				break;
+			}
+		} else {
+			if (current_info == board_info) {
+				best_info = current_info;
+				break;
+			}
+		}
+	}
+
+	list_for_every_entry(&dt_list->node, dt_node_tmp1, dt_node, node) {
+		if (!dt_node_tmp1){
+			dprintf(SPEW, "Current node is the end\n");
+			break;
+		}
+		switch(dtb_info) {
+		case DTB_FOUNDRY:
+			current_info = ((dt_node_tmp1->dt_entry_m->platform_id) & 0x00ff0000);
+			break;
+		case DTB_PMIC_MODEL:
+			for (i = 0; i < 4; i++) {
+				current_pmic_model[i] = (dt_node_tmp1->dt_entry_m->pmic_rev[i] & 0xff);
+			}
+			break;
+		default:
+			dprintf(CRITICAL, "ERROR: Unsupported version (%d) in dt node check \n",
+					dtb_info);
+			return 0;
+		}
+
+		if (dtb_info == DTB_PMIC_MODEL) {
+			if ((current_pmic_model[0] != best_pmic_model[0]) ||
+				(current_pmic_model[1] != best_pmic_model[1]) ||
+				(current_pmic_model[2] != best_pmic_model[2]) ||
+				(current_pmic_model[3] != best_pmic_model[3])) {
+
+				delete_current_dt = 1;
+			}
+		} else {
+			if (current_info != best_info) {
+				delete_current_dt = 1;
+			}
+		}
+
+		if (delete_current_dt) {
+			dprintf(SPEW, "Delete don't fit DTB entry %u/%08x/0x%08x/%x/%x/%x/%x/%x/%x/%x\n",
+				dt_node_tmp1->dt_entry_m->platform_id, dt_node_tmp1->dt_entry_m->variant_id,
+				dt_node_tmp1->dt_entry_m->board_hw_subtype, dt_node_tmp1->dt_entry_m->soc_rev,
+				dt_node_tmp1->dt_entry_m->pmic_rev[0], dt_node_tmp1->dt_entry_m->pmic_rev[1],
+				dt_node_tmp1->dt_entry_m->pmic_rev[2], dt_node_tmp1->dt_entry_m->pmic_rev[3],
+				dt_node_tmp1->dt_entry_m->offset, dt_node_tmp1->dt_entry_m->size);
+
+			dt_node_tmp2 = dt_node_tmp1->node.prev;
+			dt_entry_list_delete(dt_node_tmp1);
+			dt_node_tmp1 = dt_node_tmp2;
+			delete_current_dt = 0;
 		}
 	}
 
 	return 1;
 }
 
-static int __dev_tree_get_entry_info(struct dt_table *table, struct dt_entry *dt_entry_info,
-										uint32_t target_variant_id, uint32_t subtype_mask)
+static int update_dtb_entry_node(struct dt_entry_node *dt_list, uint32_t dtb_info) {
+	struct dt_entry_node *dt_node_tmp1 = NULL;
+	struct dt_entry_node *dt_node_tmp2 = NULL;
+	uint32_t current_info = 0;
+	uint32_t board_info = 0;
+	uint32_t best_info = 0;
+
+	/* start to select the best entry*/
+	list_for_every_entry(&dt_list->node, dt_node_tmp1, dt_node, node) {
+		if (!dt_node_tmp1){
+			dprintf(SPEW, "Current node is the end\n");
+			break;
+		}
+		switch(dtb_info) {
+		case DTB_SOC:
+			current_info = dt_node_tmp1->dt_entry_m->soc_rev;
+			board_info = board_soc_version();
+			break;
+		case DTB_MAJOR_MINOR:
+			current_info = ((dt_node_tmp1->dt_entry_m->variant_id) & 0x00ffff00);
+			board_info = (board_target_id() & 0x00ffff00);
+			break;
+		case DTB_PMIC0:
+			current_info = ((dt_node_tmp1->dt_entry_m->pmic_rev[0]) & 0x00ffff00);
+			board_info = (board_pmic_target(0) & 0x00ffff00);
+			break;
+		case DTB_PMIC1:
+			current_info = ((dt_node_tmp1->dt_entry_m->pmic_rev[1]) & 0x00ffff00);
+			board_info = (board_pmic_target(1) & 0x00ffff00);
+			break;
+		case DTB_PMIC2:
+			current_info = ((dt_node_tmp1->dt_entry_m->pmic_rev[2]) & 0x00ffff00);
+			board_info = (board_pmic_target(2) & 0x00ffff00);
+			break;
+		case DTB_PMIC3:
+			current_info = ((dt_node_tmp1->dt_entry_m->pmic_rev[3]) & 0x00ffff00);
+			board_info = (board_pmic_target(3) & 0x00ffff00);
+			break;
+		default:
+			dprintf(CRITICAL, "ERROR: Unsupported version (%d) in dt node check \n",
+					dtb_info);
+			return 0;
+		}
+
+		if (current_info == board_info) {
+			best_info = current_info;
+			break;
+		}
+		if ((current_info < board_info) && (current_info > best_info)) {
+			best_info = current_info;
+		}
+		if (current_info < best_info) {
+			dprintf(SPEW, "Delete don't fit DTB entry %u/%08x/0x%08x/%x/%x/%x/%x/%x/%x/%x\n",
+				dt_node_tmp1->dt_entry_m->platform_id, dt_node_tmp1->dt_entry_m->variant_id,
+				dt_node_tmp1->dt_entry_m->board_hw_subtype, dt_node_tmp1->dt_entry_m->soc_rev,
+				dt_node_tmp1->dt_entry_m->pmic_rev[0], dt_node_tmp1->dt_entry_m->pmic_rev[1],
+				dt_node_tmp1->dt_entry_m->pmic_rev[2], dt_node_tmp1->dt_entry_m->pmic_rev[3],
+				dt_node_tmp1->dt_entry_m->offset, dt_node_tmp1->dt_entry_m->size);
+
+			dt_node_tmp2 = dt_node_tmp1->node.prev;
+			dt_entry_list_delete(dt_node_tmp1);
+			dt_node_tmp1 = dt_node_tmp2;
+		}
+	}
+
+	list_for_every_entry(&dt_list->node, dt_node_tmp1, dt_node, node) {
+		if (!dt_node_tmp1){
+			dprintf(SPEW, "Current node is the end\n");
+			break;
+		}
+		switch(dtb_info) {
+		case DTB_SOC:
+			current_info = dt_node_tmp1->dt_entry_m->soc_rev;
+			break;
+		case DTB_MAJOR_MINOR:
+			current_info = ((dt_node_tmp1->dt_entry_m->variant_id) & 0x00ffff00);
+			break;
+		case DTB_PMIC0:
+			current_info = ((dt_node_tmp1->dt_entry_m->pmic_rev[0]) & 0x00ffff00);
+			break;
+		case DTB_PMIC1:
+			current_info = ((dt_node_tmp1->dt_entry_m->pmic_rev[1]) & 0x00ffff00);
+			break;
+		case DTB_PMIC2:
+			current_info = ((dt_node_tmp1->dt_entry_m->pmic_rev[2]) & 0x00ffff00);
+			break;
+		case DTB_PMIC3:
+			current_info = ((dt_node_tmp1->dt_entry_m->pmic_rev[3]) & 0x00ffff00);
+			break;
+		default:
+			dprintf(CRITICAL, "ERROR: Unsupported version (%d) in dt node check \n",
+					dtb_info);
+			return 0;
+		}
+
+		if (current_info != best_info) {
+			dprintf(SPEW, "Delete don't fit DTB entry %u/%08x/0x%08x/%x/%x/%x/%x/%x/%x/%x\n",
+				dt_node_tmp1->dt_entry_m->platform_id, dt_node_tmp1->dt_entry_m->variant_id,
+				dt_node_tmp1->dt_entry_m->board_hw_subtype, dt_node_tmp1->dt_entry_m->soc_rev,
+				dt_node_tmp1->dt_entry_m->pmic_rev[0], dt_node_tmp1->dt_entry_m->pmic_rev[1],
+				dt_node_tmp1->dt_entry_m->pmic_rev[2], dt_node_tmp1->dt_entry_m->pmic_rev[3],
+				dt_node_tmp1->dt_entry_m->offset, dt_node_tmp1->dt_entry_m->size);
+
+			dt_node_tmp2 = dt_node_tmp1->node.prev;
+			dt_entry_list_delete(dt_node_tmp1);
+			dt_node_tmp1 = dt_node_tmp2;
+		}
+	}
+	return 1;
+}
+
+static struct dt_entry *platform_dt_match_best(struct dt_entry_node *dt_list)
+{
+	struct dt_entry_node *dt_node_tmp1 = NULL;
+
+	/* check Foundry id
+	* the foundry id must exact match board founddry id, this is compatibility check,
+	* if couldn't find the exact match from DTB, will exact match 0x0.
+	*/
+	if (!platform_dt_absolute_compat_match(dt_list, DTB_FOUNDRY))
+		return NULL;
+
+	/* check PMIC model
+	* the PMIC model must exact match board PMIC model, this is compatibility check,
+	* if couldn't find the exact match from DTB, will exact match 0x0.
+	*/
+	if (!platform_dt_absolute_compat_match(dt_list, DTB_PMIC_MODEL))
+		return NULL;
+
+	/* check soc version
+	* the suitable soc version must less than or equal to board soc version
+	*/
+	if (!update_dtb_entry_node(dt_list, DTB_SOC))
+		return NULL;
+
+	/*check major and minor version
+	* the suitable major&minor version must less than or equal to board major&minor version
+	*/
+	if (!update_dtb_entry_node(dt_list, DTB_MAJOR_MINOR))
+		return NULL;
+
+	/*check pmic info
+	* the suitable pmic major&minor info must less than or equal to board pmic major&minor version
+	*/
+	if (!update_dtb_entry_node(dt_list, DTB_PMIC0))
+		return NULL;
+	if (!update_dtb_entry_node(dt_list, DTB_PMIC1))
+		return NULL;
+	if (!update_dtb_entry_node(dt_list, DTB_PMIC2))
+		return NULL;
+	if (!update_dtb_entry_node(dt_list, DTB_PMIC3))
+		return NULL;
+
+	list_for_every_entry(&dt_list->node, dt_node_tmp1, dt_node, node) {
+		if (!dt_node_tmp1) {
+			dprintf(CRITICAL, "ERROR: Couldn't find the suitable DTB!\n");
+			return NULL;
+		}
+		if (dt_node_tmp1->dt_entry_m)
+			return dt_node_tmp1->dt_entry_m;
+	}
+
+	return NULL;
+}
+
+/* Function to obtain the index information for the correct device tree
+ *  based on the platform data.
+ *  If a matching device tree is found, the information is returned in the
+ *  "dt_entry_info" out parameter and a function value of 0 is returned, otherwise
+ *  a non-zero function value is returned.
+ */
+int dev_tree_get_entry_info(struct dt_table *table, struct dt_entry *dt_entry_info)
 {
 	uint32_t i;
-	unsigned char *table_ptr;
+	unsigned char *table_ptr = NULL;
 	struct dt_entry dt_entry_buf_1;
-	struct dt_entry dt_entry_buf_2;
-	struct dt_entry *cur_dt_entry;
-	struct dt_entry *best_match_dt_entry;
-	struct dt_entry_v1 *dt_entry_v1;
+	struct dt_entry *cur_dt_entry = NULL;
+	struct dt_entry *best_match_dt_entry = NULL;
+	struct dt_entry_v1 *dt_entry_v1 = NULL;
+	struct dt_entry_v2 *dt_entry_v2 = NULL;
+	struct dt_entry_node *dt_entry_queue = NULL;
+	struct dt_entry_node *dt_node_tmp1 = NULL;
+	struct dt_entry_node *dt_node_tmp2 = NULL;
 	uint32_t found = 0;
 
 	if (!dt_entry_info) {
@@ -468,7 +893,16 @@
 	table_ptr = (unsigned char *)table + DEV_TREE_HEADER_SIZE;
 	cur_dt_entry = &dt_entry_buf_1;
 	best_match_dt_entry = NULL;
+	dt_entry_queue = (struct dt_entry_node *)
+				malloc(sizeof(struct dt_entry_node));
 
+	if (!dt_entry_queue) {
+		dprintf(CRITICAL, "Out of memory\n");
+		return -1;
+	}
+
+	list_initialize(&dt_entry_queue->node);
+	dprintf(INFO, "DTB Total entry: %d, DTB version: %d\n", table->num_entries, table->version);
 	for(i = 0; found == 0 && i < table->num_entries; i++)
 	{
 		memset(cur_dt_entry, 0, sizeof(struct dt_entry));
@@ -478,99 +912,114 @@
 			cur_dt_entry->platform_id = dt_entry_v1->platform_id;
 			cur_dt_entry->variant_id = dt_entry_v1->variant_id;
 			cur_dt_entry->soc_rev = dt_entry_v1->soc_rev;
-			cur_dt_entry->board_hw_subtype = board_hardware_subtype();
+			cur_dt_entry->board_hw_subtype = (dt_entry_v1->variant_id >> 0x18);
+			cur_dt_entry->pmic_rev[0] = board_pmic_target(0);
+			cur_dt_entry->pmic_rev[1] = board_pmic_target(1);
+			cur_dt_entry->pmic_rev[2] = board_pmic_target(2);
+			cur_dt_entry->pmic_rev[3] = board_pmic_target(3);
 			cur_dt_entry->offset = dt_entry_v1->offset;
 			cur_dt_entry->size = dt_entry_v1->size;
 			table_ptr += sizeof(struct dt_entry_v1);
 			break;
 		case DEV_TREE_VERSION_V2:
+			dt_entry_v2 = (struct dt_entry_v2*)table_ptr;
+			cur_dt_entry->platform_id = dt_entry_v2->platform_id;
+			cur_dt_entry->variant_id = dt_entry_v2->variant_id;
+			cur_dt_entry->soc_rev = dt_entry_v2->soc_rev;
+			/* For V2 version of DTBs we have platform version field as part
+			 * of variant ID, in such case the subtype will be mentioned as 0x0
+			 * As the qcom, board-id = <0xSSPMPmPH, 0x0>
+			 * SS -- Subtype
+			 * PM -- Platform major version
+			 * Pm -- Platform minor version
+			 * PH -- Platform hardware CDP/MTP
+			 * In such case to make it compatible with LK algorithm move the subtype
+			 * from variant_id to subtype field
+			 */
+			if (dt_entry_v2->board_hw_subtype == 0)
+				cur_dt_entry->board_hw_subtype = (cur_dt_entry->variant_id >> 0x18);
+			else
+				cur_dt_entry->board_hw_subtype = dt_entry_v2->board_hw_subtype;
+			cur_dt_entry->pmic_rev[0] = board_pmic_target(0);
+			cur_dt_entry->pmic_rev[1] = board_pmic_target(1);
+			cur_dt_entry->pmic_rev[2] = board_pmic_target(2);
+			cur_dt_entry->pmic_rev[3] = board_pmic_target(3);
+			cur_dt_entry->offset = dt_entry_v2->offset;
+			cur_dt_entry->size = dt_entry_v2->size;
+			table_ptr += sizeof(struct dt_entry_v2);
+			break;
+		case DEV_TREE_VERSION_V3:
 			memcpy(cur_dt_entry, (struct dt_entry *)table_ptr,
 				   sizeof(struct dt_entry));
+			/* For V3 version of DTBs we have platform version field as part
+			 * of variant ID, in such case the subtype will be mentioned as 0x0
+			 * As the qcom, board-id = <0xSSPMPmPH, 0x0>
+			 * SS -- Subtype
+			 * PM -- Platform major version
+			 * Pm -- Platform minor version
+			 * PH -- Platform hardware CDP/MTP
+			 * In such case to make it compatible with LK algorithm move the subtype
+			 * from variant_id to subtype field
+			 */
+			if (cur_dt_entry->board_hw_subtype == 0)
+				cur_dt_entry->board_hw_subtype = (cur_dt_entry->variant_id >> 0x18);
+
 			table_ptr += sizeof(struct dt_entry);
 			break;
 		default:
 			dprintf(CRITICAL, "ERROR: Unsupported version (%d) in DT table \n",
 					table->version);
+			free(dt_entry_queue);
 			return -1;
 		}
 
-		/* DTBs are stored in the ascending order of soc revision.
-		 * For eg: Rev0..Rev1..Rev2 & so on.
-		 * we pickup the DTB with highest soc rev number which is less
-		 * than or equal to actual hardware
-		 */
-		switch(platform_dt_match(cur_dt_entry, target_variant_id, subtype_mask)) {
-		case 0:
-			best_match_dt_entry = cur_dt_entry;
-			found = 1;
-			break;
-		case -1:
-			if (!best_match_dt_entry) {
-				/* copy structure */
-				best_match_dt_entry = cur_dt_entry;
-				cur_dt_entry = &dt_entry_buf_2;
-			} else {
-				/* Swap dt_entry buffers */
-				struct dt_entry *temp = cur_dt_entry;
-				cur_dt_entry = best_match_dt_entry;
-				best_match_dt_entry = temp;
-			}
-		default:
-			break;
-		}
-	}
+		/* DTBs must match the platform_id, platform_hw_id, platform_subtype and DDR size.
+		* The satisfactory DTBs are stored in dt_entry_queue
+		*/
+		platform_dt_absolute_match(cur_dt_entry, dt_entry_queue);
 
+	}
+	best_match_dt_entry = platform_dt_match_best(dt_entry_queue);
 	if (best_match_dt_entry) {
 		*dt_entry_info = *best_match_dt_entry;
 		found = 1;
 	}
 
 	if (found != 0) {
-		dprintf(INFO, "Using DTB entry %u/%08x/0x%08x/%u for device %u/%08x/0x%08x/%u\n",
+		dprintf(INFO, "Using DTB entry 0x%08x/%08x/0x%08x/%u for device 0x%08x/%08x/0x%08x/%u\n",
 				dt_entry_info->platform_id, dt_entry_info->soc_rev,
 				dt_entry_info->variant_id, dt_entry_info->board_hw_subtype,
 				board_platform_id(), board_soc_version(),
 				board_target_id(), board_hardware_subtype());
+		if (dt_entry_info->pmic_rev[0] == 0 && dt_entry_info->pmic_rev[0] == 0 &&
+			dt_entry_info->pmic_rev[0] == 0 && dt_entry_info->pmic_rev[0] == 0) {
+			dprintf(SPEW, "No maintain pmic info in DTB, device pmic info is 0x%0x/0x%x/0x%x/0x%0x\n",
+					board_pmic_target(0), board_pmic_target(1),
+					board_pmic_target(2), board_pmic_target(3));
+		} else {
+			dprintf(INFO, "Using pmic info 0x%0x/0x%x/0x%x/0x%0x for device 0x%0x/0x%x/0x%x/0x%0x\n",
+					dt_entry_info->pmic_rev[0], dt_entry_info->pmic_rev[1],
+					dt_entry_info->pmic_rev[2], dt_entry_info->pmic_rev[3],
+					board_pmic_target(0), board_pmic_target(1),
+					board_pmic_target(2), board_pmic_target(3));
+		}
 		return 0;
 	}
 
 	dprintf(CRITICAL, "ERROR: Unable to find suitable device tree for device (%u/0x%08x/0x%08x/%u)\n",
 			board_platform_id(), board_soc_version(),
 			board_target_id(), board_hardware_subtype());
+
+	list_for_every_entry(&dt_entry_queue->node, dt_node_tmp1, dt_node, node) {
+		/* free node memory */
+		dt_node_tmp2 = dt_node_tmp1->node.prev;
+		dt_entry_list_delete(dt_node_tmp1);
+		dt_node_tmp1 = dt_node_tmp2;
+	}
+	free(dt_entry_queue);
 	return -1;
 }
 
-/* Function to obtain the index information for the correct device tree
- *  based on the platform data.
- *  If a matching device tree is found, the information is returned in the
- *  "dt_entry_info" out parameter and a function value of 0 is returned, otherwise
- *  a non-zero function value is returned.
- */
-int dev_tree_get_entry_info(struct dt_table *table, struct dt_entry *dt_entry_info)
-{
-	uint32_t target_variant_id;
-
-	target_variant_id = board_target_id();
-	if (__dev_tree_get_entry_info(table, dt_entry_info, target_variant_id, 0xff) == 0) {
-		return 0;
-	}
-
-	/*
-	 * for compatible with version 1 and version 2 dtbtool
-	 * will compare the subtype inside the variant id
-	 */
-	target_variant_id = board_hardware_id() | ((board_hardware_subtype() & 0xff) << 24);
-	if (__dev_tree_get_entry_info(table, dt_entry_info, target_variant_id, 0xff) == 0) {
-		return 0;
-	}
-
-	/*
-	* add compatible with old device selection method which don't compare subtype
-	*/
-	target_variant_id = board_hardware_id();
-	return __dev_tree_get_entry_info(table, dt_entry_info, target_variant_id, 0);
-}
-
 /* Function to add the first RAM partition info to the device tree.
  * Note: The function replaces the reg property in the "/memory" node
  * with the addr and size provided.
@@ -619,7 +1068,7 @@
 
 	/* Find the #address-cells size. */
 	valp = (uint32_t*)fdt_getprop(fdt, offset, "#address-cells", &len);
-	if (len <= 0)
+	if (len <= 0 || !valp)
 	{
 		if (len == -FDT_ERR_NOTFOUND)
 		{
@@ -640,7 +1089,7 @@
 
 	/* Find the #size-cells size. */
 	valp = (uint32_t*)fdt_getprop(fdt, offset, "#size-cells", &len);
-	if (len <= 0)
+	if (len <= 0 || !valp)
 	{
 		if (len == -FDT_ERR_NOTFOUND)
 		{
@@ -818,12 +1267,15 @@
 	}
 
 	offset = ret;
-	/* Adding the cmdline to the chosen node */
-	ret = fdt_setprop_string(fdt, offset, (const char*)"bootargs", (const void*)cmdline);
-	if (ret)
+	if (cmdline)
 	{
-		dprintf(CRITICAL, "ERROR: Cannot update chosen node [bootargs]\n");
-		return ret;
+		/* Adding the cmdline to the chosen node */
+		ret = fdt_appendprop_string(fdt, offset, (const char*)"bootargs", (const void*)cmdline);
+		if (ret)
+		{
+			dprintf(CRITICAL, "ERROR: Cannot update chosen node [bootargs]\n");
+			return ret;
+		}
 	}
 
 	if (ramdisk_size) {
diff --git a/platform/msm_shared/hsusb.c b/platform/msm_shared/hsusb.c
index c9ae3b2..49da56c 100644
--- a/platform/msm_shared/hsusb.c
+++ b/platform/msm_shared/hsusb.c
@@ -159,6 +159,7 @@
 	unsigned cfg;
 
 	ept = memalign(CACHE_LINE, ROUNDUP(sizeof(*ept), CACHE_LINE));
+	ASSERT(ept);
 
 	ept->maxpkt = max_pkt;
 	ept->num = num;
@@ -249,6 +250,7 @@
 {
 	struct usb_request *req;
 	req = memalign(CACHE_LINE, ROUNDUP(sizeof(*req), CACHE_LINE));
+	ASSERT(req);
 	req->req.buf = 0;
 	req->req.length = 0;
 	req->item = memalign(CACHE_LINE, ROUNDUP(sizeof(struct ept_queue_item),
@@ -693,6 +695,7 @@
 	writel(0x08, USB_AHB_MODE);
 
 	epts = memalign(lcm(4096, CACHE_LINE), ROUNDUP(4096, CACHE_LINE));
+	ASSERT(epts);
 
 	dprintf(INFO, "USB init ept @ %p\n", epts);
 	memset(epts, 0, 32 * sizeof(struct ept_queue_head));
diff --git a/platform/msm_shared/image_verify.c b/platform/msm_shared/image_verify.c
index 0d280f2..284f8e5 100644
--- a/platform/msm_shared/image_verify.c
+++ b/platform/msm_shared/image_verify.c
@@ -55,6 +55,11 @@
 		goto cleanup;
 	}
 	pub_key = X509_get_pubkey(x509_certificate);
+	if (pub_key == NULL) {
+		dprintf(CRITICAL, "ERROR: Boot Invalid, PUB_KEY is NULL!\n");
+		goto cleanup;
+	}
+
 	rsa_key = EVP_PKEY_get1_RSA(pub_key);
 	if (rsa_key == NULL) {
 		dprintf(CRITICAL, "ERROR: Boot Invalid, RSA_KEY is NULL!\n");
diff --git a/platform/msm_shared/include/board.h b/platform/msm_shared/include/board.h
index 75fc888..d7e82d5 100644
--- a/platform/msm_shared/include/board.h
+++ b/platform/msm_shared/include/board.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -39,10 +39,12 @@
 struct board_pmic_data {
 	uint32_t pmic_type;
 	uint32_t pmic_version;
+	uint32_t pmic_target;
 };
 
 struct board_data {
 	uint32_t platform;
+	uint32_t foundry_id;
 	uint32_t platform_version;
 	uint32_t platform_hw;
 	uint32_t platform_subtype;
@@ -64,6 +66,7 @@
 uint32_t board_hardware_subtype(void);
 uint32_t board_get_ddr_subtype(void);
 uint32_t board_hlos_subtype(void);
+uint32_t board_pmic_target(uint8_t num_ent);
 
 /* DDR Subtype Macros
  * Determine the DDR Size on the device and define
@@ -79,4 +82,5 @@
        SUBTYPE_512MB = 1,
 };
 
+uint32_t board_foundry_id(void);
 #endif
diff --git a/platform/msm_shared/include/dev_tree.h b/platform/msm_shared/include/dev_tree.h
index 1d9b9ad..a6534c0 100644
--- a/platform/msm_shared/include/dev_tree.h
+++ b/platform/msm_shared/include/dev_tree.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -27,6 +27,7 @@
 */
 
 #include <debug.h>
+#include <list.h>
 
 #ifndef __DEVICE_TREE__
 #define __DEVICE_TREE__
@@ -36,6 +37,8 @@
 #define DEV_TREE_MAGIC_LEN      4
 #define DEV_TREE_VERSION_V1     1
 #define DEV_TREE_VERSION_V2     2
+#define DEV_TREE_VERSION_V3     3
+
 #define DEV_TREE_HEADER_SIZE    12
 
 #define DTB_MAGIC               0xedfe0dd0
@@ -54,6 +57,18 @@
 #define DT_ENTRY_V1_SIZE        0xC
 #define PLAT_ID_SIZE            0x8
 #define BOARD_ID_SIZE           0x8
+#define PMIC_ID_SIZE           0x8
+
+
+struct dt_entry_v2
+{
+	uint32_t platform_id;
+	uint32_t variant_id;
+	uint32_t board_hw_subtype;
+	uint32_t soc_rev;
+	uint32_t offset;
+	uint32_t size;
+};
 
 struct dt_entry
 {
@@ -61,6 +76,7 @@
 	uint32_t variant_id;
 	uint32_t board_hw_subtype;
 	uint32_t soc_rev;
+	uint32_t pmic_rev[4];
 	uint32_t offset;
 	uint32_t size;
 };
@@ -84,6 +100,11 @@
 	uint32_t platform_subtype;
 };
 
+struct pmic_id
+{
+	uint32_t pmic_version[4];
+};
+
 struct dt_mem_node_info
 {
 	uint32_t offset;
@@ -92,12 +113,29 @@
 	uint32_t size_cell_size;
 };
 
+enum dt_entry_info
+{
+	DTB_FOUNDRY = 0,
+	DTB_SOC,
+	DTB_MAJOR_MINOR,
+	DTB_PMIC0,
+	DTB_PMIC1,
+	DTB_PMIC2,
+	DTB_PMIC3,
+	DTB_PMIC_MODEL,
+};
+
 enum dt_err_codes
 {
 	DT_OP_SUCCESS,
 	DT_OP_FAILURE = -1,
 };
 
+typedef struct dt_entry_node {
+	struct list_node node;
+	struct dt_entry * dt_entry_m;
+}dt_node;
+
 int dev_tree_validate(struct dt_table *table, unsigned int page_size, uint32_t *dt_hdr_size);
 int dev_tree_get_entry_info(struct dt_table *table, struct dt_entry *dt_entry_info);
 int update_device_tree(void *fdt, const char *, void *, unsigned);
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index dc54c8a..ac389ee 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -78,6 +78,7 @@
 #define MDSS_MDP_HW_REV_102    MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */
 #define MDSS_MDP_HW_REV_102_1  MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */
 #define MDSS_MDP_HW_REV_103    MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */
+#define MDSS_MDP_HW_REV_105    MDSS_MDP_REV(1, 5, 0) /* 8994 v1.0 */
 #define MDSS_MDP_HW_REV_106    MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */
 #define MDSS_MDP_HW_REV_108    MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */
 #define MDSS_MDP_HW_REV_200    MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */
@@ -110,6 +111,9 @@
 #define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL    REG_MDP(0x3F8)
 #define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL    REG_MDP(0x4F0)
 
+#define MDP_REG_PPB0_CNTL                       REG_MDP(0x1420)
+#define MDP_REG_PPB0_CONFIG                     REG_MDP(0x1424)
+
 #define MDP_INTF_0_BASE                         REG_MDP(0x12500)
 #define MDP_INTF_1_BASE                         REG_MDP(0x12700)
 #define MDP_INTF_2_BASE                         REG_MDP(0x12900)
@@ -144,6 +148,10 @@
 #define MMSS_MDP_SMP_ALLOC_W_BASE               REG_MDP(0x0180)
 #define MMSS_MDP_SMP_ALLOC_R_BASE               REG_MDP(0x0230)
 
+/* source pipe opmode bits for flip */
+#define MDSS_MDP_OP_MODE_FLIP_UD                BIT(14)
+#define MDSS_MDP_OP_MODE_FLIP_LR                BIT(13)
+
 #define MDP_QOS_REMAPPER_CLASS_0                REG_MDP(0x02E0)
 #define MDP_QOS_REMAPPER_CLASS_1                REG_MDP(0x02E4)
 
diff --git a/platform/msm_shared/include/mipi_dsi.h b/platform/msm_shared/include/mipi_dsi.h
index cdc5395..2a8e192 100644
--- a/platform/msm_shared/include/mipi_dsi.h
+++ b/platform/msm_shared/include/mipi_dsi.h
@@ -85,6 +85,8 @@
 #define MIPI_DSI_MRPS       0x04	/* Maximum Return Packet Size */
 #define MIPI_DSI_REG_LEN    16	/* 4 x 4 bytes register */
 
+#define DSI_HW_REV_103_1		0x10030001	/* 8936/8939 */
+
 #define DTYPE_GEN_WRITE2 0x23	/* 4th Byte is 0x80 */
 #define DTYPE_GEN_LWRITE 0x29	/* 4th Byte is 0xc0 */
 #define DTYPE_DCS_WRITE1 0x15	/* 4th Byte is 0x80 */
@@ -163,6 +165,7 @@
 	char bistCtrl[MAX_BIST_CONFIG];
 	char laneCfg[MAX_LANE_CONFIG];
 	enum dsi_reg_mode regulator_mode;
+	int is_pll_20nm;
 };
 
 typedef struct mdss_dsi_pll_config {
@@ -179,6 +182,15 @@
 	uint8_t   pclk_m;
 	uint8_t   pclk_n;
 	uint8_t   pclk_d;
+
+	/* pll 20nm */
+	uint32_t  dec_start;
+	uint32_t  frac_start;
+	uint32_t  lock_comp;
+	uint8_t  hr_oclk2;
+	uint8_t  hr_oclk3;
+	uint8_t  lp_div_mux;
+	uint8_t  ndiv;
 };
 
 struct mipi_dsi_cmd {
@@ -217,6 +229,8 @@
 int mdss_dsi_config(struct msm_fb_panel_data *panel);
 int mdss_dsi_phy_init(struct mipi_dsi_panel_config *,
 		uint32_t ctl_base, uint32_t phy_base);
+void mdss_dsi_phy_contention_detection(struct mipi_dsi_panel_config *,
+				uint32_t phy_base);
 
 int mdss_dsi_video_mode_config(uint16_t disp_width,
 	uint16_t disp_height,
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index 8bf3a8f..8b7af72 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -110,6 +110,7 @@
 	uint8_t dual_pipe;
 	uint8_t split_display;
 	uint8_t pipe_swap;
+	uint8_t dst_split;
 };
 
 struct mipi_panel_info {
@@ -194,7 +195,7 @@
 	uint32_t type;
 	uint32_t wait_cycle;
 	uint32_t clk_rate;
-	uint32_t rotation;
+	uint32_t orientation;
 	/*  Select pipe type for handoff */
 	uint32_t pipe_type;
 	char     lowpowerstop;
diff --git a/platform/msm_shared/include/partition_parser.h b/platform/msm_shared/include/partition_parser.h
index cf89433..a2d3edd 100644
--- a/platform/msm_shared/include/partition_parser.h
+++ b/platform/msm_shared/include/partition_parser.h
@@ -158,6 +158,12 @@
 	uint8_t lun;
 };
 
+/* Partition info requested by app layer */
+struct partition_info {
+	uint64_t offset;
+	uint64_t size;
+};
+
 int partition_get_index(const char *name);
 unsigned long long partition_get_size(int index);
 unsigned long long partition_get_offset(int index);
@@ -165,6 +171,11 @@
 unsigned int partition_read_table();
 unsigned int write_partition(unsigned size, unsigned char *partition);
 bool partition_gpt_exists();
+/* Return the partition offset & size to app layer
+ * Caller should validate the size & offset !=0
+ */
+
+struct partition_info partition_get_info(const char *name);
 
 /* For Debugging */
 void partition_dump(void);
diff --git a/platform/msm_shared/include/regulator.h b/platform/msm_shared/include/regulator.h
new file mode 100644
index 0000000..4e6c932
--- /dev/null
+++ b/platform/msm_shared/include/regulator.h
@@ -0,0 +1,52 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Fundation, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __REGULATOR_H
+#define __REGULATOR_H
+
+#define KEY_SOFTWARE_ENABLE                0x6E657773 // swen - software enable
+#define KEY_LDO_SOFTWARE_MODE              0X646D736C // lsmd - LDO software mode
+#define KEY_SMPS_SOFTWARE_MODE             0X646D7373 // ssmd - SMPS software mode
+#define KEY_PIN_CTRL_ENABLE                0x6E656370 //pcen - pin control enable
+#define KEY_PIN_CTRL_POWER_MODE            0x646d6370 // pcmd - pin control mode
+#define KEY_CURRENT                        0x616D //ma
+#define KEY_MICRO_VOLT                     0x7675 //uv
+#define KEY_FREQUENCY                      0x71657266 //freq
+#define KEY_FREQUENCY_REASON               0x6E736572 //resn
+#define KEY_FOLLOW_QUIET_MODE              0x6D71 //qm
+#define KEY_HEAD_ROOM                      0x7268 // hr
+#define KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY 0x62636370 // pccb - clk buffer pin control
+#define KEY_BYPASS_ALLOWED_KEY             0x61707962 //bypa - bypass allowed
+#define KEY_CORNER_LEVEL_KEY               0x6E726F63 // corn - coner voltage
+#define KEY_ACTIVE_FLOOR                   0x636676
+
+void regulator_enable();
+void regulator_disable();
+
+#endif
diff --git a/platform/msm_shared/include/rpm-smd.h b/platform/msm_shared/include/rpm-smd.h
new file mode 100644
index 0000000..5ac8a1b
--- /dev/null
+++ b/platform/msm_shared/include/rpm-smd.h
@@ -0,0 +1,97 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Fundation, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __RPM_SMD_H
+#define __RPM_SMD_H
+
+#include <arch/defines.h>
+#include <stdint.h>
+#include <sys/types.h>
+
+typedef enum
+{
+	RPM_REQUEST_TYPE,
+	RPM_CMD_TYPE,
+	RPM_SUCCESS_REQ_ACK,
+	RPM_SUCCESS_CMD_ACK,
+	RPM_ERROR_ACK,
+}msg_type;
+
+enum
+{
+	RESOURCETYPE,
+	RESOURCEID,
+	KVP_KEY,
+	KVP_LENGTH,
+	KVP_VALUE,
+};
+
+typedef struct
+{
+	uint32_t type;
+	uint32_t len;
+} rpm_gen_hdr;
+
+typedef struct
+{
+	uint32_t key;
+	uint32_t len;
+	uint32_t val;
+} kvp_data;
+
+typedef struct
+{
+	uint32_t id;
+	uint32_t set;
+	uint32_t resourceType;
+	uint32_t resourceId;
+	uint32_t dataLength;
+}rpm_req_hdr;
+
+typedef struct
+{
+	rpm_gen_hdr hdr;
+	rpm_req_hdr req_hdr;
+	kvp_data *data;
+} rpm_req;
+
+typedef struct
+{
+	rpm_gen_hdr hdr;
+	kvp_data *data;
+} rpm_cmd;
+
+typedef rpm_cmd rpm_ack_msg;
+int rpm_send_data(uint32_t *data, uint32_t len, msg_type type);
+uint32_t rpm_recv_data(uint32_t *len);
+void rpm_clk_enable(uint32_t *data, uint32_t len);
+void rpm_clk_disable(uint32_t *data, uint32_t len);
+void rpm_smd_init();
+void rpm_smd_uninit();
+#endif
diff --git a/platform/msm_shared/include/sdhci.h b/platform/msm_shared/include/sdhci.h
index beebb09..7dc93a6 100644
--- a/platform/msm_shared/include/sdhci.h
+++ b/platform/msm_shared/include/sdhci.h
@@ -288,8 +288,8 @@
 #define SDHCI_READ_MODE                           BIT(4)
 #define SDHCI_SWITCH_CMD                          6
 #define SDHCI_CMD_TIMEOUT                         0xF
-#define SDHCI_MAX_CMD_RETRY                       10000
-#define SDHCI_MAX_TRANS_RETRY                     10000
+#define SDHCI_MAX_CMD_RETRY                       5000000
+#define SDHCI_MAX_TRANS_RETRY                     10000000
 
 #define SDHCI_PREP_CMD(c, f)                      ((((c) & 0xff) << 8) | ((f) & 0xff))
 
diff --git a/platform/msm_shared/include/sdhci_msm.h b/platform/msm_shared/include/sdhci_msm.h
index 897a988..79ae142 100644
--- a/platform/msm_shared/include/sdhci_msm.h
+++ b/platform/msm_shared/include/sdhci_msm.h
@@ -132,4 +132,6 @@
 void sdhci_msm_init(struct sdhci_host *host, struct sdhci_msm_data *data);
 uint32_t sdhci_msm_execute_tuning(struct sdhci_host *host, struct mmc_card * card, uint32_t bus_width);
 void sdhci_mode_disable(struct sdhci_host *host);
+/* API: Toggle the bit for clock-data recovery */
+void sdhci_msm_toggle_cdr(struct sdhci_host *host, bool enable);
 #endif
diff --git a/platform/msm_shared/include/smd.h b/platform/msm_shared/include/smd.h
new file mode 100644
index 0000000..0daaace
--- /dev/null
+++ b/platform/msm_shared/include/smd.h
@@ -0,0 +1,129 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Fundation, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __SMD_H
+#define __SMD_H
+
+#include <arch/defines.h>
+#include <stdint.h>
+#include <sys/types.h>
+#include <string.h>
+#include <kernel/event.h>
+
+#define SMD_CHANNEL_ALLOC_MAX 2048
+#define SMD_CHANNEL_NAME_SIZE_MAX 20
+
+/* Stream related states */
+#define SMD_SS_CLOSED            0x0 /* Closed: must be 0 */
+#define SMD_SS_OPENING           0x1 /* Stream is opening */
+#define SMD_SS_OPENED            0x2 /* Stream is opened */
+#define SMD_SS_FLUSHING          0x3 /* Stream is flushing */
+#define SMD_SS_CLOSING           0x4 /* Stream is closing */
+#define SMD_SS_RESET             0x5 /* Stream is resetting */
+#define SMD_SS_RESET_OPENING     0x6 /* Stream reset on local */
+
+typedef enum
+{
+	SMD_APPS_RPM=0x0F,
+} smd_channel_type;
+
+typedef struct
+{
+	uint32_t stream_state;
+	uint32_t DTR_DSR;
+	uint32_t CTS_RTS;
+	uint32_t CD;
+	uint32_t RI;
+	uint32_t data_written;
+	uint32_t data_read;
+	uint32_t state_updated;
+	uint32_t mask_recv_intr;
+	uint32_t read_index;
+	uint32_t write_index;
+} smd_shared_stream_info_type;
+
+//Every port has 2 FIFOs, one in each direction
+typedef struct
+{
+	char name[SMD_CHANNEL_NAME_SIZE_MAX];
+	uint32_t cid;
+	uint32_t ctype;
+	uint32_t ref_count;
+} smd_channel_alloc_entry_t;
+
+typedef enum
+{
+	SMD_STREAMING_BUFFER,
+} smd_protocol_type;
+
+typedef struct
+{
+	smd_protocol_type protocol;
+	uint32_t port_id;
+	smd_channel_type ch_type;
+} smd_port_to_info_type;
+
+typedef struct
+{
+	uint32_t pkt_size;
+	uint32_t app_field;
+	uint32_t app_ptr;
+	uint32_t kind;
+	uint32_t priority;
+} smd_pkt_hdr;
+
+typedef struct
+{
+	smd_shared_stream_info_type ch0;
+	smd_shared_stream_info_type ch1;
+} smd_port_ctrl_info;
+
+typedef struct
+{
+	smd_channel_alloc_entry_t alloc_entry;
+	uint8_t *send_buf;
+	uint8_t *recv_buf;
+	uint32_t fifo_size;
+	smd_port_ctrl_info *port_info;
+	uint32_t current_state;
+	event_t wevt;
+	event_t revt;
+} smd_channel_info_t;
+
+int smd_init(smd_channel_info_t *ch, uint32_t ch_type);
+void smd_uninit(smd_channel_info_t *ch);
+uint8_t* smd_read(smd_channel_info_t *ch, uint32_t *len, int ch_type);
+int smd_write(smd_channel_info_t *ch, void *data, uint32_t len, int type);
+int smd_get_channel_info(smd_channel_info_t *ch, uint32_t ch_type);
+void smd_get_channel_entry(smd_channel_info_t *ch, uint32_t ch_type);
+void smd_notify_rpm();
+enum handler_return smd_irq_handler(void* data);
+void smd_set_state(smd_channel_info_t *ch, uint32_t state, uint32_t flag);
+void smd_signal_read_complete(smd_channel_info_t *ch, uint32_t len);
+#endif
diff --git a/platform/msm_shared/include/utp.h b/platform/msm_shared/include/utp.h
index 4d70f16..042c002 100644
--- a/platform/msm_shared/include/utp.h
+++ b/platform/msm_shared/include/utp.h
@@ -46,7 +46,7 @@
 
 #define UTP_MUTEX_ACQUIRE_TIMEOUT                          0x100000
 
-#define UTP_GENERIC_CMD_TIMEOUT                            10000
+#define UTP_GENERIC_CMD_TIMEOUT                            40000
 
 struct utp_prdt_entry
 {
diff --git a/platform/msm_shared/jtag.c b/platform/msm_shared/jtag.c
index 0430eaf..cf278f8 100644
--- a/platform/msm_shared/jtag.c
+++ b/platform/msm_shared/jtag.c
@@ -2,6 +2,8 @@
  * Copyright (C) 2008 The Android Open Source Project
  * All rights reserved.
  *
+ * Copyright (C) 2008-2014, The Linux Foundation. All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
@@ -11,6 +13,9 @@
  *    notice, this list of conditions and the following disclaimer in
  *    the documentation and/or other materials provided with the
  *    distribution.
+ *   * Neither the name of The Linux Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
@@ -32,10 +37,11 @@
 #define STATUS_OKAY  1
 #define STATUS_FAIL  2
 #define STATUS_PRINT 3
+#define JTAG_CMD_NUM  256
 
 volatile unsigned _jtag_cmd = 0;
 volatile unsigned _jtag_msg = 0;
-unsigned char _jtag_cmd_buffer[128];
+unsigned char _jtag_cmd_buffer[JTAG_CMD_NUM];
 unsigned char _jtag_msg_buffer[128];
 
 volatile unsigned _jtag_arg0 = 0;
@@ -82,7 +88,7 @@
 		if (jtag_cmd_pending()) {
 			do_cmd((const char *)_jtag_cmd_buffer, _jtag_arg0,
 			       _jtag_arg1, _jtag_arg2);
-			for (n = 0; n < 256; n++)
+			for (n = 0; n < JTAG_CMD_NUM; n++)
 				_jtag_cmd_buffer[n] = 0;
 			_jtag_arg0 = 0;
 			_jtag_arg1 = 0;
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index b860450..6e8fea4 100644
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -127,6 +127,7 @@
 {
 	uint32_t src_size, out_size, stride;
 	uint32_t fb_off = 0;
+	uint32_t flip_bits = 0;
 
 	/* write active region size*/
 	src_size = (fb->height << 16) + fb->width;
@@ -152,7 +153,15 @@
 	/* Tight Packing 3bpp 0-Alpha 8-bit R B G */
 	writel(0x0002243F, pipe_base + PIPE_SSPP_SRC_FORMAT);
 	writel(0x00020001, pipe_base + PIPE_SSPP_SRC_UNPACK_PATTERN);
-	writel(0x00, pipe_base + PIPE_SSPP_SRC_OP_MODE);
+
+	/* bit(0) is set if hflip is required.
+	 * bit(1) is set if vflip is required.
+	 */
+	if (pinfo->orientation & 0x1)
+		flip_bits |= MDSS_MDP_OP_MODE_FLIP_LR;
+	if (pinfo->orientation & 0x2)
+		flip_bits |= MDSS_MDP_OP_MODE_FLIP_UD;
+	writel(flip_bits, pipe_base + PIPE_SSPP_SRC_OP_MODE);
 }
 
 static void mdss_vbif_setup()
@@ -335,6 +344,11 @@
 		}
 	}
 
+	if (pinfo->lcdc.dst_split &&  (intf_base == MDP_INTF_1_BASE)) {
+		writel(BIT(16), MDP_REG_PPB0_CONFIG);
+		writel(BIT(5), MDP_REG_PPB0_CNTL);
+	}
+
 	mdss_mdp_intf_off = intf_base + mdss_mdp_intf_offset();
 
 	hsync_period = lcdc->h_pulse_width +
@@ -532,9 +546,15 @@
 	reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo, 1);
 	writel(reg, MDP_CTL_0_BASE + CTL_TOP);
 
+	/*If dst_split is enabled only intf 2 needs to be enabled.
+	CTL_1 path should not be set since CTL_0 itself is going
+	to split after DSPP block*/
+
 	if (pinfo->mipi.dual_dsi) {
-		reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo, 0);
-		writel(reg, MDP_CTL_1_BASE + CTL_TOP);
+		if (!pinfo->lcdc.dst_split) {
+			reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo,0);
+			writel(reg, MDP_CTL_1_BASE + CTL_TOP);
+		}
 		intf_sel |= BIT(16); /* INTF 2 enable */
 	}
 
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 0700fc5..7ac614e 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -364,6 +364,7 @@
 	uint8_t DLNx_EN;
 	uint8_t lane_swap = 0;
 	uint32_t timing_ctl = 0;
+	uint32_t lane_swap_dsi1 = 0;
 
 #if (DISPLAY_TYPE_MDSS == 1)
 	switch (pinfo->num_of_lanes) {
@@ -400,7 +401,11 @@
 				| PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1,
 				MIPI_DSI1_BASE + COMMAND_MODE_DMA_CTRL);
 
-		writel(lane_swap, MIPI_DSI1_BASE + LANE_SWAP_CTL);
+		if (readl(MIPI_DSI_BASE) == DSI_HW_REV_103_1) /*for 8939 hw dsi1 has Lane_map as 3210*/
+			lane_swap_dsi1 = 0x7;
+		else
+			lane_swap_dsi1 = lane_swap;
+		writel(lane_swap_dsi1, MIPI_DSI1_BASE + LANE_SWAP_CTL);
 		writel(timing_ctl, MIPI_DSI1_BASE + TIMING_CTL);
 	}
 
@@ -679,6 +684,8 @@
 		goto error;
 	}
 
+	mdss_dsi_phy_contention_detection(&mipi_pinfo, DSI0_PHY_BASE);
+
 	if (panel->pre_init_func) {
 		ret = panel->pre_init_func();
 		if (ret) {
@@ -797,13 +804,12 @@
 		mdelay(10);
 		writel(0x0001, DSI_SOFT_RESET);
 		writel(0x0000, DSI_SOFT_RESET);
-		writel(0x1115501, DSI_INT_CTRL);
 		writel(0, DSI_CTRL);
 	}
 
-	writel(0x1115501, DSI_INT_CTRL);
+	writel(0x1115501, MIPI_DSI0_BASE + INT_CTRL);
 	if (pinfo->mipi.broadcast)
-		writel(0x1115501, DSI_INT_CTRL + 0x600);
+		writel(0x1115501, MIPI_DSI1_BASE + INT_CTRL);
 
 	return NO_ERROR;
 }
diff --git a/platform/msm_shared/mipi_dsi_autopll_20nm.c b/platform/msm_shared/mipi_dsi_autopll_20nm.c
new file mode 100644
index 0000000..754eb18
--- /dev/null
+++ b/platform/msm_shared/mipi_dsi_autopll_20nm.c
@@ -0,0 +1,276 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include <debug.h>
+#include <reg.h>
+#include <err.h>
+#include <smem.h>
+#include <mipi_dsi.h>
+#include <platform/iomap.h>
+
+#define LPFR_LUT_SIZE 10
+
+#define VCO_REF_CLOCK_RATE 19200000
+
+#define FRAC_DIVIDER 10000
+
+#define MMSS_DSI_PHY_PLL_SYS_CLK_CTRL                   0x0000
+#define MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN                 0x0004
+#define MMSS_DSI_PHY_PLL_CMN_MODE                       0x0008
+#define MMSS_DSI_PHY_PLL_IE_TRIM                        0x000C
+#define MMSS_DSI_PHY_PLL_IP_TRIM                        0x0010
+#define MMSS_DSI_PHY_PLL_PLL_CNTRL              	0x0014
+#define MMSS_DSI_PHY_PLL_PLL_PHSEL_CONTROL              0x0018
+#define MMSS_DSI_PHY_PLL_IPTAT_TRIM_VCCA_TX_SEL         0x001C
+#define MMSS_DSI_PHY_PLL_PLL_PHSEL_DC                   0x0020
+#define MMSS_DSI_PHY_PLL_PLL_IP_SETI                    0x0024
+#define MMSS_DSI_PHY_PLL_CORE_CLK_IN_SYNC_SEL           0x0028
+#define MMSS_DSI_PHY_PLL_PLL_BKG_KVCO_CAL_EN    	0x002C
+
+#define MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN            0x0030
+#define MMSS_DSI_PHY_PLL_PLL_CP_SETI                    0x0034
+#define MMSS_DSI_PHY_PLL_PLL_IP_SETP                    0x0038
+#define MMSS_DSI_PHY_PLL_PLL_CP_SETP                    0x003C
+#define MMSS_DSI_PHY_PLL_ATB_SEL1                       0x0040
+#define MMSS_DSI_PHY_PLL_ATB_SEL2                       0x0044
+#define MMSS_DSI_PHY_PLL_SYSCLK_EN_SEL_TXBAND           0x0048
+#define MMSS_DSI_PHY_PLL_RESETSM_CNTRL                  0x004C
+#define MMSS_DSI_PHY_PLL_RESETSM_CNTRL2                 0x0050
+#define MMSS_DSI_PHY_PLL_RESETSM_CNTRL3                 0x0054
+#define MMSS_DSI_PHY_PLL_RESETSM_PLL_CAL_COUNT1         0x0058
+#define MMSS_DSI_PHY_PLL_RESETSM_PLL_CAL_COUNT2         0x005C
+#define MMSS_DSI_PHY_PLL_DIV_REF1                       0x0060
+#define MMSS_DSI_PHY_PLL_DIV_REF2                       0x0064
+#define MMSS_DSI_PHY_PLL_KVCO_COUNT1                    0x0068
+#define MMSS_DSI_PHY_PLL_KVCO_COUNT2                    0x006C
+#define MMSS_DSI_PHY_PLL_KVCO_CAL_CNTRL                 0x0070
+#define MMSS_DSI_PHY_PLL_KVCO_CODE                      0x0074
+#define MMSS_DSI_PHY_PLL_VREF_CFG1                      0x0078
+#define MMSS_DSI_PHY_PLL_VREF_CFG2                      0x007C
+#define MMSS_DSI_PHY_PLL_VREF_CFG3                      0x0080
+#define MMSS_DSI_PHY_PLL_VREF_CFG4                      0x0084
+#define MMSS_DSI_PHY_PLL_VREF_CFG5                      0x0088
+#define MMSS_DSI_PHY_PLL_VREF_CFG6                      0x008C
+#define MMSS_DSI_PHY_PLL_PLLLOCK_CMP1                   0x0090
+#define MMSS_DSI_PHY_PLL_PLLLOCK_CMP2                   0x0094
+#define MMSS_DSI_PHY_PLL_PLLLOCK_CMP3                   0x0098
+#define MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN         	0x009C
+
+#define MMSS_DSI_PHY_PLL_BGTC                           0x00A0
+#define MMSS_DSI_PHY_PLL_PLL_TEST_UPDN                  0x00A4
+#define MMSS_DSI_PHY_PLL_PLL_VCO_TUNE                   0x00A8
+#define MMSS_DSI_PHY_PLL_DEC_START1                     0x00AC
+#define MMSS_DSI_PHY_PLL_PLL_AMP_OS                     0x00B0
+#define MMSS_DSI_PHY_PLL_SSC_EN_CENTER                  0x00B4
+#define MMSS_DSI_PHY_PLL_SSC_ADJ_PER1                   0x00B8
+#define MMSS_DSI_PHY_PLL_SSC_ADJ_PER2                   0x00BC
+#define MMSS_DSI_PHY_PLL_SSC_PER1                       0x00C0
+#define MMSS_DSI_PHY_PLL_SSC_PER2                       0x00C4
+#define MMSS_DSI_PHY_PLL_SSC_STEP_SIZE1                 0x00C8
+#define MMSS_DSI_PHY_PLL_SSC_STEP_SIZE2                 0x00CC
+#define MMSS_DSI_PHY_PLL_RES_CODE_UP                    0x00D0
+#define MMSS_DSI_PHY_PLL_RES_CODE_DN                    0x00D4
+#define MMSS_DSI_PHY_PLL_RES_CODE_UP_OFFSET             0x00D8
+#define MMSS_DSI_PHY_PLL_RES_CODE_DN_OFFSET             0x00DC
+#define MMSS_DSI_PHY_PLL_RES_CODE_START_SEG1            0x00E0
+#define MMSS_DSI_PHY_PLL_RES_CODE_START_SEG2            0x00E4
+#define MMSS_DSI_PHY_PLL_RES_CODE_CAL_CSR               0x00E8
+#define MMSS_DSI_PHY_PLL_RES_CODE                       0x00EC
+#define MMSS_DSI_PHY_PLL_RES_TRIM_CONTROL               0x00F0
+#define MMSS_DSI_PHY_PLL_RES_TRIM_CONTROL2              0x00F4
+#define MMSS_DSI_PHY_PLL_RES_TRIM_EN_VCOCALDONE         0x00F8
+#define MMSS_DSI_PHY_PLL_FAUX_EN                        0x00FC
+
+#define MMSS_DSI_PHY_PLL_DIV_FRAC_START1                0x0100
+#define MMSS_DSI_PHY_PLL_DIV_FRAC_START2                0x0104
+#define MMSS_DSI_PHY_PLL_DIV_FRAC_START3                0x0108
+#define MMSS_DSI_PHY_PLL_DEC_START2                     0x010C
+#define MMSS_DSI_PHY_PLL_PLL_RXTXEPCLK_EN               0x0110
+#define MMSS_DSI_PHY_PLL_PLL_CRCTRL                     0x0114
+#define MMSS_DSI_PHY_PLL_LOW_POWER_RO_CONTROL           0x013C
+#define MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL           0x0140
+#define MMSS_DSI_PHY_PLL_HR_OCLK2_DIVIDER               0x0144
+#define MMSS_DSI_PHY_PLL_HR_OCLK3_DIVIDER               0x0148
+#define MMSS_DSI_PHY_PLL_PLL_VCO_HIGH                   0x014C
+#define MMSS_DSI_PHY_PLL_RESET_SM                       0x0150
+
+uint32_t mdss_dsi_pll_20nm_lock_status(uint32_t pll_base)
+{
+	uint32_t cnt, status;
+
+	udelay(1000);
+
+	/* check pll lock first */
+	for (cnt = 0; cnt < 5; cnt++) {
+		status = readl(pll_base + MMSS_DSI_PHY_PLL_RESET_SM);
+		dprintf(SPEW, "%s: pll_base=%x cnt=%d status=%x\n",
+				__func__, pll_base, cnt, status);
+		status &= 0x20; /* bit 5 */
+		if (status)
+			break;
+		udelay(5000);
+	}
+
+	if (!status)
+		goto pll_done;
+
+	/* check pll ready */
+	for (cnt = 0; cnt < 5; cnt++) {
+		status = readl(pll_base + MMSS_DSI_PHY_PLL_RESET_SM);
+		dprintf(SPEW, "%s: pll_base=%x cnt=%d status=%x\n",
+				__func__, pll_base, cnt, status);
+		status &= 0x40; /* bit 6 */
+		if (status)
+			break;
+		udelay(5000);
+	}
+
+pll_done:
+	return status;
+}
+
+uint32_t mdss_dsi_pll_20nm_sw_reset_st_machine(uint32_t pll_base)
+{
+	writel(0x64, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_START_SEG1);
+	writel(0x64, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_START_SEG2);
+	writel(0x15, pll_base + MMSS_DSI_PHY_PLL_RES_TRIM_CONTROL);
+
+	writel(0x20, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL);
+	writel(0x07, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL2);
+	writel(0x02, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
+	writel(0x03, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
+}
+
+static void pll_20nm_phy_kvco_config(uint32_t pll_base)
+{
+
+	writel(0x00, pll_base + MMSS_DSI_PHY_PLL_DIV_REF1);
+	writel(0x01, pll_base + MMSS_DSI_PHY_PLL_DIV_REF2);
+	writel(0x8a, pll_base + MMSS_DSI_PHY_PLL_KVCO_COUNT1);
+	writel(0x00, pll_base + MMSS_DSI_PHY_PLL_KVCO_CAL_CNTRL);
+	writel(0x00, pll_base + MMSS_DSI_PHY_PLL_KVCO_CODE);
+}
+
+static void pll_20nm_phy_loop_bw_config(uint32_t pll_base)
+{
+	writel(0x03, pll_base + MMSS_DSI_PHY_PLL_PLL_IP_SETI);
+	writel(0x3f, pll_base + MMSS_DSI_PHY_PLL_PLL_CP_SETI);
+	writel(0x03, pll_base + MMSS_DSI_PHY_PLL_PLL_IP_SETP);
+	writel(0x1f, pll_base + MMSS_DSI_PHY_PLL_PLL_CP_SETP);
+	writel(0x77, pll_base + MMSS_DSI_PHY_PLL_PLL_CRCTRL);
+}
+
+static void pll_20nm_phy_config(uint32_t pll_base)
+{
+	writel(0x40, pll_base + MMSS_DSI_PHY_PLL_SYS_CLK_CTRL);
+	writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN);
+	writel(0x00, pll_base + MMSS_DSI_PHY_PLL_CMN_MODE);
+	writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_IE_TRIM);
+	writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_IP_TRIM);
+	writel(0x08, pll_base + MMSS_DSI_PHY_PLL_PLL_PHSEL_CONTROL);
+	writel(0x0e, pll_base + MMSS_DSI_PHY_PLL_IPTAT_TRIM_VCCA_TX_SEL);
+	writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_PHSEL_DC);
+	writel(0x00, pll_base + MMSS_DSI_PHY_PLL_CORE_CLK_IN_SYNC_SEL);
+	writel(0x08, pll_base + MMSS_DSI_PHY_PLL_PLL_BKG_KVCO_CAL_EN);
+	writel(0x3f, pll_base + MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN);
+	writel(0x00, pll_base + MMSS_DSI_PHY_PLL_ATB_SEL1);
+	writel(0x00, pll_base + MMSS_DSI_PHY_PLL_ATB_SEL2);
+	writel(0x4b, pll_base + MMSS_DSI_PHY_PLL_SYSCLK_EN_SEL_TXBAND);
+	udelay(1000);
+
+	pll_20nm_phy_kvco_config(pll_base);
+
+	writel(0x00, pll_base + MMSS_DSI_PHY_PLL_VREF_CFG1);
+	writel(0x00, pll_base + MMSS_DSI_PHY_PLL_VREF_CFG2);
+	writel(0x10, pll_base + MMSS_DSI_PHY_PLL_VREF_CFG3);
+	writel(0x00, pll_base + MMSS_DSI_PHY_PLL_VREF_CFG4);
+	writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_BGTC);
+	writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_TEST_UPDN);
+	writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_VCO_TUNE);
+	writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_AMP_OS);
+	writel(0x00, pll_base + MMSS_DSI_PHY_PLL_SSC_EN_CENTER);
+	writel(0x00, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_UP);
+	writel(0x00, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_DN);
+	writel(0x00, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_CAL_CSR);
+	writel(0x00, pll_base + MMSS_DSI_PHY_PLL_RES_TRIM_EN_VCOCALDONE);
+	writel(0x0c, pll_base + MMSS_DSI_PHY_PLL_FAUX_EN);
+	writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_PLL_RXTXEPCLK_EN);
+
+	writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_LOW_POWER_RO_CONTROL);
+	udelay(1000);
+
+	pll_20nm_phy_loop_bw_config(pll_base);
+}
+
+int32_t mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t ctl_base,
+				struct mdss_dsi_pll_config *pd)
+{
+	uint32_t data;
+
+	mdss_dsi_phy_sw_reset(ctl_base);
+	pll_20nm_phy_config(pll_base);
+
+	/* set up divider */
+	data = readl(pll_base + MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL);
+	data |= 0x080; /* bit 7 */
+	data |= (pd->lp_div_mux << 5);
+	data |= pd->ndiv;
+
+	writel(data, pll_base + MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL);
+
+	writel(pd->hr_oclk2, pll_base + MMSS_DSI_PHY_PLL_HR_OCLK2_DIVIDER);
+	writel(pd->hr_oclk3, pll_base + MMSS_DSI_PHY_PLL_HR_OCLK3_DIVIDER);
+
+	writel(((pd->frac_start & 0x7f) | 0x80),
+				pll_base + MMSS_DSI_PHY_PLL_DIV_FRAC_START1);
+	writel((((pd->frac_start >> 7) & 0x7f) | 0x80),
+				pll_base + MMSS_DSI_PHY_PLL_DIV_FRAC_START2);
+	writel((((pd->frac_start >> 14) & 0x3f) | 0x40),
+				pll_base + MMSS_DSI_PHY_PLL_DIV_FRAC_START3);
+
+	writel(((pd->dec_start & 0x7f) | 0x80),
+				pll_base + MMSS_DSI_PHY_PLL_DEC_START1);
+	writel((((pd->dec_start & 0x80) >> 7) | 0x02),
+				pll_base + MMSS_DSI_PHY_PLL_DEC_START2);
+
+	writel((pd->lock_comp & 0xff),
+				pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP1);
+
+	writel(((pd->lock_comp >> 8) & 0xff),
+				pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP2);
+
+	writel(((pd->lock_comp >> 16) & 0xff),
+				pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP3);
+
+	/*
+	 * Make sure that PLL vco configuration is complete
+	 * before controlling the state machine.
+	 */
+	udelay(1000);
+	dmb();
+}
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index 4e9ed58..cd2d217 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -36,6 +36,23 @@
 #define MIPI_DSI1_BASE MIPI_DSI_BASE
 #endif
 
+#define MMSS_DSI_CLKOUT_TIMING_CTRL               0x0c4
+#define MMSS_DSI_PHY_TIMING_CTRL_0                0x0140
+#define MMSS_DSI_PHY_CTRL_0                       0x0170
+#define MMSS_DSI_PHY_CTRL_1                       0x0174
+#define MMSS_DSI_PHY_CTRL_2                       0x0178
+#define MMSS_DSI_PHY_STRENGTH_CTRL_0              0x0184
+#define MMSS_DSI_PHY_STRENGTH_CTRL_1              0x0188
+#define MMSS_DSI_PHY_BIST_CTRL_0                  0x01b4
+#define MMSS_DSI_PHY_GLBL_TEST_CTRL               0x01d4
+#define MMSS_DSI_PHY_LDO_CTRL                     0x01dc
+
+#define TOTAL_TIMING_CTRL_CONFIG                  12
+#define TOTAL_BIST_CTRL_CONFIG                    6
+/* 4 data lanes and 1 clock lanes */
+#define TOTAL_LANE_COUNT                          5
+#define CONFIG_REG_FOR_EACH_LANE                  9
+
 static void mipi_dsi_calibration(void)
 {
 	uint32_t i = 0;
@@ -274,7 +291,7 @@
 	return 0;
 }
 
-int mdss_dsi_phy_init(struct mipi_dsi_panel_config *pinfo,
+static int mdss_dsi_phy_28nm_init(struct mipi_dsi_panel_config *pinfo,
 				uint32_t ctl_base, uint32_t phy_base)
 {
 	struct mdss_dsi_phy_ctrl *pd;
@@ -310,8 +327,6 @@
 	/* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */
 	writel(0x5f, phy_base + 0x0170);
 
-	/* Strength ctrl 1 */
-	writel(pd->strength[1], phy_base + 0x0188);
 	dmb();
 	/* 4 lanes + clk lane configuration */
 	/* lane config n * (0 - 4) & DataPath setup */
@@ -329,7 +344,8 @@
 	writel(0x5f, phy_base + 0x0170);
 
 	/* DSI_PHY_DSIPHY_GLBL_TEST_CTRL */
-	if (phy_base == DSI0_PHY_BASE)
+	if (phy_base == DSI0_PHY_BASE ||
+		(readl(MIPI_DSI0_BASE) == DSI_HW_REV_103_1))
 		writel(0x01, phy_base + 0x01d4);
 	else
 		writel(0x00, phy_base + 0x01d4);
@@ -348,3 +364,96 @@
 	dmb();
 
 }
+
+void mdss_dsi_phy_contention_detection(
+		struct mipi_dsi_panel_config *pinfo,
+		uint32_t phy_base)
+{
+        struct mdss_dsi_phy_ctrl *pd;
+
+        if (mdp_get_revision() == MDP_REV_304)
+                return;
+
+        pd = (pinfo->mdss_dsi_phy_config);
+	writel(pd->strength[1], phy_base + 0x0188);
+	dmb();
+}
+
+static int mdss_dsi_phy_20nm_init(struct mipi_dsi_panel_config *pinfo,
+				uint32_t ctl_base, uint32_t phy_base)
+{
+	struct mdss_dsi_phy_ctrl *pd = pinfo->mdss_dsi_phy_config;
+	uint32_t i, off = 0, ln, offset;
+
+	/* Strength ctrl 0 */
+	writel(pd->strength[0], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_0);
+
+	if (pd->regulator_mode == DSI_PHY_REGULATOR_LDO_MODE)
+		pd->regulator[0] = 0x2; /* LDO mode */
+	mdss_dsi_phy_regulator_init(pd);
+
+	if (pd->regulator_mode == DSI_PHY_REGULATOR_LDO_MODE)
+		writel(0x25, phy_base + MMSS_DSI_PHY_LDO_CTRL); /* LDO mode */
+	else
+		writel(0x00, phy_base + MMSS_DSI_PHY_LDO_CTRL); /* DCDC mode */
+
+	off = MMSS_DSI_PHY_TIMING_CTRL_0;
+	for (i = 0; i < TOTAL_TIMING_CTRL_CONFIG; i++, off += 4) {
+		writel(pd->timing[i], phy_base + off);
+		dmb();
+	}
+
+        /* Currently the Phy settings for the DSI 0 is done in clk prepare*/
+	if (phy_base == DSI1_PHY_BASE) {
+		writel(0x00, phy_base + MMSS_DSI_PHY_CTRL_1);
+		writel(0x05, phy_base + MMSS_DSI_PHY_CTRL_0);
+		dmb();
+
+		writel(0x7f, phy_base + MMSS_DSI_PHY_CTRL_0);
+		dmb();
+
+		/* BITCLK_HS_SEL should be set to 0 for left */
+		writel(0x00, phy_base + MMSS_DSI_PHY_GLBL_TEST_CTRL);
+
+		writel(0x00, phy_base + MMSS_DSI_PHY_CTRL_2);
+		writel(0x02, phy_base + MMSS_DSI_PHY_CTRL_2);
+		writel(0x03, phy_base + MMSS_DSI_PHY_CTRL_2);
+		dmb();
+	}
+
+	writel(pd->strength[1], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_1);
+	dmb();
+
+	for (ln = 0; ln < TOTAL_LANE_COUNT; ln++) {
+		off = (ln * 0x40);
+		for (i = 0; i < CONFIG_REG_FOR_EACH_LANE; i++, off += 4) {
+			offset = i + (ln * CONFIG_REG_FOR_EACH_LANE);
+			writel(pd->laneCfg[offset], phy_base + off);
+			dmb();
+		}
+	}
+
+	dmb();
+
+	off = MMSS_DSI_PHY_BIST_CTRL_0;
+	for (i = 0; i < TOTAL_BIST_CTRL_CONFIG; i++, off +=4) {
+		writel(pd->bistCtrl[i], phy_base + off);
+	}
+	dmb();
+
+	writel(0x41b, ctl_base + MMSS_DSI_CLKOUT_TIMING_CTRL);
+	dmb();
+}
+
+int mdss_dsi_phy_init (struct mipi_dsi_panel_config *pinfo,
+				uint32_t ctl_base, uint32_t phy_base)
+{
+	int ret;
+
+	if (pinfo->mdss_dsi_phy_config->is_pll_20nm)
+		ret = mdss_dsi_phy_20nm_init(pinfo, ctl_base, phy_base);
+	else
+		ret = mdss_dsi_phy_28nm_init(pinfo, ctl_base, phy_base);
+
+	return ret;
+}
diff --git a/platform/msm_shared/mmc_sdhci.c b/platform/msm_shared/mmc_sdhci.c
index 7b76875..982af7a 100644
--- a/platform/msm_shared/mmc_sdhci.c
+++ b/platform/msm_shared/mmc_sdhci.c
@@ -878,15 +878,27 @@
 		sdhci_msm_set_mci_clk(host);
 		clock_config_mmc(host->msm_host->slot, SDHCI_CLK_400MHZ);
 	}
+
+	/* Execute Tuning for hs200 mode */
+	if ((mmc_ret = sdhci_msm_execute_tuning(host, card, width)))
+		dprintf(CRITICAL, "Tuning for hs200 failed\n");
+
+	/* Once the tuning is executed revert back the clock to 200MHZ
+	 * and disable the MCI_CLK divider so that we can use SDHC clock
+	 * divider to supply clock to the card
+	 */
+	if (host->timing == MMC_HS400_TIMING)
+	{
+		MMC_SAVE_TIMING(host, MMC_HS200_TIMING);
+		sdhci_msm_set_mci_clk(host);
+		clock_config_mmc(host->msm_host->slot, MMC_CLK_192MHZ);
+	}
 	else
 	{
 		/* Save the timing value, before changing the clock */
 		MMC_SAVE_TIMING(host, MMC_HS200_TIMING);
 	}
 
-	/* Execute Tuning for hs200 mode */
-	if ((mmc_ret = sdhci_msm_execute_tuning(host, card, width)))
-		dprintf(CRITICAL, "Tuning for hs200 failed\n");
 
 	DBG("\n Enabling HS200 Mode Done\n");
 
@@ -1034,6 +1046,8 @@
 	* Enable HS400 mode
 	*/
 	sdhci_msm_set_mci_clk(host);
+	/* Set the clock back to 400 MHZ */
+	clock_config_mmc(host->msm_host->slot, SDHCI_CLK_400MHZ);
 
 	/* 7. Execute Tuning for hs400 mode */
 	if ((mmc_ret = sdhci_msm_execute_tuning(host, card, width)))
diff --git a/platform/msm_shared/partition_parser.c b/platform/msm_shared/partition_parser.c
index 5534024..d8774b9 100644
--- a/platform/msm_shared/partition_parser.c
+++ b/platform/msm_shared/partition_parser.c
@@ -910,6 +910,33 @@
 	}
 }
 
+struct partition_info partition_get_info(const char *name)
+{
+	struct partition_info info = {0};
+
+	int index = INVALID_PTN;
+
+	if(!name)
+	{
+		dprintf(CRITICAL, "Invalid partition name passed\n");
+		goto out;
+	}
+
+	index = partition_get_index(name);
+
+	if (index != INVALID_PTN)
+	{
+		info.offset = partition_get_offset(index);
+		info.size   = partition_get_size(index);
+	}
+	else
+	{
+		dprintf(CRITICAL, "Error unable to find partition : [%s]\n", name);
+	}
+out:
+	return info;
+}
+
 uint8_t partition_get_lun(int index)
 {
 	return partition_entries[index].lun;
diff --git a/platform/msm_shared/qgic.c b/platform/msm_shared/qgic.c
index 09bb238..48e846d 100644
--- a/platform/msm_shared/qgic.c
+++ b/platform/msm_shared/qgic.c
@@ -132,7 +132,7 @@
 	enum handler_return ret;
 
 	num = readl(GIC_CPU_INTACK);
-	if (num > NR_IRQS)
+	if (num >= NR_IRQS)
 		return 0;
 
 	ret = handler[num].func(handler[num].arg);
diff --git a/platform/msm_shared/qpic_nand.c b/platform/msm_shared/qpic_nand.c
index f638e37..0c858d9 100644
--- a/platform/msm_shared/qpic_nand.c
+++ b/platform/msm_shared/qpic_nand.c
@@ -607,6 +607,7 @@
 
 	/* Allocate memory required to read the onfi param page */
 	buffer = (unsigned char*) malloc(ONFI_READ_PARAM_PAGE_BUFFER_SIZE);
+	ASSERT(buffer != NULL);
 
 	/* Read the vld and dev_cmd1 registers before modifying */
 	vld = qpic_nand_read_reg(NAND_DEV_CMD_VLD, 0, ce_array);
diff --git a/platform/msm_shared/qusb2_phy.c b/platform/msm_shared/qusb2_phy.c
index 8e59579..6675d67 100644
--- a/platform/msm_shared/qusb2_phy.c
+++ b/platform/msm_shared/qusb2_phy.c
@@ -41,11 +41,28 @@
 	udelay(10);
 	writel(val & ~BIT(0), GCC_QUSB2_PHY_BCR);
 
-	/* Deassert POWERDOWN by clearing bit 0 to enable the PHY */
-	val = readl(QUSB2PHY_PORT_POWERDOWN);
-	writel(val & ~BIT(0), QUSB2PHY_PORT_POWERDOWN);
+	/* set CLAMP_N_EN and stay with disabled USB PHY */
+	writel(0x23, QUSB2PHY_PORT_POWERDOWN);
+
+	/* Set HS impedance to 42ohms */
+	writel(0xA0, QUSB2PHY_PORT_TUNE1);
+
+	/* Set TX current to 19mA, TX SR and TX bias current to 1, 1 */
+	writel(0xA5, QUSB2PHY_PORT_TUNE2);
+
+	/* Increase autocalibration bias circuit settling time
+	 * and enable utocalibration  */
+	writel(0x81, QUSB2PHY_PORT_TUNE3);
+
+	writel(0x85, QUSB2PHY_PORT_TUNE4);
+	/* Wait for tuning params to take effect right before re-enabling power*/
 	udelay(10);
 
-	/* set CLAMP_N_EN and FREEZIO_N */
+	/* Disable the PHY */
+	writel(0x23, QUSB2PHY_PORT_POWERDOWN);
+	/* Enable ULPI mode */
+	writel(0x0,  QUSB2PHY_PORT_UTMI_CTRL2);
+	/* Enable PHY */
+	/* set CLAMP_N_EN and USB PHY is enabled*/
 	writel(0x22, QUSB2PHY_PORT_POWERDOWN);
 }
diff --git a/platform/msm_shared/regulator.c b/platform/msm_shared/regulator.c
new file mode 100644
index 0000000..440049b
--- /dev/null
+++ b/platform/msm_shared/regulator.c
@@ -0,0 +1,123 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Fundation, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <regulator.h>
+#include <rpm-smd.h>
+
+#define GENERIC_DISABLE 0
+#define GENERIC_ENABLE  1
+#define SW_MODE_LDO_IPEAK 1
+#define LDOA_RES_TYPE 0x616F646C //aodl
+#define SMPS_RES_TYPE 0x61706D73 //apms
+
+static uint32_t ldo2[][11]=
+{
+	{
+		LDOA_RES_TYPE, 2,
+		KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
+		KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
+		KEY_MICRO_VOLT, 4, 0,
+	},
+
+	{
+		LDOA_RES_TYPE, 2,
+		KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
+		KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
+		KEY_MICRO_VOLT, 4, 1250000,
+	},
+};
+
+static uint32_t ldo12[][11]=
+{
+	{
+		LDOA_RES_TYPE, 12,
+		KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
+		KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
+		KEY_MICRO_VOLT, 4, 0,
+	},
+
+	{
+		LDOA_RES_TYPE, 12,
+		KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
+		KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
+		KEY_MICRO_VOLT, 4, 1800000,
+	},
+};
+
+static uint32_t ldo14[][11]=
+{
+	{
+		LDOA_RES_TYPE, 14,
+		KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
+		KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
+		KEY_MICRO_VOLT, 4, 0,
+	},
+
+	{
+		LDOA_RES_TYPE, 14,
+		KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
+		KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
+		KEY_MICRO_VOLT, 4, 1800000,
+	},
+};
+
+static uint32_t ldo28[][11]=
+{
+	{
+		LDOA_RES_TYPE, 28,
+		KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
+		KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
+		KEY_MICRO_VOLT, 4, 0,
+	},
+
+	{
+		LDOA_RES_TYPE, 28,
+		KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
+		KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
+		KEY_MICRO_VOLT, 4, 1000000,
+	},
+
+};
+
+void regulator_enable()
+{
+	rpm_send_data(&ldo2[GENERIC_ENABLE][0], 36, RPM_REQUEST_TYPE);
+
+	rpm_send_data(&ldo12[GENERIC_ENABLE][0], 36, RPM_REQUEST_TYPE);
+
+	rpm_send_data(&ldo14[GENERIC_ENABLE][0], 36, RPM_REQUEST_TYPE);
+
+	rpm_send_data(&ldo28[GENERIC_ENABLE][0], 36, RPM_REQUEST_TYPE);
+}
+
+
+void regulator_disable()
+{
+
+}
diff --git a/platform/msm_shared/rpm-smd.c b/platform/msm_shared/rpm-smd.c
new file mode 100644
index 0000000..6144fba
--- /dev/null
+++ b/platform/msm_shared/rpm-smd.c
@@ -0,0 +1,182 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Fundation, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <rpm-smd.h>
+#include <smd.h>
+#include <stdint.h>
+#include <sys/types.h>
+#include <arch/defines.h>
+#include <debug.h>
+#include <stdlib.h>
+
+#define RPM_REQ_MAGIC 0x00716572
+#define RPM_CMD_MAGIC 0x00646d63
+#define REQ_MSG_LENGTH 0x14
+#define CMD_MSG_LENGTH 0x08
+#define ACK_MSG_LENGTH 0x0C
+
+static uint32_t msg_id;
+smd_channel_info_t ch;
+
+void rpm_smd_init()
+{
+	smd_init(&ch, SMD_APPS_RPM);
+}
+
+void rpm_smd_uninit()
+{
+	smd_uninit(&ch);
+}
+
+static void fill_kvp_object(kvp_data **kdata, uint32_t *data, uint32_t len)
+{
+	uint32_t i =0;
+
+	*kdata = (kvp_data *) memalign(CACHE_LINE, ROUNDUP(len, CACHE_LINE));
+	ASSERT(*kdata);
+
+	memcpy(*kdata, data+2, len);
+}
+
+static void free_kvp_object(kvp_data **kdata)
+{
+	if(*kdata)
+		free(*kdata);
+}
+
+int rpm_send_data(uint32_t *data, uint32_t len, msg_type type)
+{
+	rpm_req req;
+	rpm_cmd cmd;
+	uint32_t len_to_smd = 0;
+	int ret = 0;
+	uint32_t ack_msg_len = 0;
+	uint32_t rlen = 0;
+	void *smd_data = NULL;
+
+	switch(type)
+	{
+		case RPM_REQUEST_TYPE:
+			req.hdr.type = RPM_REQ_MAGIC;
+			req.hdr.len = len + REQ_MSG_LENGTH;//20
+			req.req_hdr.id = ++msg_id;
+			req.req_hdr.set = 0;//assume active set. check sleep set.
+			req.req_hdr.resourceType = data[RESOURCETYPE];
+			req.req_hdr.resourceId = data[RESOURCEID];
+			req.req_hdr.dataLength = len;
+
+			fill_kvp_object(&req.data, data, len);
+			len_to_smd = req.req_hdr.dataLength + 0x28;
+
+			smd_data = (void*) malloc(len_to_smd);
+			ASSERT(smd_data);
+
+			memcpy(smd_data, &req.hdr, sizeof(rpm_gen_hdr));
+			memcpy(smd_data + sizeof(rpm_gen_hdr), &req.req_hdr, sizeof(rpm_req_hdr));
+			memcpy(smd_data + sizeof(rpm_gen_hdr)+ sizeof(rpm_req_hdr), req.data, len);
+
+			ret = smd_write(&ch, smd_data, len_to_smd, SMD_APPS_RPM);
+
+			/* Read the response */
+			ack_msg_len = rpm_recv_data(&rlen);
+
+			smd_signal_read_complete(&ch, ack_msg_len);
+
+			free(smd_data);
+			free_kvp_object(&req.data);
+		break;
+		case RPM_CMD_TYPE:
+			cmd.hdr.type = RPM_CMD_MAGIC;
+			cmd.hdr.len = CMD_MSG_LENGTH;//0x8;
+			len_to_smd  = 0x12;
+
+			fill_kvp_object(&cmd.data, data, len);
+			ret = smd_write(&ch, (void *)&cmd, len_to_smd, SMD_APPS_RPM);
+
+			free_kvp_object(&cmd.data);
+		break;
+		default:
+		break;
+	}
+
+	return ret;
+}
+
+uint32_t rpm_recv_data(uint32_t* len)
+{
+	rpm_ack_msg *resp;
+	msg_type type;
+	uint32_t ret = 0;
+
+	resp = (rpm_ack_msg*)smd_read(&ch, len, SMD_APPS_RPM);
+
+	arch_invalidate_cache_range((addr_t)resp, sizeof(rpm_gen_hdr));
+
+	if(resp->hdr.type == RPM_CMD_MAGIC)
+	{
+		type = RPM_CMD_TYPE;
+	}
+	else if(resp->hdr.type == RPM_REQ_MAGIC)
+	{
+		type = RPM_REQUEST_TYPE;
+	}
+
+	if (type == RPM_CMD_TYPE && resp->hdr.len == ACK_MSG_LENGTH)
+	{
+		dprintf(SPEW, "Received SUCCESS CMD ACK\n");
+	}
+	else if (type == RPM_REQUEST_TYPE && resp->hdr.len == ACK_MSG_LENGTH)
+	{
+		dprintf(SPEW, "Received SUCCESS REQ ACK \n");
+	}
+	else
+	{
+		ret = 1;
+		dprintf(CRITICAL, "Received ERROR ACK \n");
+	}
+
+	if(!ret)
+	{
+		ret = sizeof(rpm_gen_hdr) + sizeof(kvp_data);
+	}
+
+	return ret;
+}
+
+void rpm_clk_enable(uint32_t *data, uint32_t len)
+{
+	/* Send the request to SMD */
+	rpm_send_data(data, len, RPM_REQUEST_TYPE);
+}
+
+void rpm_clk_disable(uint32_t *data, uint32_t len)
+{
+	dprintf(CRITICAL,"Clock disable\n");
+}
+
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index 9b03643..f5f6dce 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -16,6 +16,13 @@
 	$(LOCAL_DIR)/hsusb.o \
 	$(LOCAL_DIR)/boot_stats.o
 
+ifeq ($(ENABLE_SMD_SUPPORT),1)
+OBJS += \
+	$(LOCAL_DIR)/rpm-smd.o \
+	$(LOCAL_DIR)/smd.o \
+	$(LOCAL_DIR)/regulator.o
+endif
+
 ifeq ($(ENABLE_SDHCI_SUPPORT),1)
 OBJS += \
 	$(LOCAL_DIR)/sdhci.o \
@@ -371,7 +378,33 @@
 			$(LOCAL_DIR)/dload_util.o
 endif
 
+ifeq ($(PLATFORM),fsm9010)
+	OBJS += $(LOCAL_DIR)/qgic.o \
+			$(LOCAL_DIR)/qtimer.o \
+			$(LOCAL_DIR)/qtimer_mmap.o \
+			$(LOCAL_DIR)/interrupts.o \
+			$(LOCAL_DIR)/clock.o \
+			$(LOCAL_DIR)/clock_pll.o \
+			$(LOCAL_DIR)/clock_lib2.o \
+			$(LOCAL_DIR)/uart_dm.o \
+			$(LOCAL_DIR)/board.o \
+			$(LOCAL_DIR)/scm.o \
+			$(LOCAL_DIR)/spmi.o \
+			$(LOCAL_DIR)/bam.o \
+			$(LOCAL_DIR)/qpic_nand.o \
+			$(LOCAL_DIR)/dev_tree.o \
+			$(LOCAL_DIR)/certificate.o \
+			$(LOCAL_DIR)/image_verify.o \
+			$(LOCAL_DIR)/crypto_hash.o \
+			$(LOCAL_DIR)/crypto5_eng.o \
+			$(LOCAL_DIR)/crypto5_wrapper.o \
+			$(LOCAL_DIR)/i2c_qup.o \
+			$(LOCAL_DIR)/gpio.o \
+			$(LOCAL_DIR)/dload_util.o
+endif
+
 ifeq ($(PLATFORM),msm8994)
+DEFINES += DISPLAY_TYPE_MDSS=1
 	OBJS += $(LOCAL_DIR)/qgic.o \
 			$(LOCAL_DIR)/qtimer.o \
 			$(LOCAL_DIR)/qtimer_mmap.o \
@@ -399,7 +432,31 @@
 			$(LOCAL_DIR)/crypto_hash.o \
 			$(LOCAL_DIR)/crypto5_eng.o \
 			$(LOCAL_DIR)/crypto5_wrapper.o \
-			$(LOCAL_DIR)/qusb2_phy.o
+			$(LOCAL_DIR)/qusb2_phy.o \
+			$(LOCAL_DIR)/mdp5.o \
+			$(LOCAL_DIR)/display.o \
+			$(LOCAL_DIR)/mipi_dsi.o \
+			$(LOCAL_DIR)/mipi_dsi_phy.o \
+			$(LOCAL_DIR)/mipi_dsi_autopll.o \
+			$(LOCAL_DIR)/mipi_dsi_autopll_20nm.o
+endif
+
+ifeq ($(PLATFORM),ferrum)
+	OBJS += $(LOCAL_DIR)/qgic.o \
+			$(LOCAL_DIR)/qtimer.o \
+			$(LOCAL_DIR)/qtimer_mmap.o \
+			$(LOCAL_DIR)/interrupts.o \
+			$(LOCAL_DIR)/clock.o \
+			$(LOCAL_DIR)/clock_pll.o \
+			$(LOCAL_DIR)/clock_lib2.o \
+			$(LOCAL_DIR)/uart_dm.o \
+			$(LOCAL_DIR)/board.o \
+			$(LOCAL_DIR)/spmi.o \
+			$(LOCAL_DIR)/bam.o \
+			$(LOCAL_DIR)/qpic_nand.o \
+			$(LOCAL_DIR)/scm.o \
+			$(LOCAL_DIR)/dev_tree.o \
+			$(LOCAL_DIR)/gpio.o
 endif
 
 ifeq ($(ENABLE_BOOT_CONFIG_SUPPORT), 1)
diff --git a/platform/msm_shared/sdhci.c b/platform/msm_shared/sdhci.c
index fd7b5ae..e9f4e0d 100644
--- a/platform/msm_shared/sdhci.c
+++ b/platform/msm_shared/sdhci.c
@@ -458,7 +458,7 @@
 		}
 
 		retry++;
-		udelay(500);
+		udelay(1);
 		if (retry == SDHCI_MAX_CMD_RETRY) {
 			dprintf(CRITICAL, "Error: Command never completed\n");
 			ret = 1;
@@ -520,7 +520,7 @@
 			}
 
 			retry++;
-			udelay(1000);
+			udelay(1);
 			if (retry == max_trans_retry) {
 				dprintf(CRITICAL, "Error: Transfer never completed\n");
 				ret = 1;
@@ -842,7 +842,14 @@
 		trans_mode |= SDHCI_DMA_EN;
 
 		if (cmd->trans_mode == SDHCI_MMC_READ)
+		{
 			trans_mode |= SDHCI_READ_MODE;
+			sdhci_msm_toggle_cdr(host, true);
+		}
+		else
+		{
+			sdhci_msm_toggle_cdr(host, false);
+		}
 
 		/* Enable auto cmd23 or cmd12 for multi block transfer
 		 * based on what command card supports
diff --git a/platform/msm_shared/sdhci_msm.c b/platform/msm_shared/sdhci_msm.c
index 9e6fc6c..5a7795f 100644
--- a/platform/msm_shared/sdhci_msm.c
+++ b/platform/msm_shared/sdhci_msm.c
@@ -286,7 +286,7 @@
 	/* Write 1 to CLK_OUT_EN */
 	REG_WRITE32(host, (REG_READ32(host, SDCC_DLL_CONFIG_REG) | SDCC_DLL_CLK_OUT_EN), SDCC_DLL_CONFIG_REG);
 	/* Wait for DLL_LOCK in DLL_STATUS register, wait time 50us */
-	while(!((REG_READ32(host, SDCC_REG_DLL_STATUS)) & SDCC_DLL_LOCK_STAT));
+	while(!((REG_READ32(host, SDCC_REG_DLL_STATUS)) & SDCC_DLL_LOCK_STAT))
 	{
 		udelay(1);
 		timeout--;
@@ -304,6 +304,24 @@
 	return 0;
 }
 
+void sdhci_msm_toggle_cdr(struct sdhci_host *host, bool enable)
+{
+	uint32_t core_cfg;
+
+	core_cfg = REG_READ32(host, SDCC_DLL_CONFIG_REG);
+
+	if (enable)
+	{
+		core_cfg |= SDCC_DLL_CDR_EN;
+	}
+	else
+	{
+		core_cfg &= ~SDCC_DLL_CDR_EN;
+	}
+
+	REG_WRITE32(host, core_cfg, SDCC_DLL_CONFIG_REG);
+}
+
 /* Configure DLL with delay value based on 'phase' */
 static uint32_t sdhci_msm_config_dll(struct sdhci_host *host, uint32_t phase)
 {
diff --git a/platform/msm_shared/smd.c b/platform/msm_shared/smd.c
new file mode 100644
index 0000000..dfb5b62
--- /dev/null
+++ b/platform/msm_shared/smd.c
@@ -0,0 +1,377 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Fundation, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <smd.h>
+#include <smem.h>
+#include <debug.h>
+#include <platform/irqs.h>
+#include <platform/iomap.h>
+#include <platform/interrupts.h>
+#include <reg.h>
+#include <malloc.h>
+#include <bits.h>
+
+smd_channel_alloc_entry_t *smd_channel_alloc_entry;
+
+
+static void smd_write_state(smd_channel_info_t *ch, uint32_t state)
+{
+	if(state == SMD_SS_OPENED)
+	{
+		ch->port_info->ch0.DTR_DSR = 1;
+		ch->port_info->ch0.CTS_RTS = 1;
+		ch->port_info->ch0.CD = 1;
+	}
+	else
+	{
+		ch->port_info->ch0.DTR_DSR = 0;
+		ch->port_info->ch0.CTS_RTS = 0;
+		ch->port_info->ch0.CD = 0;
+	}
+
+	ch->port_info->ch0.stream_state = state;
+}
+
+static void smd_state_update(smd_channel_info_t *ch, uint32_t flag)
+{
+	ch->port_info->ch0.state_updated = flag;
+}
+
+void smd_get_channel_entry(smd_channel_info_t *ch, uint32_t ch_type)
+{
+	int i = 0;
+
+	for(i = 0; i< SMEM_NUM_SMD_STREAM_CHANNELS; i++)
+	{
+		if((smd_channel_alloc_entry[i].ctype & 0xFF) == ch_type)
+		{
+			memcpy(&ch->alloc_entry, &smd_channel_alloc_entry[i], sizeof(smd_channel_alloc_entry_t));
+			break;
+		}
+	}
+
+	/* Channel not found */
+	if(i == SMEM_NUM_SMD_STREAM_CHANNELS)
+	{
+		dprintf(CRITICAL, "smd channel type %x not found\n", ch_type);
+		ASSERT(0);
+	}
+}
+
+int smd_get_channel_info(smd_channel_info_t *ch, uint32_t ch_type)
+{
+	int ret = 0;
+	uint8_t *fifo_buf = NULL;
+	uint32_t fifo_buf_size = 0;
+	uint32_t size = 0;
+
+	smd_get_channel_entry(ch, ch_type);
+
+
+	ch->port_info = smem_get_alloc_entry(SMEM_SMD_BASE_ID + ch->alloc_entry.cid,
+										 &size);
+
+	fifo_buf = smem_get_alloc_entry(SMEM_SMD_FIFO_BASE_ID + ch->alloc_entry.cid,
+									&fifo_buf_size);
+
+	fifo_buf_size /= 2;
+	ch->send_buf = fifo_buf;
+	ch->recv_buf = fifo_buf + fifo_buf_size;
+	ch->fifo_size = fifo_buf_size;
+
+	return ret;
+}
+
+int smd_init(smd_channel_info_t *ch, uint32_t ch_type)
+{
+	unsigned ret = 0;
+
+	smd_channel_alloc_entry = (smd_channel_alloc_entry_t*)memalign(CACHE_LINE, SMD_CHANNEL_ALLOC_MAX);
+	ASSERT(smd_channel_alloc_entry);
+
+	ret = smem_read_alloc_entry(SMEM_CHANNEL_ALLOC_TBL,
+							(void*)smd_channel_alloc_entry,
+							SMD_CHANNEL_ALLOC_MAX);
+	if(ret)
+	{
+		dprintf(CRITICAL,"ERROR reading smem channel alloc tbl\n");
+		return -1;
+	}
+
+	smd_get_channel_info(ch, ch_type);
+
+	register_int_handler(SMD_IRQ, smd_irq_handler, ch);
+	unmask_interrupt(SMD_IRQ);
+
+	smd_set_state(ch, SMD_SS_OPENING, 1);
+
+	smd_notify_rpm();
+
+	return 0;
+}
+
+void smd_uninit(smd_channel_info_t *ch)
+{
+	smd_set_state(ch, SMD_SS_CLOSING, 1);
+
+	smd_notify_rpm();
+}
+
+bool is_channel_open(smd_channel_info_t *ch)
+{
+	if(ch->port_info->ch0.stream_state == SMD_SS_OPENED &&
+	  (ch->port_info->ch1.stream_state == SMD_SS_OPENED ||
+	   ch->port_info->ch1.stream_state == SMD_SS_FLUSHING))
+		return true;
+	else
+		return false;
+}
+
+uint8_t* smd_read(smd_channel_info_t *ch, uint32_t *len, int ch_type)
+{
+	smd_pkt_hdr smd_hdr;
+	uint32_t size = 0;
+
+	/* Read the indices from smem */
+	ch->port_info = smem_get_alloc_entry(SMEM_SMD_BASE_ID + ch->alloc_entry.cid,
+										 &size);
+	if(!ch->port_info->ch1.DTR_DSR)
+	{
+		dprintf(CRITICAL,"%s: DTR is off\n", __func__);
+		return -1;
+	}
+
+	/* Wait until the data updated in the smd buffer is equal to smd packet header*/
+	while ((ch->port_info->ch1.write_index - ch->port_info->ch1.read_index) < sizeof(smd_pkt_hdr))
+	{
+		/* Get the update info from memory */
+		arch_invalidate_cache_range((addr_t) ch->port_info, size);
+
+		if ((ch->port_info->ch1.read_index + sizeof(smd_pkt_hdr)) >= ch->fifo_size)
+		{
+			dprintf(CRITICAL, "At %d:%s:RX channel read index [%u] is greater than RX fifo size[%u]\n",
+							   __LINE__,__func__, ch->port_info->ch1.read_index, ch->fifo_size);
+			return -1;
+		}
+	}
+
+
+	arch_invalidate_cache_range((addr_t)(ch->recv_buf + ch->port_info->ch1.read_index), sizeof(smd_hdr));
+
+	/* Copy the smd buffer to local buf */
+	memcpy(&smd_hdr, (void*)(ch->recv_buf + ch->port_info->ch1.read_index), sizeof(smd_hdr));
+
+	*len = smd_hdr.pkt_size;
+
+	/* Wait on the data being updated in SMEM before returing the response */
+	while ((ch->port_info->ch1.write_index - ch->port_info->ch1.read_index) < smd_hdr.pkt_size)
+	{
+		/* Get the update info from memory */
+		arch_invalidate_cache_range((addr_t) ch->port_info, size);
+
+		if ((ch->port_info->ch1.read_index + sizeof(smd_hdr) + smd_hdr.pkt_size) >= ch->fifo_size)
+		{
+			dprintf(CRITICAL, "At %d:%s:RX channel read index [%u] is greater than RX fifo size[%u]\n",
+							   __LINE__,__func__, ch->port_info->ch1.read_index, ch->fifo_size);
+			return -1;
+		}
+	}
+
+	/* We are good to return the response now */
+	return (uint8_t*)(ch->recv_buf + ch->port_info->ch1.read_index + sizeof(smd_hdr));
+}
+
+void smd_signal_read_complete(smd_channel_info_t *ch, uint32_t len)
+{
+	ch->port_info->ch1.read_index += sizeof(smd_pkt_hdr) + len;
+
+	/* Clear the data_written flag */
+	ch->port_info->ch1.data_written = 0;
+
+	/* Set the data_read flag */
+	ch->port_info->ch0.data_read = 1;
+	ch->port_info->ch0.mask_recv_intr = 1;
+
+	dsb();
+
+	smd_notify_rpm();
+}
+
+int smd_write(smd_channel_info_t *ch, void *data, uint32_t len, int ch_type)
+{
+	smd_pkt_hdr smd_hdr;
+	uint32_t size = 0;
+
+	memset(&smd_hdr, 0, sizeof(smd_pkt_hdr));
+
+	if(len + sizeof(smd_hdr) > ch->fifo_size)
+	{
+		dprintf(CRITICAL,"%s: len is greater than fifo sz\n", __func__);
+		return -1;
+	}
+
+	/* Read the indices from smem */
+	ch->port_info = smem_get_alloc_entry(SMEM_SMD_BASE_ID + ch->alloc_entry.cid,
+                                                        &size);
+
+	if(!is_channel_open(ch))
+	{
+		dprintf(CRITICAL,"%s: channel is not in OPEN state \n", __func__);
+		return -1;
+	}
+
+	if(!ch->port_info->ch0.DTR_DSR)
+	{
+		dprintf(CRITICAL,"%s: DTR is off\n", __func__);
+		return -1;
+	}
+
+	/* Clear the data_read flag */
+	ch->port_info->ch1.data_read = 0;
+
+	/*copy the local buf to smd buf */
+	smd_hdr.pkt_size = len;
+
+	memcpy(ch->send_buf + ch->port_info->ch0.write_index, &smd_hdr, sizeof(smd_hdr));
+
+	memcpy(ch->send_buf + ch->port_info->ch0.write_index + sizeof(smd_hdr), data, len);
+
+	arch_invalidate_cache_range((addr_t)ch->send_buf+ch->port_info->ch0.write_index, sizeof(smd_hdr) + len);
+
+	/* Update write index */
+	ch->port_info->ch0.write_index += sizeof(smd_hdr) + len;
+
+	dsb();
+
+	/* Set the necessary flags */
+
+	ch->port_info->ch0.data_written = 1;
+	ch->port_info->ch0.mask_recv_intr = 0;
+
+	dsb();
+
+	smd_notify_rpm();
+
+	return 0;
+}
+
+void smd_notify_rpm()
+{
+	/* Set BIT 0 to notify RPM via IPC interrupt*/
+	writel(BIT(0), APCS_ALIAS0_IPC_INTERRUPT);
+}
+
+void smd_set_state(smd_channel_info_t *ch, uint32_t state, uint32_t flag)
+{
+	uint32_t current_state;
+	uint32_t size = 0;
+
+	if(!ch->port_info)
+	{
+		ch->port_info = smem_get_alloc_entry(SMEM_SMD_BASE_ID + ch->alloc_entry.cid,
+							&size);
+		ASSERT(ch->port_info);
+	}
+
+	current_state = ch->port_info->ch0.stream_state;
+
+	switch(state)
+	{
+		case SMD_SS_CLOSED:
+		if(current_state == SMD_SS_OPENED)
+		{
+			smd_write_state(ch, SMD_SS_CLOSING);
+		}
+		else
+		{
+			smd_write_state(ch, SMD_SS_CLOSED);
+		}
+		break;
+		case SMD_SS_OPENING:
+		if(current_state == SMD_SS_CLOSING || current_state == SMD_SS_CLOSED)
+		{
+			smd_write_state(ch, SMD_SS_OPENING);
+			ch->port_info->ch1.read_index = 0;
+			ch->port_info->ch0.write_index = 0;
+			ch->port_info->ch0.mask_recv_intr = 0;
+		}
+		break;
+		case SMD_SS_OPENED:
+		if(current_state == SMD_SS_OPENING)
+		{
+			smd_write_state(ch, SMD_SS_OPENED);
+		}
+		break;
+		case SMD_SS_CLOSING:
+		if(current_state == SMD_SS_OPENED)
+		{
+			smd_write_state(ch, SMD_SS_CLOSING);
+		}
+		break;
+		case SMD_SS_FLUSHING:
+		case SMD_SS_RESET:
+		case SMD_SS_RESET_OPENING:
+		default:
+		break;
+	}
+
+	ch->current_state = state;
+
+	smd_state_update(ch, flag);
+}
+
+
+enum handler_return smd_irq_handler(void* data)
+{
+	smd_channel_info_t *ch = (smd_channel_info_t*)data;
+
+	if(ch->current_state == SMD_SS_CLOSED)
+	{
+		free(smd_channel_alloc_entry);
+		return INT_NO_RESCHEDULE;
+	}
+
+	if(ch->port_info->ch1.state_updated)
+		ch->port_info->ch1.state_updated = 0;
+
+	/* Should we have to use a do while and change states until we complete */
+	if(ch->current_state != ch->port_info->ch1.stream_state)
+	{
+		smd_set_state(ch, ch->port_info->ch1.stream_state, 0);
+	}
+
+	if(ch->current_state == SMD_SS_CLOSING)
+	{
+		smd_set_state(ch, SMD_SS_CLOSED, 1);
+		smd_notify_rpm();
+		dprintf(CRITICAL,"Channel alloc freed\n");
+	}
+
+	return INT_NO_RESCHEDULE;
+}
diff --git a/platform/msm_shared/smem.c b/platform/msm_shared/smem.c
index dc1b141..948a256 100644
--- a/platform/msm_shared/smem.c
+++ b/platform/msm_shared/smem.c
@@ -37,6 +37,26 @@
 
 static struct smem *smem;
 
+/* DYNAMIC SMEM REGION feature enables LK to dynamically
+ * read the SMEM addr info from TCSR register or IMEM location.
+ * The first word read, if indicates a MAGIC number, then
+ * Dynamic SMEM is assumed to be enabled. Read the remaining
+ * SMEM info for SMEM Size and Phy_addr from the other bytes.
+ */
+
+#if DYNAMIC_SMEM
+uint32_t smem_get_base_addr()
+{
+	struct smem_addr_info *smem_info = NULL;
+
+	smem_info = (struct smem_addr_info *) SMEM_TARG_INFO_ADDR;
+	if(smem_info && (smem_info->identifier == SMEM_TARGET_INFO_IDENTIFIER))
+		return smem_info->phy_addr;
+	else
+		return MSM_SHARED_BASE;
+}
+#endif
+
 /* buf MUST be 4byte aligned, and len MUST be a multiple of 8. */
 unsigned smem_read_alloc_entry(smem_mem_type_t type, void *buf, int len)
 {
@@ -46,7 +66,11 @@
 	unsigned size;
 	uint32_t smem_addr = 0;
 
+#if DYNAMIC_SMEM
+	smem_addr = smem_get_base_addr();
+#else
 	smem_addr = platform_get_smem_base_addr();
+#endif
 
 	smem = (struct smem *)smem_addr;
 
@@ -73,6 +97,45 @@
 	return 0;
 }
 
+/* Return a pointer to smem_item with size */
+void* smem_get_alloc_entry(smem_mem_type_t type, uint32_t* size)
+{
+	struct smem_alloc_info *ainfo = NULL;
+	uint32_t smem_addr = 0;
+	uint32_t base_ext = 0;
+	uint32_t offset = 0;
+	void *ret = 0;
+
+#if DYNAMIC_SMEM
+	smem_addr = smem_get_base_addr();
+#else
+	smem_addr = platform_get_smem_base_addr();
+#endif
+	smem = (struct smem *)smem_addr;
+
+	if (type < SMEM_FIRST_VALID_TYPE || type > SMEM_LAST_VALID_TYPE)
+		return 1;
+
+	ainfo = &smem->alloc_info[type];
+	if (readl(&ainfo->allocated) == 0)
+		return 1;
+
+	*size = readl(&ainfo->size);
+	base_ext = readl(&ainfo->base_ext);
+	offset = readl(&ainfo->offset);
+
+	if(base_ext)
+	{
+		ret = base_ext + offset;
+	}
+	else
+	{
+		ret = (void*) smem_addr + offset;
+	}
+
+	return ret;
+}
+
 unsigned
 smem_read_alloc_entry_offset(smem_mem_type_t type, void *buf, int len,
 			     int offset)
@@ -83,7 +146,11 @@
 	unsigned size = len;
 	uint32_t smem_addr = 0;
 
+#if DYNAMIC_SMEM
+	smem_addr = smem_get_base_addr();
+#else
 	smem_addr = platform_get_smem_base_addr();
+#endif
 
 	smem = (struct smem *)smem_addr;
 
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index e2ac883..14925f5 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -47,6 +47,8 @@
 
 #define SMEM_TARGET_INFO_IDENTIFIER     0x49494953
 
+#define SMEM_NUM_SMD_STREAM_CHANNELS        64
+
 enum smem_ram_ptable_version
 {
 	SMEM_RAM_PTABLE_VERSION_0,
@@ -71,7 +73,7 @@
 	unsigned allocated;
 	unsigned offset;
 	unsigned size;
-	unsigned reserved;
+	unsigned base_ext;
 };
 
 struct smem_board_info_v2 {
@@ -186,7 +188,7 @@
 	 * Need for 8 bytes alignment
 	 * while reading from shared memory
 	 */
-	unsigned buffer_align;
+	uint32_t foundry_id; /* Used as foundry_id only for v9 and used as an alignment field for v8 */
 };
 
 typedef struct {
@@ -363,10 +365,16 @@
 	APQ8039  = 241,
 	MSM8236  = 242,
 	MSM8636  = 243,
+	MSM8909  = 245,
 	APQ8016  = 247,
 	MSM8216  = 248,
 	MSM8116  = 249,
 	MSM8616  = 250,
+	APQ8094  = 253,
+	FSM9008  = 254,
+	FSM9010  = 255,
+	FSM9016  = 256,
+	FSM9055  = 257,
 };
 
 enum platform {
@@ -409,13 +417,16 @@
 
 typedef enum {
 	SMEM_SPINLOCK_ARRAY = 7,
-
 	SMEM_AARM_PARTITION_TABLE = 9,
+	SMEM_CHANNEL_ALLOC_TBL = 13,
+	SMEM_SMD_BASE_ID = 14,
 
 	SMEM_APPS_BOOT_MODE = 106,
 
 	SMEM_BOARD_INFO_LOCATION = 137,
 
+	SMEM_SMD_FIFO_BASE_ID = 338,
+
 	SMEM_USABLE_RAM_PARTITION_TABLE = 402,
 
 	SMEM_POWER_ON_STATUS_INFO = 403,
@@ -565,4 +576,5 @@
 void smem_get_ram_ptable_entry(ram_partition*, uint32_t entry);
 uint32_t smem_get_ram_ptable_version(void);
 uint32_t smem_get_ram_ptable_len(void);
+void* smem_get_alloc_entry(smem_mem_type_t type, uint32_t* size);
 #endif				/* __PLATFORM_MSM_SHARED_SMEM_H */
diff --git a/platform/msm_shared/usb30_dwc.c b/platform/msm_shared/usb30_dwc.c
index 46b7ae4..df1442b 100644
--- a/platform/msm_shared/usb30_dwc.c
+++ b/platform/msm_shared/usb30_dwc.c
@@ -489,8 +489,9 @@
 	uint8_t                 event_status = DWC_EVENT_EP_EVENT_STATUS(*event);
 	uint16_t                event_param  = DWC_EVENT_EP_EVENT_PARAM(*event);
 
+	ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
 	dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
-#endif
+	ASSERT(ep != NULL);
 
 	DBG("\n\n\n++EP_EVENT: %s in ctrl_state: %s ep_state[%d]: %s",
 		event_lookup_ep[event_id],
@@ -501,7 +502,7 @@
 	DBG("\n ep_phy_num = %d param = 0x%x status = 0x%x", ep_phy_num,
 														 event_param,
 														 event_status);
-
+#endif
 
 	/* call the handler for the current control state */
 	switch (dev->ctrl_state)
@@ -549,11 +550,13 @@
 		ASSERT(0);
 	}
 
+#ifdef DEBUG_USB
 	DBG("\n--EP_EVENT: %s in ctrl_state: %s ep_state[%d]: %s",
 		event_lookup_ep[event_id],
 		dev_ctrl_state_lookup[dev->ctrl_state],
 		ep_phy_num,
 		ep_state_lookup[ep->state]);
+#endif
 }
 
 /* check status of transfer:
@@ -638,7 +641,9 @@
 	dwc_event_ep_event_id_t event_id   = DWC_EVENT_EP_EVENT_ID(*event);
 	uint8_t event_status               = DWC_EVENT_EP_EVENT_STATUS(*event);
 
+	ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
 	dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+	ASSERT(ep != NULL);
 
 	switch (event_id)
 	{
@@ -751,7 +756,9 @@
 	uint8_t event_ctrl_stage           = DWC_EVENT_EP_EVENT_CTRL_STAGE(*event);
 	uint8_t event_status               = DWC_EVENT_EP_EVENT_STATUS(*event);
 
+	ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
 	dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+	ASSERT(ep != NULL);
 
 	switch (event_id)
 	{
@@ -985,7 +992,9 @@
 	dwc_event_ep_event_id_t event_id   = DWC_EVENT_EP_EVENT_ID(*event);
 	uint8_t event_status               = DWC_EVENT_EP_EVENT_STATUS(*event);
 
+	ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
 	dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+	ASSERT(ep != NULL);
 
 	switch (event_id)
 	{
@@ -1057,7 +1066,9 @@
 	dwc_event_ep_event_id_t event_id   = DWC_EVENT_EP_EVENT_ID(*event);
 	uint8_t event_status               = DWC_EVENT_EP_EVENT_STATUS(*event);
 
+	ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
 	dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+	ASSERT(ep != NULL);
 
 	switch (event_id)
 	{
@@ -1134,7 +1145,9 @@
 	uint8_t ep_phy_num                 = DWC_EVENT_EP_EVENT_EP_NUM(*event);
 	dwc_event_ep_event_id_t event_id   = DWC_EVENT_EP_EVENT_ID(*event);
 
+	ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
 	dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+	ASSERT(ep != NULL);
 
 	switch (event_id)
 	{
@@ -1169,10 +1182,8 @@
 static void dwc_event_handler_ep_bulk_state_inactive(dwc_dev_t *dev,
 													 uint32_t *event)
 {
-#ifdef DEBUG_USB
 	uint8_t ep_phy_num                 = DWC_EVENT_EP_EVENT_EP_NUM(*event);
 	dwc_dep_cmd_id_t cmd               = DWC_EVENT_EP_EVENT_CMD_TYPE(*event);
-#endif
 	dwc_event_ep_event_id_t event_id   = DWC_EVENT_EP_EVENT_ID(*event);
 
 	switch (event_id)
@@ -1209,7 +1220,9 @@
 	dwc_event_ep_event_id_t event_id   = DWC_EVENT_EP_EVENT_ID(*event);
 	uint8_t event_status               = DWC_EVENT_EP_EVENT_STATUS(*event);
 
+	ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
 	dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+	ASSERT(ep != NULL);
 
 	switch (event_id)
 	{
@@ -1257,7 +1270,9 @@
 	uint8_t ep_phy_num                 = DWC_EVENT_EP_EVENT_EP_NUM(*event);
 	dwc_event_ep_event_id_t event_id   = DWC_EVENT_EP_EVENT_ID(*event);
 
+	ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
 	dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+	ASSERT(ep != NULL);
 
 	switch (event_id)
 	{
@@ -1339,9 +1354,11 @@
 	uint16_t                event_param  = DWC_EVENT_EP_EVENT_PARAM(*event);
 #endif
 
-
+	ASSERT(ep_phy_num < DWC_MAX_NUM_OF_EP);
 	dwc_ep_t *ep = &dev->ep[DWC_EP_PHY_TO_INDEX(ep_phy_num)];
+	ASSERT(ep != NULL);
 
+#ifdef DEBUG_USB
 	DBG("\n\n\n++EP_EVENT: %s in ctrl_state: %s ep_state[%d]: %s",
 		event_lookup_ep[event_id],
 		dev_ctrl_state_lookup[dev->ctrl_state],
@@ -1350,6 +1367,7 @@
 
 	DBG("\n ep_phy_num = %d param = 0x%x status = 0x%x",
 			ep_phy_num, event_param, event_status);
+#endif
 
 	switch (ep->state)
 	{
@@ -1375,11 +1393,13 @@
 		ASSERT(0);
 	}
 
+#ifdef DEBUG_USB
 	DBG("\n--EP_EVENT: %s in ctrl_state: %s ep_state[%d]: %s",
 		event_lookup_ep[event_id],
 		dev_ctrl_state_lookup[dev->ctrl_state],
 		ep_phy_num,
 		ep_state_lookup[ep->state]);
+#endif
 }
 
 
diff --git a/platform/msmzirc/include/platform/iomap.h b/platform/msmzirc/include/platform/iomap.h
index e3962ba..f8e9cf3 100644
--- a/platform/msmzirc/include/platform/iomap.h
+++ b/platform/msmzirc/include/platform/iomap.h
@@ -139,6 +139,7 @@
 #define USB_HS_AHB_CBCR             (CLK_CTL_BASE + 0x41008)
 #define USB_HS_SYSTEM_CMD_RCGR      (CLK_CTL_BASE + 0x41010)
 #define USB_HS_SYSTEM_CFG_RCGR      (CLK_CTL_BASE + 0x41014)
+#define QUSB2A_PHY_BCR              (CLK_CTL_BASE + 0x41028)
 
 /* USB 3.0 clock */
 #define SYS_NOC_USB3_AXI_CBCR       (CLK_CTL_BASE + 0x5E084)
@@ -170,6 +171,11 @@
 #define QUSB2_PHY_BASE              0x00079000
 #define QUSB2PHY_PORT_POWERDOWN     (QUSB2_PHY_BASE + 0x000000B4)
 #define GCC_QUSB2_PHY_BCR           (CLK_CTL_BASE + 0x00041028)
+#define QUSB2PHY_PORT_UTMI_CTRL2    (QUSB2_PHY_BASE + 0x000000C4)
+#define QUSB2PHY_PORT_TUNE1         (QUSB2_PHY_BASE + 0x00000080)
+#define QUSB2PHY_PORT_TUNE2         (QUSB2_PHY_BASE + 0x00000084)
+#define QUSB2PHY_PORT_TUNE3         (QUSB2_PHY_BASE + 0x00000088)
+#define QUSB2PHY_PORT_TUNE4         (QUSB2_PHY_BASE + 0x0000008C)
 
 /* SS QMP (Qulacomm Multi Protocol) */
 #define QMP_PHY_BASE                0x78000
diff --git a/platform/msmzirc/msmzirc-clock.c b/platform/msmzirc/msmzirc-clock.c
index aee1076..ca97cb0 100644
--- a/platform/msmzirc/msmzirc-clock.c
+++ b/platform/msmzirc/msmzirc-clock.c
@@ -357,6 +357,15 @@
 	},
 };
 
+static struct reset_clk gcc_usb2a_phy_sleep_clk = {
+	.bcr_reg = (uint32_t *) QUSB2A_PHY_BCR,
+
+	.c = {
+		.dbg_name = "usb2b_phy_sleep_clk",
+		.ops      = &clk_ops_reset,
+	},
+};
+
 static struct clk_lookup msm_clocks_zirc[] =
 {
 	CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
@@ -370,6 +379,7 @@
 	CLK_LOOKUP("usb30_pipe_clk",   gcc_usb30_pipe_clk.c),
 	CLK_LOOKUP("usb30_aux_clk",    gcc_usb30_aux_clk.c),
 
+	CLK_LOOKUP("usb2b_phy_sleep_clk", gcc_usb2a_phy_sleep_clk.c),
 	CLK_LOOKUP("usb30_phy_reset",     gcc_usb30_phy_reset.c),
 
 	CLK_LOOKUP("usb_phy_cfg_ahb_clk", gcc_usb_phy_cfg_ahb_clk.c),
diff --git a/project/ferrum.mk b/project/ferrum.mk
new file mode 100644
index 0000000..e40bfff
--- /dev/null
+++ b/project/ferrum.mk
@@ -0,0 +1,36 @@
+# top level project rules for the ferrum project
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+TARGET := ferrum
+
+MODULES += app/aboot
+
+DEBUG := 1
+EMMC_BOOT := 1
+
+#DEFINES += WITH_DEBUG_DCC=1
+DEFINES += WITH_DEBUG_UART=1
+#DEFINES += WITH_DEBUG_FBCON=1
+DEFINES += DEVICE_TREE=1
+#DEFINES += MMC_BOOT_BAM=1
+#DEFINES += CRYPTO_BAM=1
+DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
+
+DEFINES += ABOOT_FORCE_KERNEL_ADDR=0x80008000
+DEFINES += ABOOT_FORCE_RAMDISK_ADDR=0x82000000
+DEFINES += ABOOT_FORCE_TAGS_ADDR=0x81E00000
+DEFINES += ABOOT_FORCE_KERNEL64_ADDR=0x00080000
+
+#Disable thumb mode
+ENABLE_THUMB := false
+
+ENABLE_SDHCI_SUPPORT := 1
+
+ifeq ($(ENABLE_SDHCI_SUPPORT),1)
+DEFINES += MMC_SDHCI_SUPPORT=1
+endif
+
+ifeq ($(EMMC_BOOT),1)
+DEFINES += _EMMC_BOOT=1
+endif
diff --git a/project/fsm9010.mk b/project/fsm9010.mk
new file mode 100644
index 0000000..1fa0a02
--- /dev/null
+++ b/project/fsm9010.mk
@@ -0,0 +1,30 @@
+# top level project rules for the fsm9010 project
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+TARGET := fsm9010
+
+MODULES += app/aboot
+
+DEBUG := 1
+EMMC_BOOT := 1
+ENABLE_SDHCI_SUPPORT := 0
+
+DEFINES += WITH_DEBUG_DCC=1
+DEFINES += WITH_DEBUG_UART=1
+#DEFINES += WITH_DEBUG_FBCON=1
+DEFINES += DEVICE_TREE=1
+#DEFINES += MMC_BOOT_BAM=1
+DEFINES += CRYPTO_BAM=1
+DEFINES += CRYPTO_REG_ACCESS=1
+
+#Disable thumb mode
+ENABLE_THUMB := false
+
+ifeq ($(EMMC_BOOT),1)
+DEFINES += _EMMC_BOOT=1
+endif
+
+ifeq ($(ENABLE_SDHCI_SUPPORT),1)
+DEFINES += MMC_SDHCI_SUPPORT=1
+endif
diff --git a/project/msm8916.mk b/project/msm8916.mk
index 0b76b89..201f173 100644
--- a/project/msm8916.mk
+++ b/project/msm8916.mk
@@ -26,7 +26,7 @@
 DEFINES += ABOOT_FORCE_TAGS_ADDR=0x81E00000
 
 #Enable the feature of long press power on
-DEFINES += LONG_PRESS_POWER_ON=0
+DEFINES += LONG_PRESS_POWER_ON=1
 
 #Disable thumb mode
 ENABLE_THUMB := false
@@ -48,3 +48,6 @@
 ifeq ($(ENABLE_PON_VIB_SUPPORT),true)
 DEFINES += PON_VIB_SUPPORT=1
 endif
+
+#enable user force reset feature
+DEFINES += USER_FORCE_RESET_SUPPORT=1
diff --git a/project/msm8994.mk b/project/msm8994.mk
index 7bbc4c2..bf22317 100644
--- a/project/msm8994.mk
+++ b/project/msm8994.mk
@@ -12,6 +12,9 @@
 ENABLE_UFS_SUPPORT   := 1
 ENABLE_BOOT_CONFIG_SUPPORT := 1
 ENABLE_USB30_SUPPORT := 1
+USE_DYNAMIC_SMEM := 1
+ENABLE_SMD_SUPPORT := 1
+ENABLE_PWM_SUPPORT := true
 
 #DEFINES += WITH_DEBUG_DCC=1
 DEFINES += WITH_DEBUG_UART=1
@@ -44,3 +47,11 @@
 ifeq ($(ENABLE_USB30_SUPPORT),1)
 DEFINES += USB30_SUPPORT=1
 endif
+
+ifeq ($(USE_DYNAMIC_SMEM),1)
+DEFINES += DYNAMIC_SMEM=1
+endif
+
+ifeq ($(ENABLE_SMD_SUPPORT),1)
+DEFINES += SMD_SUPPORT=1
+endif
diff --git a/target/apq8084/target_display.c b/target/apq8084/target_display.c
index 3aa2379..1dd3a66 100755
--- a/target/apq8084/target_display.c
+++ b/target/apq8084/target_display.c
@@ -382,7 +382,7 @@
 		buf_size -= LK_OVERRIDE_PANEL_LEN;
 		strlcat(pbuf, HDMI_CONTROLLER_STRING, buf_size);
 	} else {
-		ret = gcdb_display_cmdline_arg(pbuf, buf_size);
+		ret = gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
 	}
 
 	return ret;
@@ -394,20 +394,20 @@
 
 	panel_name += strspn(panel_name, " ");
 
-	if (!strcmp(panel_name, NO_PANEL_CONFIG)) {
-		dprintf(INFO, "Skip panel configuration\n");
+	if ((!strcmp(panel_name, NO_PANEL_CONFIG))
+			|| (!strcmp(panel_name, SIM_VIDEO_PANEL))
+			|| (!strcmp(panel_name, SIM_DUALDSI_VIDEO_PANEL))) {
+		dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n",
+								panel_name);
 		return;
-	}
-
-	if (!strcmp(panel_name, HDMI_PANEL_NAME)) {
+	} else if (!strcmp(panel_name, HDMI_PANEL_NAME)) {
 		dprintf(INFO, "%s: HDMI is primary\n", __func__);
 		return;
 	}
 
 	ret = gcdb_display_init(panel_name, MDP_REV_50, MIPI_FB_ADDR);
-	if (ret) {
+	if (ret)
 		msm_display_off();
-	}
 }
 
 void target_display_shutdown(void)
diff --git a/target/ferrum/init.c b/target/ferrum/init.c
new file mode 100644
index 0000000..5e87b2e
--- /dev/null
+++ b/target/ferrum/init.c
@@ -0,0 +1,172 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <platform/iomap.h>
+#include <reg.h>
+#include <target.h>
+#include <platform.h>
+#include <uart_dm.h>
+#include <mmc.h>
+#include <dev/keys.h>
+#include <spmi_v2.h>
+#include <pm8x41.h>
+#include <board.h>
+#include <baseband.h>
+#include <hsusb.h>
+#include <scm.h>
+#include <platform/gpio.h>
+#include <platform/irqs.h>
+#include <platform/clock.h>
+#include <crypto5_wrapper.h>
+#include <partition_parser.h>
+#include <stdlib.h>
+#include <gpio.h>
+
+#define PMIC_ARB_CHANNEL_NUM    0
+#define PMIC_ARB_OWNER_ID       0
+
+
+struct mmc_device *dev;
+
+static uint32_t mmc_pwrctl_base[] =
+	{ MSM_SDC1_BASE, MSM_SDC2_BASE };
+
+static uint32_t mmc_sdhci_base[] =
+	{ MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE };
+
+static uint32_t  mmc_sdc_pwrctl_irq[] =
+	{ SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ };
+
+static void set_sdc_power_ctrl(void);
+
+void target_early_init(void)
+{
+#if WITH_DEBUG_UART
+	uart_dm_init(1, 0, BLSP1_UART1_BASE);
+#endif
+}
+
+void target_sdc_init()
+{
+	struct mmc_config_data config;
+
+	/* Set drive strength & pull ctrl values */
+	set_sdc_power_ctrl();
+
+	config.bus_width = DATA_BUS_WIDTH_8BIT;
+	config.max_clk_rate = MMC_CLK_177MHZ;
+
+	/* Try slot 1*/
+	config.slot         = 1;
+	config.sdhc_base    = mmc_sdhci_base[config.slot - 1];
+	config.pwrctl_base  = mmc_pwrctl_base[config.slot - 1];
+	config.pwr_irq      = mmc_sdc_pwrctl_irq[config.slot - 1];
+	config.hs400_support = 0;
+
+	if (!(dev = mmc_init(&config))) {
+	/* Try slot 2 */
+		config.slot         = 2;
+		config.max_clk_rate = MMC_CLK_200MHZ;
+		config.sdhc_base    = mmc_sdhci_base[config.slot - 1];
+		config.pwrctl_base  = mmc_pwrctl_base[config.slot - 1];
+		config.pwr_irq      = mmc_sdc_pwrctl_irq[config.slot - 1];
+
+		if (!(dev = mmc_init(&config))) {
+			dprintf(CRITICAL, "mmc init failed!");
+			ASSERT(0);
+		}
+	}
+}
+
+void *target_mmc_device()
+{
+	return (void *) dev;
+}
+
+static void target_keystatus()
+{
+}
+
+static void set_sdc_power_ctrl()
+{
+	/* Drive strength configs for sdc pins */
+	struct tlmm_cfgs sdc1_hdrv_cfg[] =
+	{
+		{ SDC1_CLK_HDRV_CTL_OFF,  TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK },
+		{ SDC1_CMD_HDRV_CTL_OFF,  TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+		{ SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_6MA, TLMM_HDRV_MASK },
+	};
+
+	/* Pull configs for sdc pins */
+	struct tlmm_cfgs sdc1_pull_cfg[] =
+	{
+		{ SDC1_CLK_PULL_CTL_OFF,  TLMM_NO_PULL, TLMM_PULL_MASK },
+		{ SDC1_CMD_PULL_CTL_OFF,  TLMM_PULL_UP, TLMM_PULL_MASK },
+		{ SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
+	};
+
+	/* Set the drive strength & pull control values */
+	tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
+	tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
+}
+
+void target_init(void)
+{
+	uint32_t base_addr;
+	uint8_t slot;
+
+	dprintf(INFO, "target_init()\n");
+
+	spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
+
+	target_keystatus();
+
+	target_sdc_init();
+
+	if (partition_read_table())
+	{
+		dprintf(CRITICAL, "Error reading the partition table info\n");
+		ASSERT(0);
+	}
+
+}
+
+void target_serialno(unsigned char *buf)
+{
+	uint32_t serialno;
+	if (target_is_emmc_boot()) {
+		serialno = mmc_get_psn();
+		snprintf((char *)buf, 13, "%x", serialno);
+	}
+}
+
+unsigned board_machtype(void)
+{
+}
+
diff --git a/target/ferrum/meminfo.c b/target/ferrum/meminfo.c
new file mode 100644
index 0000000..9d76bf6
--- /dev/null
+++ b/target/ferrum/meminfo.c
@@ -0,0 +1,85 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <reg.h>
+#include <debug.h>
+#include <malloc.h>
+#include <smem.h>
+#include <stdint.h>
+#include <libfdt.h>
+#include <platform/iomap.h>
+#include <dev_tree.h>
+
+uint32_t target_dev_tree_mem(void *fdt, uint32_t memory_node_offset)
+{
+	ram_partition ptn_entry;
+	unsigned int index;
+	int ret = 0;
+	uint32_t len = 0;
+
+	/* Make sure RAM partition table is initialized */
+	ASSERT(smem_ram_ptable_init_v1());
+
+	len = smem_get_ram_ptable_len();
+
+	/* Calculating the size of the mem_info_ptr */
+	for (index = 0 ; index < len; index++)
+	{
+		smem_get_ram_ptable_entry(&ptn_entry, index);
+
+		if((ptn_entry.category == SDRAM) &&
+			(ptn_entry.type == SYS_MEMORY))
+		{
+
+			/* Pass along all other usable memory regions to Linux */
+			ret = dev_tree_add_mem_info(fdt,
+							memory_node_offset,
+							ptn_entry.start,
+							ptn_entry.size);
+
+			if (ret)
+			{
+				dprintf(CRITICAL, "Failed to add secondary banks memory addresses\n");
+				goto target_dev_tree_mem_err;
+			}
+		}
+	}
+target_dev_tree_mem_err:
+
+	return ret;
+}
+
+void *target_get_scratch_address(void)
+{
+	return ((void *)SCRATCH_ADDR);
+}
+
+unsigned target_get_max_flash_size(void)
+{
+	return (256 * 1024 * 1024);
+}
diff --git a/target/ferrum/rules.mk b/target/ferrum/rules.mk
new file mode 100644
index 0000000..1e8c4f4
--- /dev/null
+++ b/target/ferrum/rules.mk
@@ -0,0 +1,29 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+
+PLATFORM := ferrum
+
+MEMBASE := 0x8F600000 # SDRAM
+MEMSIZE := 0x00100000 # 1MB
+
+BASE_ADDR        := 0x80000000
+SCRATCH_ADDR     := 0x90000000
+
+MODULES += \
+	dev/keys \
+	dev/vib \
+	lib/ptable \
+	dev/pmic/pm8x41 \
+	lib/libfdt
+
+DEFINES += \
+	MEMSIZE=$(MEMSIZE) \
+	MEMBASE=$(MEMBASE) \
+	BASE_ADDR=$(BASE_ADDR) \
+	SCRATCH_ADDR=$(SCRATCH_ADDR)
+
+
+OBJS += \
+	$(LOCAL_DIR)/init.o \
+	$(LOCAL_DIR)/meminfo.o
diff --git a/target/ferrum/tools/makefile b/target/ferrum/tools/makefile
new file mode 100644
index 0000000..da48f0d
--- /dev/null
+++ b/target/ferrum/tools/makefile
@@ -0,0 +1,12 @@
+#Makefile to generate appsboot.mbn
+
+ifeq ($(BOOTLOADER_OUT),.)
+APPSBOOTOUT_DIR  := $(BUILDDIR)
+else
+APPSBOOTOUT_DIR  := $(BOOTLOADER_OUT)/../..
+endif
+
+APPSBOOTHEADER: emmc_appsboot.mbn
+
+emmc_appsboot.mbn: $(OUTELF_STRIP)
+	$(hide) cp -f $(OUTELF_STRIP) $(APPSBOOTOUT_DIR)/emmc_appsboot.mbn
diff --git a/target/fsm9010/init.c b/target/fsm9010/init.c
new file mode 100644
index 0000000..8f3da01
--- /dev/null
+++ b/target/fsm9010/init.c
@@ -0,0 +1,442 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <platform/iomap.h>
+#include <platform/irqs.h>
+#include <platform/gpio.h>
+#include <reg.h>
+#include <target.h>
+#include <platform.h>
+#include <dload_util.h>
+#include <uart_dm.h>
+#include <mmc.h>
+#include <spmi.h>
+#include <board.h>
+#include <smem.h>
+#include <baseband.h>
+#include <dev/keys.h>
+#include <crypto5_wrapper.h>
+#include <hsusb.h>
+#include <clock.h>
+#include <partition_parser.h>
+#include <scm.h>
+#include <platform/clock.h>
+#include <platform/gpio.h>
+#include <platform/timer.h>
+#include <stdlib.h>
+
+extern  bool target_use_signed_kernel(void);
+static void set_sdc_power_ctrl();
+
+static unsigned int target_id;
+
+#if MMC_SDHCI_SUPPORT
+struct mmc_device *dev;
+#endif
+
+#define PMIC_ARB_CHANNEL_NUM    0
+#define PMIC_ARB_OWNER_ID       0
+
+#define WDOG_DEBUG_DISABLE_BIT  17
+
+#define CE_INSTANCE             2
+#define CE_EE                   1
+#define CE_FIFO_SIZE            64
+#define CE_READ_PIPE            3
+#define CE_WRITE_PIPE           2
+#define CE_READ_PIPE_LOCK_GRP   0
+#define CE_WRITE_PIPE_LOCK_GRP  0
+#define CE_ARRAY_SIZE           20
+
+#define FASTBOOT_MODE           0x77665500
+
+#define BOARD_SOC_VERSION1(soc_rev) (soc_rev >= 0x10000 && soc_rev < 0x20000)
+
+#if MMC_SDHCI_SUPPORT
+static uint32_t mmc_sdhci_base[] =
+	{ MSM_SDC1_SDHCI_BASE };
+static uint32_t mmc_sdc_pwrctl_irq[] =
+	{ SDCC1_PWRCTL_IRQ };
+#endif
+
+static uint32_t mmc_sdc_base[] =
+	{ MSM_SDC1_BASE };
+
+void target_early_init(void)
+{
+#if WITH_DEBUG_UART
+	uart_dm_init(2, 0, BLSP1_UART2_BASE);
+#endif
+}
+
+/* Return 1 if vol_up pressed */
+static int target_volume_up()
+{
+	return 0;
+}
+
+/* Return 1 if vol_down pressed */
+uint32_t target_volume_down()
+{
+	return 0;
+}
+
+static void target_keystatus()
+{
+	keys_init();
+
+	if (target_volume_down())
+		keys_post_event(KEY_VOLUMEDOWN, 1);
+
+	if (target_volume_up())
+		keys_post_event(KEY_VOLUMEUP, 1);
+}
+
+/* Set up params for h/w CE. */
+void target_crypto_init_params()
+{
+	struct crypto_init_params ce_params;
+
+	/* Set up base addresses and instance. */
+	ce_params.crypto_instance  = CE_INSTANCE;
+	ce_params.crypto_base      = MSM_CE2_BASE;
+	ce_params.bam_base         = MSM_CE2_BAM_BASE;
+
+	/* Set up BAM config. */
+	ce_params.bam_ee               = CE_EE;
+	ce_params.pipes.read_pipe      = CE_READ_PIPE;
+	ce_params.pipes.write_pipe     = CE_WRITE_PIPE;
+	ce_params.pipes.read_pipe_grp  = CE_READ_PIPE_LOCK_GRP;
+	ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP;
+
+	/* Assign buffer sizes. */
+	ce_params.num_ce           = CE_ARRAY_SIZE;
+	ce_params.read_fifo_size   = CE_FIFO_SIZE;
+	ce_params.write_fifo_size  = CE_FIFO_SIZE;
+
+	/* BAM is initialized by TZ for this platform.
+	 * Do not do it again as the initialization address space
+	 * is locked.
+	 */
+	ce_params.do_bam_init      = 0;
+
+	crypto_init_params(&ce_params);
+}
+
+crypto_engine_type board_ce_type(void)
+{
+	return CRYPTO_ENGINE_TYPE_HW;
+}
+
+#if MMC_SDHCI_SUPPORT
+static void target_mmc_sdhci_init()
+{
+	struct mmc_config_data config = {0};
+
+	config.bus_width = DATA_BUS_WIDTH_8BIT;
+	config.max_clk_rate = MMC_CLK_96MHZ;
+
+	/* Trying Slot 1*/
+	config.slot = 1;
+	config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+	config.pwrctl_base = mmc_sdc_base[config.slot - 1];
+	config.pwr_irq     = mmc_sdc_pwrctl_irq[config.slot - 1];
+
+	if (!(dev = mmc_init(&config))) {
+		dprintf(CRITICAL, "mmc init failed!");
+		ASSERT(0);
+	}
+
+	/*
+	 * MMC initialization is complete, read the partition table info
+	 */
+	if (partition_read_table()) {
+		dprintf(CRITICAL, "Error reading the partition table info\n");
+		ASSERT(0);
+	}
+}
+
+void *target_mmc_device()
+{
+	return (void *) dev;
+}
+
+#else
+
+static void target_mmc_mci_init()
+{
+	uint32_t base_addr;
+	uint8_t slot;
+
+	/* Trying Slot 1 */
+	slot = 1;
+	base_addr = mmc_sdc_base[slot - 1];
+
+	if (mmc_boot_main(slot, base_addr))
+	{
+		dprintf(CRITICAL, "mmc init failed!");
+		ASSERT(0);
+	}
+}
+
+/*
+ * Function to set the capabilities for the host
+ */
+void target_mmc_caps(struct mmc_host *host)
+{
+	host->caps.bus_width = MMC_BOOT_BUS_WIDTH_8_BIT;
+	host->caps.ddr_mode = 0;
+	host->caps.hs200_mode = 1;
+	host->caps.hs_clk_rate = MMC_CLK_96MHZ;
+}
+
+#endif
+
+void target_init(void)
+{
+	dprintf(INFO, "target_init()\n");
+
+	target_keystatus();
+
+	if (target_use_signed_kernel())
+		target_crypto_init_params();
+
+	/*
+	 * Set drive strength & pull ctrl for
+	 * emmc
+	 */
+	set_sdc_power_ctrl();
+
+#if MMC_SDHCI_SUPPORT
+	target_mmc_sdhci_init();
+#else
+	target_mmc_mci_init();
+#endif
+}
+
+unsigned board_machtype(void)
+{
+	return target_id;
+}
+
+void target_fastboot_init(void)
+{
+}
+
+/* Detect the target type */
+void target_detect(struct board_data *board)
+{
+	/* This property is filled as part of board.c */
+}
+
+/* Detect the modem type */
+void target_baseband_detect(struct board_data *board)
+{
+	uint32_t platform;
+	uint32_t platform_subtype;
+
+	platform = board->platform;
+	platform_subtype = board->platform_subtype;
+
+	/*
+	 * Look for platform subtype if present, else
+	 * check for platform type to decide on the
+	 * baseband type
+	 */
+	switch (platform_subtype) {
+	case HW_PLATFORM_SUBTYPE_UNKNOWN:
+		break;
+	default:
+		dprintf(CRITICAL, "Platform Subtype : %u is not supported\n",platform_subtype);
+		ASSERT(0);
+	};
+
+	switch (platform) {
+	case FSM9010:
+		board->baseband = BASEBAND_MSM;
+		break;
+	default:
+		dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
+		ASSERT(0);
+	};
+}
+
+unsigned target_baseband()
+{
+	return board_baseband();
+}
+
+void target_serialno(unsigned char *buf)
+{
+	unsigned int serialno;
+	if (target_is_emmc_boot()) {
+		serialno = mmc_get_psn();
+		snprintf((char *)buf, 13, "%x", serialno);
+	}
+}
+
+unsigned check_reboot_mode(void)
+{
+	uint32_t restart_reason = 0;
+	uint32_t restart_reason_addr;
+
+	restart_reason_addr = RESTART_REASON_ADDR;
+
+	/* Read reboot reason and scrub it */
+	restart_reason = readl(restart_reason_addr);
+	writel(0x00, restart_reason_addr);
+
+	return restart_reason;
+}
+
+void reboot_device(unsigned reboot_reason)
+{
+	/* Write the reboot reason */
+	writel(reboot_reason, RESTART_REASON_ADDR);
+
+	/* Disable Watchdog Debug.
+	 * Required becuase of a H/W bug which causes the system to
+	 * reset partially even for non watchdog resets.
+	 */
+	writel(readl(GCC_WDOG_DEBUG) & ~(1 << WDOG_DEBUG_DISABLE_BIT), GCC_WDOG_DEBUG);
+
+	dsb();
+
+	/* Wait until the write takes effect. */
+	while(readl(GCC_WDOG_DEBUG) & (1 << WDOG_DEBUG_DISABLE_BIT));
+
+	/* Drop PS_HOLD for MSM */
+	writel(0x00, MPM2_MPM_PS_HOLD);
+
+	mdelay(5000);
+
+	dprintf(CRITICAL, "Rebooting failed\n");
+}
+
+int set_download_mode(enum dload_mode mode)
+{
+	dload_util_write_cookie(mode == NORMAL_DLOAD ?
+		DLOAD_MODE_ADDR_V2 : EMERGENCY_DLOAD_MODE_ADDR_V2, mode);
+
+	return 0;
+}
+
+/* Check if MSM needs VBUS mimic for USB */
+static int target_needs_vbus_mimic()
+{
+	return 1;
+}
+
+/* Do target specific usb initialization */
+void target_usb_init(void)
+{
+	uint32_t val;
+
+	extern void ulpi_write(unsigned val, unsigned reg);
+
+	if (target_needs_vbus_mimic()) {
+		/* Select and enable external configuration with USB PHY */
+		ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_SET);
+
+		/* Enable sess_vld */
+		val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN;
+		writel(val, USB_GENCONFIG_2);
+
+		/* Enable external vbus configuration in the LINK */
+		val = readl(USB_USBCMD);
+		val |= SESS_VLD_CTRL;
+		writel(val, USB_USBCMD);
+	}
+}
+
+/* Returns 1 if target supports continuous splash screen. */
+int target_cont_splash_screen()
+{
+	return 0;
+}
+
+unsigned target_pause_for_battery_charge(void)
+{
+	return 0;
+}
+
+void target_uninit(void)
+{
+#if MMC_SDHCI_SUPPORT
+	mmc_put_card_to_sleep(dev);
+#else
+	mmc_put_card_to_sleep();
+#endif
+}
+
+void shutdown_device()
+{
+	dprintf(CRITICAL, "Going down for shutdown.\n");
+
+	/* Drop PS_HOLD for MSM */
+	writel(0x00, MPM2_MPM_PS_HOLD);
+
+	mdelay(5000);
+
+	dprintf(CRITICAL, "Shutdown failed\n");
+}
+
+static void set_sdc_power_ctrl()
+{
+	/* Drive strength configs for sdc pins */
+	struct tlmm_cfgs sdc1_hdrv_cfg[] =
+	{
+		{ SDC1_CLK_HDRV_CTL_OFF,  TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+		{ SDC1_CMD_HDRV_CTL_OFF,  TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+		{ SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+	};
+
+	/* Pull configs for sdc pins */
+	struct tlmm_cfgs sdc1_pull_cfg[] =
+	{
+		{ SDC1_CLK_PULL_CTL_OFF,  TLMM_NO_PULL, TLMM_PULL_MASK },
+		{ SDC1_CMD_PULL_CTL_OFF,  TLMM_PULL_UP, TLMM_PULL_MASK },
+		{ SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
+	};
+
+	/* Set the drive strength & pull control values */
+	tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
+	tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
+}
+
+int emmc_recovery_init(void)
+{
+	extern int _emmc_recovery_init(void);
+
+	return _emmc_recovery_init();
+}
+
+void target_usb_stop(void)
+{
+}
diff --git a/target/fsm9010/meminfo.c b/target/fsm9010/meminfo.c
new file mode 100644
index 0000000..c6dd53e
--- /dev/null
+++ b/target/fsm9010/meminfo.c
@@ -0,0 +1,95 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if DEVICE_TREE /* If using device tree */
+
+#include <reg.h>
+#include <debug.h>
+#include <malloc.h>
+#include <smem.h>
+#include <stdint.h>
+#include <libfdt.h>
+#include <platform/iomap.h>
+#include <dev_tree.h>
+
+/* Funtion to add the ram partition entries into device tree.
+ * The function assumes that all the entire fixed memory regions should
+ * be listed in the first bank of the passed in ddr regions.
+ */
+uint32_t target_dev_tree_mem(void *fdt, uint32_t memory_node_offset)
+{
+	ram_partition ptn_entry;
+	unsigned int index;
+	int ret = 0;
+	uint32_t len = 0;
+
+	/* Make sure RAM partition table is initialized */
+	ASSERT(smem_ram_ptable_init_v1());
+
+	len = smem_get_ram_ptable_len();
+
+	/* Calculating the size of the mem_info_ptr */
+	for (index = 0 ; index < len; index++)
+	{
+		smem_get_ram_ptable_entry(&ptn_entry, index);
+
+		if((ptn_entry.category == SDRAM) &&
+			(ptn_entry.type == SYS_MEMORY))
+		{
+
+			/* Pass along all other usable memory regions to Linux */
+			ret = dev_tree_add_mem_info(fdt,
+							memory_node_offset,
+							ptn_entry.start,
+							ptn_entry.size);
+
+			if (ret)
+			{
+				dprintf(CRITICAL,
+					"Failed to add secondary banks memory addresses\n");
+				goto target_dev_tree_mem_err;
+			}
+
+		}
+	}
+
+target_dev_tree_mem_err:
+
+	return ret;
+}
+
+void *target_get_scratch_address(void)
+{
+	return ((void *)SCRATCH_ADDR);
+}
+
+unsigned target_get_max_flash_size(void)
+{
+	return (512 * 1024 * 1024);
+}
+#endif /* DEVICE_TREE */
diff --git a/target/fsm9010/rules.mk b/target/fsm9010/rules.mk
new file mode 100644
index 0000000..63f02b5
--- /dev/null
+++ b/target/fsm9010/rules.mk
@@ -0,0 +1,34 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+
+PLATFORM := fsm9010
+
+MEMBASE := 0x0F900000 # SDRAM
+MEMSIZE := 0x00100000 # 1MB
+
+BASE_ADDR        := 0x00000000
+
+TAGS_ADDR        := BASE_ADDR+0x01e00000
+KERNEL_ADDR      := BASE_ADDR+0x00008000
+RAMDISK_ADDR     := BASE_ADDR+0x02000000
+SCRATCH_ADDR     := 0x0ff00000
+
+MODULES += \
+	dev/keys \
+    lib/ptable \
+    lib/libfdt
+
+DEFINES += \
+	MEMSIZE=$(MEMSIZE) \
+	MEMBASE=$(MEMBASE) \
+	BASE_ADDR=$(BASE_ADDR) \
+	TAGS_ADDR=$(TAGS_ADDR) \
+	KERNEL_ADDR=$(KERNEL_ADDR) \
+	RAMDISK_ADDR=$(RAMDISK_ADDR) \
+	SCRATCH_ADDR=$(SCRATCH_ADDR)
+
+
+OBJS += \
+    $(LOCAL_DIR)/init.o \
+    $(LOCAL_DIR)/meminfo.o
diff --git a/target/fsm9010/tools/makefile b/target/fsm9010/tools/makefile
new file mode 100644
index 0000000..2757e07
--- /dev/null
+++ b/target/fsm9010/tools/makefile
@@ -0,0 +1,44 @@
+#Makefile to generate appsboot.mbn
+
+ifeq ($(BOOTLOADER_OUT),.)
+APPSBOOTHEADER_DIR  := $(BUILDDIR)
+else
+APPSBOOTHEADER_DIR  := $(BOOTLOADER_OUT)/../..
+endif
+
+SRC_DIR  := target/$(TARGET)/tools
+COMPILER := gcc
+
+ifeq ($(EMMC_BOOT), 1)
+  APPSBOOTHDR_FILES := EMMCBOOT.MBN
+else
+  ifeq ($(BUILD_NANDWRITE), 1)
+    APPSBOOTHDR_FILES :=
+  else
+    APPSBOOTHDR_FILES := appsboot.mbn
+  endif
+endif
+
+APPSBOOTHEADER: $(APPSBOOTHDR_FILES)
+
+
+appsboot.mbn: appsboothd.mbn $(OUTBIN)
+	cp $(OUTBIN) $(APPSBOOTHEADER_DIR)/appsboot.raw
+	cat $(APPSBOOTHEADER_DIR)/appsboothd.mbn $(OUTBIN) > $(APPSBOOTHEADER_DIR)/appsboot.mbn
+	rm -f $(APPSBOOTHEADER_DIR)/appsboothd.mbn
+
+appsboothd.mbn: mkheader $(OUTBIN)
+	$(BUILDDIR)/mkheader $(OUTBIN) $(APPSBOOTHEADER_DIR)/appsboothd.mbn
+
+EMMCBOOT.MBN: emmc_appsboothd.mbn $(OUTBIN)
+	cp $(OUTBIN) $(APPSBOOTHEADER_DIR)/emmc_appsboot.raw
+	cat $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn $(OUTBIN) > $(APPSBOOTHEADER_DIR)/EMMCBOOT.MBN
+	cat $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn $(OUTBIN) > $(APPSBOOTHEADER_DIR)/emmc_appsboot.mbn
+	rm -f $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn
+
+emmc_appsboothd.mbn: mkheader $(OUTBIN)
+	$(BUILDDIR)/mkheader $(OUTBIN) $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn
+
+mkheader: $(SRC_DIR)/mkheader.c
+	@mkdir -p $(BUILDDIR)
+	${COMPILER} -DMEMBASE=$(MEMBASE) $(SRC_DIR)/mkheader.c -o $(BUILDDIR)/mkheader
diff --git a/target/fsm9010/tools/mkheader.c b/target/fsm9010/tools/mkheader.c
new file mode 100644
index 0000000..4a84bd6
--- /dev/null
+++ b/target/fsm9010/tools/mkheader.c
@@ -0,0 +1,344 @@
+/*
+ * Copyright (c) 2007, Google Inc.
+ * All rights reserved.
+ *
+ * Copyright (c) 2009-2011, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  * Neither the name of Google, Inc. nor the names of its contributors
+ *    may be used to endorse or promote products derived from this
+ *    software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <string.h>
+
+#include <sys/stat.h>
+
+int print_usage()
+{
+	fprintf(stderr, "usage: mkheader <bin> <hdr> <none|unified-boot>\n");
+	fprintf(stderr, "       mkheader <bin> <hdr> <unsecure-boot>"
+		" <outbin>\n");
+	fprintf(stderr, "       mkheader <bin> <hdr> <secure-boot> <outbin>"
+		" <maxsize>\n");
+	fprintf(stderr, "       mkheader <bin> <hdr> <secure-boot> <outbin>"
+		" <maxsize> <certchain> <files...>\n\n");
+	fprintf(stderr, "bin:               Input raw appsbl binary\n");
+	fprintf(stderr,
+		"hdr:               Output of appsbl header location\n");
+	fprintf(stderr,
+		"outbin:            Output of the signed or unsigned"
+		" apps boot location\n");
+	fprintf(stderr,
+		"maxsize:           Maximum size for certificate" " chain\n");
+	fprintf(stderr,
+		"certchain:         Output of the certchain location\n");
+	fprintf(stderr,
+		"files:             Input format <bin signature>"
+		" <certifcate file(s) for certificate chain>...\n");
+	fprintf(stderr,
+		"certificate chain: Files will be concatenated in order"
+		" to create the certificate chain\n\n");
+	return -1;
+}
+
+int cat(FILE * in, FILE * out, unsigned size, unsigned buff_size)
+{
+	unsigned bytes_left = size;
+	char buf[buff_size];
+	int ret = 0;
+
+	while (bytes_left) {
+		fread(buf, sizeof(char), buff_size, in);
+		if (!feof(in)) {
+			bytes_left -= fwrite(buf, sizeof(char), buff_size, out);
+		} else
+			bytes_left = 0;
+	}
+	ret = ferror(in) | ferror(out);
+	if (ret)
+		fprintf(stderr, "ERROR: Occured during file concatenation\n");
+	return ret;
+}
+
+int main(int argc, char *argv[])
+{
+	struct stat s;
+	unsigned size, base;
+	int unified_boot = 0;
+	unsigned unified_boot_magic[20];
+	unsigned non_unified_boot_magic[10];
+	unsigned magic_len = 0;
+	unsigned *magic;
+	unsigned cert_chain_size = 0;
+	unsigned signature_size = 0;
+	int secure_boot = 0;
+	int fd;
+
+	if (argc < 3) {
+		return print_usage();
+	}
+
+	if (argc == 4) {
+		if (!strcmp("unified-boot", argv[3])) {
+			unified_boot = 1;
+		} else if (!strcmp("secure-boot", argv[3])) {
+			fprintf(stderr,
+				"ERROR: Missing arguments: [outbin maxsize] |"
+				" [outbin, maxsize, certchain,"
+				" signature + certifcate(s)]\n");
+			return print_usage();
+		} else if (!strcmp("unsecure-boot", argv[3])) {
+			fprintf(stderr, "ERROR: Missing arguments:"
+				" outbin directory\n");
+			return print_usage();
+		}
+	}
+
+	if (argc > 4) {
+		if (!strcmp("secure-boot", argv[3])) {
+			if (argc < 9 && argc != 6) {
+				fprintf(stderr,
+					"ERROR: Missing argument(s):"
+					" [outbin maxsize] | [outbin, maxsize,"
+					" certchain,"
+					" signature + certifcate(s)]\n");
+				return print_usage();
+			}
+			secure_boot = 1;
+			signature_size = 256;	//Support SHA 256
+			cert_chain_size = atoi(argv[5]);
+		}
+	}
+
+	if (stat(argv[1], &s)) {
+		perror("cannot stat binary");
+		return -1;
+	}
+
+	if (unified_boot) {
+		magic = unified_boot_magic;
+		magic_len = sizeof(unified_boot_magic);
+	} else {
+		magic = non_unified_boot_magic;
+		magic_len = sizeof(non_unified_boot_magic);
+	}
+
+	size = s.st_size;
+#if MEMBASE
+	base = MEMBASE;
+#else
+	base = 0;
+#endif
+
+	printf("Image Destination Pointer: 0x%x\n", base);
+
+	magic[0] = 0x00000005;	/* appsbl */
+	magic[1] = 0x00000003;	//Flash_partition_version /* nand */
+	magic[2] = 0x00000000;	//image source pointer
+	magic[3] = base;	//image destination pointer
+	magic[4] = size + cert_chain_size + signature_size;	//image size
+	magic[5] = size;	//code size
+	magic[6] = base + size;
+	magic[7] = signature_size;
+	magic[8] = size + base + signature_size;
+	magic[9] = cert_chain_size;
+
+	if (unified_boot == 1) {
+		magic[10] = 0x33836685;	/* cookie magic number */
+		magic[11] = 0x00000001;	/* cookie version */
+		magic[12] = 0x00000002;	/* file formats */
+		magic[13] = 0x00000000;
+		magic[14] = 0x00000000;	/* not setting size for boot.img */
+		magic[15] = 0x00000000;
+		magic[16] = 0x00000000;
+		magic[17] = 0x00000000;
+		magic[18] = 0x00000000;
+		magic[19] = 0x00000000;
+	}
+
+	fd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, 0644);
+	if (fd < 0) {
+		perror("cannot open header for writing");
+		return -1;
+	}
+	if (write(fd, magic, magic_len) != magic_len) {
+		perror("cannot write header");
+		close(fd);
+		unlink(argv[2]);
+		return -1;
+	}
+	close(fd);
+
+	if (secure_boot && argc > 6) {
+		FILE *input_file;
+		FILE *output_file;
+		unsigned buff_size = 1;
+		char buf[buff_size];
+		unsigned bytes_left;
+		unsigned current_cert_chain_size = 0;
+		int padding_size = 0;
+		int i;
+
+		if ((output_file = fopen(argv[6], "wb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		printf("Certificate Chain Output File: %s\n", argv[6]);
+
+		for (i = 8; i < argc; i++) {
+			if ((input_file = fopen(argv[i], "rb")) == NULL) {
+				perror("ERROR: Occured during fopen");
+				return -1;
+			}
+			stat(argv[i], &s);
+			bytes_left = s.st_size;
+			current_cert_chain_size += bytes_left;
+			if (cat(input_file, output_file, bytes_left, buff_size))
+				return -1;
+			fclose(input_file);
+		}
+
+		//Pad certifcate chain to the max expected size from input
+		memset(buf, 0xFF, sizeof(buf));
+		padding_size = cert_chain_size - current_cert_chain_size;
+
+		if (padding_size < 0) {
+			fprintf(stderr, "ERROR: Input certificate chain"
+				" (Size=%d) is larger than the maximum"
+				" specified (Size=%d)\n",
+				current_cert_chain_size, cert_chain_size);
+			return -1;
+		}
+
+		bytes_left = (padding_size > 0) ? padding_size : 0;
+		while (bytes_left) {
+			if (!ferror(output_file))
+				bytes_left -= fwrite(buf,
+						     sizeof(buf),
+						     buff_size, output_file);
+			else {
+				fprintf(stderr, "ERROR: Occured during"
+					" certifcate chain padding\n");
+				return -1;
+			}
+		}
+		fclose(output_file);
+
+		/* Concat and combine to signed image.
+		 * Format [HDR][RAW APPSBOOT][PADDED CERT CHAIN]
+		 */
+		if ((output_file = fopen(argv[4], "wb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		printf("Image Output File: %s\n", argv[4]);
+
+		//Header
+		if ((input_file = fopen(argv[2], "rb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		stat(argv[2], &s);
+		if (cat(input_file, output_file, s.st_size, buff_size))
+			return -1;
+		fclose(input_file);
+
+		//Raw Appsbl
+		if ((input_file = fopen(argv[1], "rb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		stat(argv[1], &s);
+		if (cat(input_file, output_file, s.st_size, buff_size))
+			return -1;
+		fclose(input_file);
+
+		//Signature
+		if ((input_file = fopen(argv[7], "rb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		stat(argv[7], &s);
+		if (cat(input_file, output_file, s.st_size, buff_size))
+			return -1;
+		fclose(input_file);
+
+		//Certifcate Chain
+		if ((input_file = fopen(argv[6], "rb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		if (cat(input_file, output_file,
+			(current_cert_chain_size + padding_size), buff_size))
+			return -1;
+		fclose(input_file);
+
+		fclose(output_file);
+
+	} else if (argc == 5 || argc == 6) {
+		FILE *input_file;
+		FILE *output_file;
+		unsigned buff_size = 1;
+		char buf[buff_size];
+
+		/* Concat and combine to unsigned image.
+		 * Format [HDR][RAW APPSBOOT]
+		 */
+		if ((output_file = fopen(argv[4], "wb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		printf("Image Output File: %s\n", argv[4]);
+
+		//Header
+		if ((input_file = fopen(argv[2], "rb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		stat(argv[2], &s);
+		if (cat(input_file, output_file, s.st_size, buff_size))
+			return -1;
+		fclose(input_file);
+
+		//Raw Appsbl
+		if ((input_file = fopen(argv[1], "rb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		stat(argv[1], &s);
+		if (cat(input_file, output_file, s.st_size, buff_size))
+			return -1;
+		fclose(input_file);
+		fclose(output_file);
+	}
+
+	printf("Done execution\n");
+
+	return 0;
+}
diff --git a/target/init.c b/target/init.c
index 0d99880..4a896e8 100644
--- a/target/init.c
+++ b/target/init.c
@@ -69,6 +69,11 @@
 {
 }
 
+__WEAK uint32_t is_user_force_reset(void)
+{
+	return 0;
+}
+
 __WEAK int set_download_mode(enum dload_mode mode)
 {
 	return -1;
diff --git a/target/msm8226/target_display.c b/target/msm8226/target_display.c
index d21fb94..355d8c9 100755
--- a/target/msm8226/target_display.c
+++ b/target/msm8226/target_display.c
@@ -389,7 +389,7 @@
 
 bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size)
 {
-	return gcdb_display_cmdline_arg(pbuf, buf_size);
+	return gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
 }
 
 void target_display_init(const char *panel_name)
@@ -398,8 +398,10 @@
         uint32_t ret = 0;
 	uint32_t fb_addr = MIPI_FB_ADDR;
 
-	if (!strcmp(panel_name, NO_PANEL_CONFIG)) {
-		dprintf(INFO, "Skip panel configuration\n");
+	if ((!strcmp(panel_name, NO_PANEL_CONFIG))
+			|| (!strcmp(panel_name, SIM_VIDEO_PANEL))) {
+		dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n",
+								panel_name);
 		return;
 	}
 
diff --git a/target/msm8610/target_display.c b/target/msm8610/target_display.c
index cb9f3ce..66dbbdd 100755
--- a/target/msm8610/target_display.c
+++ b/target/msm8610/target_display.c
@@ -164,7 +164,7 @@
 
 bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size)
 {
-	return gcdb_display_cmdline_arg(pbuf, buf_size);
+	return gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
 }
 
 void target_display_init(const char *panel_name)
diff --git a/target/msm8916/include/target/display.h b/target/msm8916/include/target/display.h
index dcbc447..0faf033 100644
--- a/target/msm8916/include/target/display.h
+++ b/target/msm8916/include/target/display.h
@@ -65,6 +65,18 @@
   0, 0, 0, 0, 0, 0
 };
 
+static struct gpio_pin bkl_gpio_skuk = {
+  "msmgpio", 1, 3, 1, 0, 1
+};
+
+static struct gpio_pin enp_gpio_skuk = {
+  "msmgpio", 97, 3, 1, 0, 1
+};
+
+static struct gpio_pin enn_gpio_skuk = {
+  "msmgpio", 98, 3, 1, 0, 1
+};
+
 /*---------------------------------------------------------------------------*/
 /* Target Physical configuration                                             */
 /*---------------------------------------------------------------------------*/
@@ -112,7 +124,8 @@
 {
 	HW_PLATFORM_SUBTYPE_DEFAULT = 0,
 	HW_PLATFORM_SUBTYPE_SKUH = 4,
-	HW_PLATFORM_SUBTYPE_SKUI = 5,
+	HW_PLATFORM_SUBTYPE_SKUI = 5, /* msm8916 */
+	HW_PLATFORM_SUBTYPE_SKUK = 5, /* msm8939 */
 };
 
 #endif
diff --git a/target/msm8916/init.c b/target/msm8916/init.c
index 2a33157..2385d24 100644
--- a/target/msm8916/init.c
+++ b/target/msm8916/init.c
@@ -168,6 +168,23 @@
 		keys_post_event(KEY_VOLUMEUP, 1);
 }
 
+#if USER_FORCE_RESET_SUPPORT
+/* Return 1 if it is a force resin triggered by user. */
+uint32_t is_user_force_reset(void)
+{
+	uint8_t poff_reason1 = pm8x41_get_pon_poff_reason1();
+	uint8_t poff_reason2 = pm8x41_get_pon_poff_reason2();
+
+	dprintf(SPEW, "poff_reason1: %d\n", poff_reason1);
+	dprintf(SPEW, "poff_reason2: %d\n", poff_reason2);
+	if (pm8x41_get_is_cold_boot() && (poff_reason1 == KPDPWR_AND_RESIN ||
+							poff_reason2 == STAGE3))
+		return 1;
+	else
+		return 0;
+}
+#endif
+
 void target_init(void)
 {
 	uint32_t base_addr;
diff --git a/target/msm8916/oem_panel.c b/target/msm8916/oem_panel.c
index 6f9ac7c..d97823c 100644
--- a/target/msm8916/oem_panel.c
+++ b/target/msm8916/oem_panel.c
@@ -47,6 +47,10 @@
 #include "include/panel_innolux_720p_video.h"
 #include "include/panel_otm8019a_fwvga_video.h"
 #include "include/panel_otm1283a_720p_video.h"
+#include "include/panel_nt35596_1080p_skuk_video.h"
+#include "include/panel_sharp_wqxga_dualdsi_video.h"
+#include "include/panel_jdi_fhd_video.h""
+#include "include/panel_hx8379a_fwvga_video.h"
 
 #define DISPLAY_MAX_PANEL_DETECTION 2
 #define OTM8019A_FWVGA_VIDEO_PANEL_ON_DELAY 50
@@ -63,6 +67,10 @@
 INNOLUX_720P_VIDEO_PANEL,
 OTM8019A_FWVGA_VIDEO_PANEL,
 OTM1283A_720P_VIDEO_PANEL,
+NT35596_1080P_VIDEO_PANEL,
+SHARP_WQXGA_DUALDSI_VIDEO_PANEL,
+JDI_FHD_VIDEO_PANEL,
+HX8379A_FWVGA_VIDEO_PANEL,
 UNKNOWN_PANEL
 };
 
@@ -77,6 +85,10 @@
 	{"innolux_720p_video", INNOLUX_720P_VIDEO_PANEL},
 	{"otm8019a_fwvga_video", OTM8019A_FWVGA_VIDEO_PANEL},
 	{"otm1283a_720p_video", OTM1283A_720P_VIDEO_PANEL},
+	{"nt35596_1080p_video", NT35596_1080P_VIDEO_PANEL},
+	{"sharp_wqxga_dualdsi_video",SHARP_WQXGA_DUALDSI_VIDEO_PANEL},
+	{"jdi_fhd_video", JDI_FHD_VIDEO_PANEL},
+	{"hx8379a_wvga_video", HX8379A_FWVGA_VIDEO_PANEL},
 };
 
 static uint32_t panel_id;
@@ -238,6 +250,87 @@
 		memcpy(phy_db->timing,
 				otm1283a_720p_video_timings, TIMING_SIZE);
 		break;
+	case NT35596_1080P_VIDEO_PANEL:
+		panelstruct->paneldata    = &nt35596_1080p_skuk_video_panel_data;
+		panelstruct->panelres     = &nt35596_1080p_skuk_video_panel_res;
+		panelstruct->color        = &nt35596_1080p_skuk_video_color;
+		panelstruct->videopanel   = &nt35596_1080p_skuk_video_video_panel;
+		panelstruct->commandpanel = &nt35596_1080p_skuk_video_command_panel;
+		panelstruct->state        = &nt35596_1080p_skuk_video_state;
+		panelstruct->laneconfig   = &nt35596_1080p_skuk_video_lane_config;
+		panelstruct->paneltiminginfo
+					= &nt35596_1080p_skuk_video_timing_info;
+		panelstruct->panelresetseq
+					= &nt35596_1080p_skuk_video_reset_seq;
+		panelstruct->backlightinfo = &nt35596_1080p_skuk_video_backlight;
+		pinfo->mipi.panel_cmds
+					= nt35596_1080p_skuk_video_on_command;
+		pinfo->mipi.num_of_panel_cmds
+					= NT35596_1080P_SKUK_VIDEO_ON_COMMAND;
+		memcpy(phy_db->timing,
+				nt35596_1080p_skuk_video_timings, TIMING_SIZE);
+		break;
+	case SHARP_WQXGA_DUALDSI_VIDEO_PANEL:
+		panelstruct->paneldata    = &sharp_wqxga_dualdsi_video_panel_data;
+		panelstruct->panelres     = &sharp_wqxga_dualdsi_video_panel_res;
+		panelstruct->color        = &sharp_wqxga_dualdsi_video_color;
+		panelstruct->videopanel   = &sharp_wqxga_dualdsi_video_video_panel;
+		panelstruct->commandpanel = &sharp_wqxga_dualdsi_video_command_panel;
+		panelstruct->state        = &sharp_wqxga_dualdsi_video_state;
+		panelstruct->laneconfig   = &sharp_wqxga_dualdsi_video_lane_config;
+		panelstruct->paneltiminginfo
+			= &sharp_wqxga_dualdsi_video_timing_info;
+		panelstruct->panelresetseq
+					 = &sharp_wqxga_dualdsi_video_reset_seq;
+		panelstruct->backlightinfo = &sharp_wqxga_dualdsi_video_backlight;
+		pinfo->mipi.panel_cmds
+			= sharp_wqxga_dualdsi_video_on_command;
+		pinfo->mipi.num_of_panel_cmds
+			= SHARP_WQXGA_DUALDSI_VIDEO_ON_COMMAND;
+		memcpy(phy_db->timing,
+			sharp_wqxga_dualdsi_video_timings, TIMING_SIZE);
+		pinfo->mipi.signature 	= SHARP_WQXGA_DUALDSI_VIDEO_SIGNATURE;
+		break;
+	case JDI_FHD_VIDEO_PANEL:
+                panelstruct->paneldata    = &jdi_fhd_video_panel_data;
+                panelstruct->panelres     = &jdi_fhd_video_panel_res;
+                panelstruct->color        = &jdi_fhd_video_color;
+                panelstruct->videopanel   = &jdi_fhd_video_video_panel;
+                panelstruct->commandpanel = &jdi_fhd_video_command_panel;
+                panelstruct->state        = &jdi_fhd_video_state;
+                panelstruct->laneconfig   = &jdi_fhd_video_lane_config;
+                panelstruct->paneltiminginfo
+                                        = &jdi_fhd_video_timing_info;
+                panelstruct->panelresetseq
+                                        = &jdi_fhd_video_reset_seq;
+                panelstruct->backlightinfo = &jdi_fhd_video_backlight;
+                pinfo->mipi.panel_cmds
+                                        = jdi_fhd_video_on_command;
+                pinfo->mipi.num_of_panel_cmds
+                                        = JDI_FHD_VIDEO_ON_COMMAND;
+                memcpy(phy_db->timing,
+                                jdi_fhd_video_timings, TIMING_SIZE);
+                break;
+	case HX8379A_FWVGA_VIDEO_PANEL:
+		panelstruct->paneldata    = &hx8379a_fwvga_video_panel_data;
+		panelstruct->panelres     = &hx8379a_fwvga_video_panel_res;
+		panelstruct->color        = &hx8379a_fwvga_video_color;
+		panelstruct->videopanel   = &hx8379a_fwvga_video_video_panel;
+		panelstruct->commandpanel = &hx8379a_fwvga_video_command_panel;
+		panelstruct->state        = &hx8379a_fwvga_video_state;
+		panelstruct->laneconfig   = &hx8379a_fwvga_video_lane_config;
+		panelstruct->paneltiminginfo
+					= &hx8379a_fwvga_video_timing_info;
+		panelstruct->panelresetseq
+					= &hx8379a_fwvga_video_reset_seq;
+		panelstruct->backlightinfo = &hx8379a_fwvga_video_backlight;
+		pinfo->mipi.panel_cmds
+					= hx8379a_fwvga_video_on_command;
+		pinfo->mipi.num_of_panel_cmds
+					= HX8379A_FWVGA_VIDEO_ON_COMMAND;
+		memcpy(phy_db->timing,
+					hx8379a_fwvga_video_timings, TIMING_SIZE);
+		break;
 	case UNKNOWN_PANEL:
 	default:
 		memset(panelstruct, 0, sizeof(struct panel_struct));
@@ -303,24 +396,40 @@
 		auto_pan_loop++;
 		break;
 	case HW_PLATFORM_QRD:
-		switch (hw_subtype) {
-		case HW_PLATFORM_SUBTYPE_SKUH:
-			target_id = board_target_id();
-			plat_hw_ver_major = ((target_id >> 16) & 0xFF);
+		target_id = board_target_id();
+		plat_hw_ver_major = ((target_id >> 16) & 0xFF);
 
-			/* qrd fan-out hw ? */
-			if ((plat_hw_ver_major >> 4) == 0x1)
-				panel_id = OTM1283A_720P_VIDEO_PANEL;
-			else
-				panel_id = INNOLUX_720P_VIDEO_PANEL;
-			break;
-		case HW_PLATFORM_SUBTYPE_SKUI:
-			panel_id = OTM8019A_FWVGA_VIDEO_PANEL;
-			break;
-		default:
-			dprintf(CRITICAL, "Invalid subtype id %d for QRD HW\n",
-				hw_subtype);
-			return PANEL_TYPE_UNKNOWN;
+		if (platform_is_msm8939()) {
+			switch (hw_subtype) {
+			case HW_PLATFORM_SUBTYPE_SKUK:
+				panel_id = NT35596_1080P_VIDEO_PANEL;
+				break;
+			default:
+				dprintf(CRITICAL, "Invalid subtype id %d for QRD HW\n",
+					hw_subtype);
+				return PANEL_TYPE_UNKNOWN;
+			}
+		} else {
+			switch (hw_subtype) {
+			case HW_PLATFORM_SUBTYPE_SKUH:
+				/* qrd SKUIC */
+				if ((plat_hw_ver_major >> 4) == 0x1)
+					panel_id = OTM1283A_720P_VIDEO_PANEL;
+				else
+					panel_id = INNOLUX_720P_VIDEO_PANEL;
+				break;
+			case HW_PLATFORM_SUBTYPE_SKUI:
+				/* qrd SKUIC */
+				if ((plat_hw_ver_major >> 4) == 0x1)
+					panel_id = HX8379A_FWVGA_VIDEO_PANEL;
+				else
+					panel_id = OTM8019A_FWVGA_VIDEO_PANEL;
+				break;
+			default:
+				dprintf(CRITICAL, "Invalid subtype id %d for QRD HW\n",
+					hw_subtype);
+				return PANEL_TYPE_UNKNOWN;
+			}
 		}
 		break;
 	default:
diff --git a/target/msm8916/target_display.c b/target/msm8916/target_display.c
index 84c26b4..ba16ac1 100755
--- a/target/msm8916/target_display.c
+++ b/target/msm8916/target_display.c
@@ -149,11 +149,11 @@
 						MIPI_DSI0_BASE, pll_data);
 		if (!dsi_pll_enable_seq_8916(DSI0_PLL_BASE))
 			dprintf(CRITICAL, "Not able to enable the pll\n");
-		gcc_dsi_clocks_enable(pll_data->pclk_m,
+		gcc_dsi_clocks_enable(pinfo->mipi.dual_dsi, pll_data->pclk_m,
 				pll_data->pclk_n,
 				pll_data->pclk_d);
 	} else if(!target_cont_splash_screen()) {
-		gcc_dsi_clocks_disable();
+		gcc_dsi_clocks_disable(pinfo->mipi.dual_dsi);
 		mdp_clock_disable();
 		mdss_bus_clocks_disable();
 		mdp_gdsc_ctrl(enable);
@@ -206,6 +206,84 @@
 	return 0;
 }
 
+static int target_panel_reset_skuh(uint8_t enable)
+{
+	int ret = NO_ERROR;
+	if (enable) {
+		/* for tps65132 ENP pin */
+		gpio_tlmm_config(enp_gpio.pin_id, 0,
+			enp_gpio.pin_direction, enp_gpio.pin_pull,
+			enp_gpio.pin_strength,
+			enp_gpio.pin_state);
+		gpio_set_dir(enp_gpio.pin_id, 2);
+
+		/* for tps65132 ENN pin*/
+		gpio_tlmm_config(enn_gpio.pin_id, 0,
+			enn_gpio.pin_direction, enn_gpio.pin_pull,
+			enn_gpio.pin_strength,
+			enn_gpio.pin_state);
+		gpio_set_dir(enn_gpio.pin_id, 2);
+
+		i2c_dev = qup_blsp_i2c_init(BLSP_ID_1, QUP_ID_1, 100000, 19200000);
+		if(!i2c_dev) {
+			dprintf(CRITICAL, "qup_blsp_i2c_init failed \n");
+			ASSERT(0);
+		}
+
+		ret = qrd_lcd_i2c_write(QRD_LCD_VPOS_ADDRESS, 0x0E); /* 5.4V */
+		if (ret) {
+			dprintf(CRITICAL, "VPOS Register: I2C Write failure\n");
+		}
+
+		ret = qrd_lcd_i2c_write(QRD_LCD_VNEG_ADDRESS, 0x0E); /* -5.4V */
+		if (ret) {
+			dprintf(CRITICAL, "VNEG Register: I2C write failure\n");
+		}
+
+		ret = qrd_lcd_i2c_write(QRD_LCD_DIS_ADDRESS, 0x0F);
+		if (ret) {
+			dprintf(CRITICAL, "Apps freq DIS Register: I2C write failure\n");
+		}
+
+		ret = qrd_lcd_i2c_write(QRD_LCD_CONTROL_ADDRESS, 0xF0);
+		if (ret) {
+			dprintf(CRITICAL, "Control Register: I2C write failure\n");
+		}
+	} else {
+		gpio_set_dir(enp_gpio.pin_id, 0); /* ENP */
+		gpio_set_dir(enn_gpio.pin_id, 0); /* ENN */
+	}
+	return 0;
+}
+
+static int target_panel_reset_skuk(uint8_t enable)
+{
+	if (enable) {
+		/* for tps65132 ENP pin*/
+		gpio_tlmm_config(enp_gpio_skuk.pin_id, 0,
+			enp_gpio_skuk.pin_direction, enp_gpio_skuk.pin_pull,
+			enp_gpio_skuk.pin_strength, enp_gpio_skuk.pin_state);
+		gpio_set_dir(enp_gpio_skuk.pin_id, 2);
+
+		/* for tps65132 ENN pin*/
+		gpio_tlmm_config(enn_gpio_skuk.pin_id, 0,
+			enn_gpio_skuk.pin_direction, enn_gpio_skuk.pin_pull,
+			enn_gpio_skuk.pin_strength, enn_gpio_skuk.pin_state);
+		gpio_set_dir(enn_gpio_skuk.pin_id, 2);
+
+		/* configure backlight gpio for SKUK */
+		gpio_tlmm_config(bkl_gpio_skuk.pin_id, 0,
+			bkl_gpio_skuk.pin_direction, bkl_gpio_skuk.pin_pull,
+			bkl_gpio_skuk.pin_strength, bkl_gpio_skuk.pin_state);
+		gpio_set_dir(bkl_gpio_skuk.pin_id, 2);
+	} else {
+		gpio_set_dir(bkl_gpio_skuk.pin_id, 0);
+		gpio_set_dir(enp_gpio_skuk.pin_id, 0); /* ENP */
+		gpio_set_dir(enn_gpio_skuk.pin_id, 0); /* ENN */
+	}
+	return 0;
+}
+
 int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
 						struct msm_panel_info *pinfo)
 {
@@ -223,47 +301,14 @@
 			gpio_set_dir(enable_gpio.pin_id, 2);
 		}
 
-		if (hw_id == HW_PLATFORM_QRD &&
-			hw_subtype == HW_PLATFORM_SUBTYPE_SKUH) {
-			/* for tps65132 chip ENP */
-			gpio_tlmm_config(enp_gpio.pin_id, 0,
-				enp_gpio.pin_direction, enp_gpio.pin_pull,
-				enp_gpio.pin_strength,
-				enp_gpio.pin_state);
-			gpio_set_dir(enp_gpio.pin_id, 2);
-
-			/* for tps65132 chip ENN */
-			gpio_tlmm_config(enn_gpio.pin_id, 0,
-				enn_gpio.pin_direction, enn_gpio.pin_pull,
-				enn_gpio.pin_strength,
-				enn_gpio.pin_state);
-			gpio_set_dir(enn_gpio.pin_id, 2);
-
-			i2c_dev = qup_blsp_i2c_init(BLSP_ID_1, QUP_ID_1, 100000, 19200000);
-			if(!i2c_dev) {
-				dprintf(CRITICAL, "qup_blsp_i2c_init failed \n");
-				ASSERT(0);
-			}
-
-			ret = qrd_lcd_i2c_write(QRD_LCD_VPOS_ADDRESS, 0x0E); /* 5.4V */
-			if (ret) {
-				dprintf(CRITICAL, "VPOS Register: I2C Write failure\n");
-			}
-
-			ret = qrd_lcd_i2c_write(QRD_LCD_VNEG_ADDRESS, 0x0E); /* -5.4V */
-			if (ret) {
-				dprintf(CRITICAL, "VNEG Register: I2C write failure\n");
-			}
-
-			ret = qrd_lcd_i2c_write(QRD_LCD_DIS_ADDRESS, 0x0F);
-			if (ret) {
-				dprintf(CRITICAL, "Apps freq DIS Register: I2C write failure\n");
-			}
-
-			ret = qrd_lcd_i2c_write(QRD_LCD_CONTROL_ADDRESS, 0xF0);
-			if (ret) {
-				dprintf(CRITICAL, "Control Register: I2C write failure\n");
-			}
+		if (platform_is_msm8939()) {
+			if ((hw_id == HW_PLATFORM_QRD) &&
+				 (hw_subtype == HW_PLATFORM_SUBTYPE_SKUK))
+				target_panel_reset_skuk(enable);
+		} else { /* msm8916 */
+			if ((hw_id == HW_PLATFORM_QRD) &&
+				 (hw_subtype == HW_PLATFORM_SUBTYPE_SKUH))
+				target_panel_reset_skuh(enable);
 		}
 
 		if (hw_id == HW_PLATFORM_MTP || hw_id == HW_PLATFORM_SURF) {
@@ -293,10 +338,14 @@
 		if (pinfo->mipi.use_enable_gpio)
 			gpio_set_dir(enable_gpio.pin_id, 0);
 
-		if(hw_id == HW_PLATFORM_QRD &&
-			hw_subtype == HW_PLATFORM_SUBTYPE_SKUH) {
-			gpio_set_dir(enp_gpio.pin_id, 0); /* ENP */
-			gpio_set_dir(enn_gpio.pin_id, 0); /* ENN */
+		if (platform_is_msm8939()) {
+			if ((hw_id == HW_PLATFORM_QRD) &&
+				 (hw_subtype == HW_PLATFORM_SUBTYPE_SKUK))
+				target_panel_reset_skuk(enable);
+		} else { /* msm8916 */
+			if ((hw_id == HW_PLATFORM_QRD) &&
+				 (hw_subtype == HW_PLATFORM_SUBTYPE_SKUH))
+				target_panel_reset_skuh(enable);
 		}
 	}
 
@@ -314,7 +363,7 @@
 
 bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size)
 {
-	return gcdb_display_cmdline_arg(pbuf, buf_size);
+	return gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
 }
 
 void target_display_init(const char *panel_name)
@@ -322,8 +371,10 @@
 	uint32_t panel_loop = 0;
 	uint32_t ret = 0;
 
-	if (!strcmp(panel_name, NO_PANEL_CONFIG)) {
-		dprintf(INFO, "Skip panel configuration\n");
+	if ((!strcmp(panel_name, NO_PANEL_CONFIG))
+			|| (!strcmp(panel_name, SIM_VIDEO_PANEL))) {
+		dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n",
+								panel_name);
 		return;
 	}
 
diff --git a/target/msm8974/target_display.c b/target/msm8974/target_display.c
index 7d985a3..1c236b6 100755
--- a/target/msm8974/target_display.c
+++ b/target/msm8974/target_display.c
@@ -382,7 +382,7 @@
 		buf_size -= LK_OVERRIDE_PANEL_LEN;
 		strlcat(pbuf, HDMI_CONTROLLER_STRING, buf_size);
 	} else {
-		ret = gcdb_display_cmdline_arg(pbuf, buf_size);
+		ret = gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
 	}
 
 	return ret;
@@ -399,16 +399,16 @@
 
 	panel_name += strspn(panel_name, " ");
 
-	if (!strcmp(panel_name, NO_PANEL_CONFIG)) {
-		dprintf(INFO, "Skip panel configuration\n");
+	if ((!strcmp(panel_name, NO_PANEL_CONFIG))
+			|| (!strcmp(panel_name, SIM_VIDEO_PANEL))
+			|| (!strcmp(panel_name, SIM_DUALDSI_VIDEO_PANEL))) {
+		dprintf(INFO, "Selected panel: %s\nSkip panel configuration",
+								panel_name);
 		return;
-	}
-
-	if (!strcmp(panel_name, HDMI_PANEL_NAME)) {
+	} else if (!strcmp(panel_name, HDMI_PANEL_NAME)) {
 		dprintf(INFO, "%s: HDMI is primary\n", __func__);
 		return;
 	}
-
 	switch (hw_id) {
 	case HW_PLATFORM_LIQUID:
 		edp_panel_init(&(panel.panel_info));
diff --git a/target/msm8994/include/target/display.h b/target/msm8994/include/target/display.h
new file mode 100644
index 0000000..70e5d76
--- /dev/null
+++ b/target/msm8994/include/target/display.h
@@ -0,0 +1,112 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef _TARGET_DISPLAY_H
+#define _TARGET_DISPLAY_H
+
+/*---------------------------------------------------------------------------*/
+/* HEADER files                                                              */
+/*---------------------------------------------------------------------------*/
+#include <display_resource.h>
+
+/*---------------------------------------------------------------------------*/
+/* GPIO configuration                                                        */
+/*---------------------------------------------------------------------------*/
+static struct gpio_pin reset_gpio = {
+  "msmgpio", 78, 3, 1, 0, 1
+};
+
+static struct gpio_pin enable_gpio = {	/* lcd_reg_en */
+  "pm8994_gpios", 14, 3, 1, 0, 1
+};
+
+static struct gpio_pin bkl_gpio = {	/* lcd_bklt_reg_en */
+  "pmi8994_gpios", 2, 3, 1, 0, 1
+};
+
+static struct gpio_pin pwm_gpio = {	/* pmi_mpp01, lpg = 0 */
+  "pmi8994_mpps", 1, 0, 1, 0, 1
+};
+/*---------------------------------------------------------------------------*/
+/* LDO configuration                                                         */
+/*---------------------------------------------------------------------------*/
+static struct ldo_entry ldo_entry_array[] = {
+  { "vdd", 14, 0, 1800000, 100000, 100, 0, 20, 0, 0},
+  { "vddio", 12, 0, 1800000, 100000, 100, 0, 20, 0, 0},
+  { "vdda", 2, 1, 1250000, 100000, 100, 0, 0, 0, 0},
+  { "vcca", 28, 1, 1000000, 10000, 100, 0, 0, 0, 0},
+};
+
+#define TOTAL_LDO_DEFINED 3
+
+/*---------------------------------------------------------------------------*/
+/* Target Physical configuration                                             */
+/*---------------------------------------------------------------------------*/
+
+static const uint32_t panel_strength_ctrl[] = {
+  0x77, 0x06
+};
+
+static const char panel_bist_ctrl[] = {
+  0x00, 0x00, 0xb1, 0xff, 0x00, 0x00
+};
+
+static const uint32_t panel_regulator_settings[] = {
+  0x03, 0x05, 0x03, 0x00, 0x20, 0x07, 0x01
+};
+
+static const char panel_lane_config[] = {
+0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x01, 0x88,
+0x02, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x01, 0x88,
+0x02, 0x00, 0x00, 0x40, 0x20, 0x00, 0x00, 0x01, 0x88,
+0x02, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 0x88,
+0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x01, 0x88
+};
+
+static const uint32_t panel_physical_ctrl[] = {
+  0x5f, 0x00, 0x00, 0x10
+};
+
+/*---------------------------------------------------------------------------*/
+/* Other Configuration                                                       */
+/*---------------------------------------------------------------------------*/
+#define DISPLAY_CMDLINE_PREFIX " mdss_mdp.panel="
+
+#define MIPI_FB_ADDR  0x03400000
+
+#define MIPI_HSYNC_PULSE_WIDTH       16
+#define MIPI_HSYNC_BACK_PORCH_DCLK   32
+#define MIPI_HSYNC_FRONT_PORCH_DCLK  76
+
+#define MIPI_VSYNC_PULSE_WIDTH       2
+#define MIPI_VSYNC_BACK_PORCH_LINES  2
+#define MIPI_VSYNC_FRONT_PORCH_LINES 4
+
+#define PWM_BL_LPG_CHAN_ID           0
+
+#endif
diff --git a/target/msm8994/init.c b/target/msm8994/init.c
index 5c993c2..4a3a5c2 100644
--- a/target/msm8994/init.c
+++ b/target/msm8994/init.c
@@ -55,6 +55,7 @@
 #include <boot_device.h>
 #include <qmp_phy.h>
 #include <qusb2_phy.h>
+#include <rpm-smd.h>
 
 #define CE_INSTANCE             2
 #define CE_EE                   1
@@ -71,6 +72,7 @@
 #define FASTBOOT_MODE           0x77665500
 
 #define BOOT_DEVICE_MASK(val)   ((val & 0x3E) >>1)
+#define PMIC_WLED_SLAVE_ID      3
 
 static void set_sdc_power_ctrl(void);
 static uint32_t mmc_pwrctl_base[] =
@@ -145,6 +147,8 @@
 
 	if (crypto_initialized())
 		crypto_eng_cleanup();
+
+	rpm_smd_uninit();
 }
 
 /* Do target specific usb initialization */
@@ -160,9 +164,6 @@
 		qusb2_phy_reset();
 	}
 
-	/* Select and enable external configuration with USB PHY */
-	ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_SET);
-
 	/* Enable sess_vld */
 	val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN;
 	writel(val, USB_GENCONFIG_2);
@@ -175,8 +176,6 @@
 
 void target_usb_stop(void)
 {
-	/* Disable VBUS mimicing in the controller. */
-	ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_CLEAR);
 }
 
 static void set_sdc_power_ctrl()
@@ -280,6 +279,12 @@
 		dprintf(CRITICAL, "Error reading the partition table info\n");
 		ASSERT(0);
 	}
+
+	rpm_smd_init();
+
+	/* QPNP WLED init for display backlight */
+	pm8x41_wled_config_slave_id(PMIC_WLED_SLAVE_ID);
+	qpnp_wled_init();
 }
 
 unsigned board_machtype(void)
@@ -293,6 +298,22 @@
 	/* This is filled from board.c */
 }
 
+/* Returns 1 if target supports continuous splash screen. */
+int target_cont_splash_screen()
+{
+        switch(board_hardware_id())
+        {
+                case HW_PLATFORM_SURF:
+                case HW_PLATFORM_MTP:
+                case HW_PLATFORM_FLUID:
+                        dprintf(SPEW, "Target_cont_splash=1\n");
+                        return 1;
+                default:
+                        dprintf(SPEW, "Target_cont_splash=0\n");
+                        return 0;
+        }
+}
+
 /* Detect the modem type */
 void target_baseband_detect(struct board_data *board)
 {
@@ -304,6 +325,9 @@
 	case MSM8994:
 		board->baseband = BASEBAND_MSM;
 		break;
+	case APQ8094:
+		board->baseband = BASEBAND_APQ;
+		break;
 	default:
 		dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
 		ASSERT(0);
@@ -383,6 +407,8 @@
 /* identify the usb controller to be used for the target */
 const char * target_usb_controller()
 {
+    if(board_hardware_id() == HW_PLATFORM_DRAGON)
+	    return "ci";
 	return "dwc";
 }
 
@@ -459,3 +485,9 @@
 
 	ASSERT(0);
 }
+
+void target_fastboot_init(void)
+{
+	/* We are entering fastboot mode, so read partition table */
+	mmc_read_partition_table(1);
+}
diff --git a/target/msm8994/oem_panel.c b/target/msm8994/oem_panel.c
new file mode 100644
index 0000000..15049a8
--- /dev/null
+++ b/target/msm8994/oem_panel.c
@@ -0,0 +1,223 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  * Neither the name of The Linux Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <err.h>
+#include <smem.h>
+#include <msm_panel.h>
+#include <board.h>
+#include <mipi_dsi.h>
+
+#include "include/panel.h"
+#include "panel_display.h"
+
+/*---------------------------------------------------------------------------*/
+/* GCDB Panel Database                                                       */
+/*---------------------------------------------------------------------------*/
+#include "include/panel_sharp_wqxga_dualdsi_video.h"
+#include "include/panel_jdi_qhd_dualdsi_video.h"
+#include "include/panel_jdi_qhd_dualdsi_cmd.h"
+
+/*---------------------------------------------------------------------------*/
+/* static panel selection variable                                           */
+/*---------------------------------------------------------------------------*/
+enum {
+SHARP_WQXGA_DUALDSI_VIDEO_PANEL,
+JDI_QHD_DUALDSI_VIDEO_PANEL,
+JDI_QHD_DUALDSI_CMD_PANEL,
+UNKNOWN_PANEL
+};
+
+/*
+ * The list of panels that are supported on this target.
+ * Any panel in this list can be selected using fastboot oem command.
+ */
+static struct panel_list supp_panels[] = {
+	{"sharp_wqxga_dualdsi_video", SHARP_WQXGA_DUALDSI_VIDEO_PANEL},
+	{"jdi_qhd_dualdsi_video", JDI_QHD_DUALDSI_VIDEO_PANEL},
+	{"jdi_qhd_dualdsi_cmd", JDI_QHD_DUALDSI_CMD_PANEL},
+};
+
+static uint32_t panel_id;
+
+int oem_panel_rotation()
+{
+	/* OEM can keep there panel specific on instructions in this
+	function */
+	return NO_ERROR;
+}
+
+int oem_panel_on()
+{
+	/* OEM can keep there panel specific on instructions in this
+	function */
+	if (panel_id == JDI_QHD_DUALDSI_CMD_PANEL) {
+		/* needs extra delay to avoid unexpected artifacts */
+		mdelay(JDI_QHD_DUALDSI_CMD_PANEL_ON_DELAY);
+
+	}
+	return NO_ERROR;
+}
+
+int oem_panel_off()
+{
+	/* OEM can keep there panel specific off instructions in this
+	function */
+	return NO_ERROR;
+}
+
+static bool init_panel_data(struct panel_struct *panelstruct,
+			struct msm_panel_info *pinfo,
+			struct mdss_dsi_phy_ctrl *phy_db)
+{
+	int pan_type;
+
+	phy_db->is_pll_20nm = 1;
+
+	switch (panel_id) {
+	case SHARP_WQXGA_DUALDSI_VIDEO_PANEL:
+		pan_type = PANEL_TYPE_DSI;
+		panelstruct->paneldata    = &sharp_wqxga_dualdsi_video_panel_data;
+		panelstruct->paneldata->panel_operating_mode = 11;
+		panelstruct->paneldata->panel_with_enable_gpio = 0;
+		panelstruct->panelres     = &sharp_wqxga_dualdsi_video_panel_res;
+		panelstruct->color        = &sharp_wqxga_dualdsi_video_color;
+		panelstruct->videopanel   = &sharp_wqxga_dualdsi_video_video_panel;
+		panelstruct->commandpanel = &sharp_wqxga_dualdsi_video_command_panel;
+		panelstruct->state        = &sharp_wqxga_dualdsi_video_state;
+		panelstruct->laneconfig   = &sharp_wqxga_dualdsi_video_lane_config;
+		panelstruct->paneltiminginfo
+			= &sharp_wqxga_dualdsi_video_timing_info;
+		panelstruct->panelresetseq
+					 = &sharp_wqxga_dualdsi_video_reset_seq;
+		panelstruct->backlightinfo = &sharp_wqxga_dualdsi_video_backlight;
+		pinfo->mipi.panel_cmds
+			= sharp_wqxga_dualdsi_video_on_command;
+		pinfo->mipi.num_of_panel_cmds
+			= SHARP_WQXGA_DUALDSI_VIDEO_ON_COMMAND;
+		memcpy(phy_db->timing,
+			sharp_wqxga_dualdsi_video_timings, TIMING_SIZE);
+		break;
+	case JDI_QHD_DUALDSI_VIDEO_PANEL:
+		pan_type = PANEL_TYPE_DSI;
+		panelstruct->paneldata    = &jdi_qhd_dualdsi_video_panel_data;
+		panelstruct->panelres     = &jdi_qhd_dualdsi_video_panel_res;
+		panelstruct->color        = &jdi_qhd_dualdsi_video_color;
+		panelstruct->videopanel   = &jdi_qhd_dualdsi_video_video_panel;
+		panelstruct->commandpanel = &jdi_qhd_dualdsi_video_command_panel;
+		panelstruct->state        = &jdi_qhd_dualdsi_video_state;
+		panelstruct->laneconfig   = &jdi_qhd_dualdsi_video_lane_config;
+		panelstruct->paneltiminginfo
+			= &jdi_qhd_dualdsi_video_timing_info;
+		panelstruct->panelresetseq
+					 = &jdi_qhd_dualdsi_video_reset_seq;
+
+		/* force backlight to WLED */
+		panelstruct->backlightinfo = &jdi_qhd_dualdsi_video_backlight;
+		jdi_qhd_dualdsi_video_backlight.bl_interface_type = BL_WLED;
+
+		pinfo->mipi.panel_cmds
+			= jdi_qhd_dualdsi_video_on_command;
+		pinfo->mipi.num_of_panel_cmds
+			= JDI_QHD_DUALDSI_VIDEO_ON_COMMAND;
+		memcpy(phy_db->timing,
+			jdi_qhd_dualdsi_video_timings, TIMING_SIZE);
+		break;
+	case JDI_QHD_DUALDSI_CMD_PANEL:
+		pan_type = PANEL_TYPE_DSI;
+		panelstruct->paneldata    = &jdi_qhd_dualdsi_cmd_panel_data;
+		panelstruct->panelres     = &jdi_qhd_dualdsi_cmd_panel_res;
+		panelstruct->color        = &jdi_qhd_dualdsi_cmd_color;
+		panelstruct->videopanel   = &jdi_qhd_dualdsi_cmd_video_panel;
+		panelstruct->commandpanel = &jdi_qhd_dualdsi_cmd_command_panel;
+		panelstruct->state        = &jdi_qhd_dualdsi_cmd_state;
+		panelstruct->laneconfig   = &jdi_qhd_dualdsi_cmd_lane_config;
+		panelstruct->paneltiminginfo
+			= &jdi_qhd_dualdsi_cmd_timing_info;
+		panelstruct->panelresetseq
+					 = &jdi_qhd_dualdsi_cmd_reset_seq;
+
+		/* force backlight to WLED */
+		jdi_qhd_dualdsi_cmd_backlight.bl_interface_type = BL_WLED;
+		panelstruct->backlightinfo = &jdi_qhd_dualdsi_cmd_backlight;
+
+		pinfo->mipi.panel_cmds
+			= jdi_qhd_dualdsi_cmd_on_command;
+		pinfo->mipi.num_of_panel_cmds
+			= JDI_QHD_DUALDSI_CMD_ON_COMMAND;
+		memcpy(phy_db->timing,
+			jdi_qhd_dualdsi_cmd_timings, TIMING_SIZE);
+		break;
+	default:
+	case UNKNOWN_PANEL:
+		pan_type = PANEL_TYPE_UNKNOWN;
+		break;
+	}
+	return pan_type;
+}
+
+bool oem_panel_select(const char *panel_name, struct panel_struct *panelstruct,
+			struct msm_panel_info *pinfo,
+			struct mdss_dsi_phy_ctrl *phy_db)
+{
+	uint32_t hw_id = board_hardware_id();
+	int32_t panel_override_id;
+
+	if (panel_name) {
+		panel_override_id = panel_name_to_id(supp_panels,
+				ARRAY_SIZE(supp_panels), panel_name);
+
+		if (panel_override_id < 0) {
+			dprintf(CRITICAL, "Not able to search the panel:%s\n",
+					 panel_name + strspn(panel_name, " "));
+		} else if (panel_override_id < UNKNOWN_PANEL) {
+			/* panel override using fastboot oem command */
+			panel_id = panel_override_id;
+
+			dprintf(INFO, "OEM panel override:%s\n",
+					panel_name + strspn(panel_name, " "));
+			goto panel_init;
+		}
+	}
+
+	switch (hw_id) {
+	case HW_PLATFORM_MTP:
+	case HW_PLATFORM_FLUID:
+	case HW_PLATFORM_SURF:
+		panel_id = SHARP_WQXGA_DUALDSI_VIDEO_PANEL;
+		break;
+	default:
+		dprintf(CRITICAL, "Display not enabled for %d HW type\n"
+					, hw_id);
+		return PANEL_TYPE_UNKNOWN;
+	}
+
+panel_init:
+	return init_panel_data(panelstruct, pinfo, phy_db);
+}
diff --git a/target/msm8994/rules.mk b/target/msm8994/rules.mk
index 3d6d853..509c91a 100644
--- a/target/msm8994/rules.mk
+++ b/target/msm8994/rules.mk
@@ -1,6 +1,7 @@
 LOCAL_DIR := $(GET_LOCAL_DIR)
 
 INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+INCLUDES += -I$(LK_TOP_DIR)/dev/gcdb/display -I$(LK_TOP_DIR)/dev/gcdb/display/include
 
 PLATFORM := msm8994
 
@@ -11,14 +12,16 @@
 
 SCRATCH_ADDR := 0x10000000
 
-DEFINES += DISPLAY_SPLASH_SCREEN=0
+DEFINES += DISPLAY_SPLASH_SCREEN=1
 DEFINES += DISPLAY_TYPE_MIPI=1
 DEFINES += DISPLAY_TYPE_DSI6G=1
 
 MODULES += \
 	dev/keys \
 	dev/pmic/pm8x41 \
+	dev/qpnp_wled \
     lib/ptable \
+	dev/gcdb/display \
     lib/libfdt
 
 DEFINES += \
@@ -34,3 +37,5 @@
 OBJS += \
     $(LOCAL_DIR)/init.o \
     $(LOCAL_DIR)/meminfo.o \
+    $(LOCAL_DIR)/target_display.o \
+    $(LOCAL_DIR)/oem_panel.o
diff --git a/target/msm8994/target_display.c b/target/msm8994/target_display.c
new file mode 100644
index 0000000..57dfe20
--- /dev/null
+++ b/target/msm8994/target_display.c
@@ -0,0 +1,315 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  * Neither the name of The Linux Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <smem.h>
+#include <err.h>
+#include <msm_panel.h>
+#include <mipi_dsi.h>
+#include <pm8x41.h>
+#include <pm8x41_wled.h>
+#include <qpnp_wled.h>
+#include <board.h>
+#include <mdp5.h>
+#include <scm.h>
+#include <endian.h>
+#include <platform/gpio.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+#include <target/display.h>
+#include "include/panel.h"
+#include "include/display_resource.h"
+
+#define HFPLL_LDO_ID 12
+
+#define GPIO_STATE_LOW 0
+#define GPIO_STATE_HIGH 2
+#define RESET_GPIO_SEQ_LEN 3
+
+#define PWM_DUTY_US 13
+#define PWM_PERIOD_US 27
+#define PMIC_WLED_SLAVE_ID 3
+#define PMIC_MPP_SLAVE_ID 2
+
+static void dsi_pll_20nm_phy_init( uint32_t pll_base, int off)
+{
+	mdss_dsi_pll_20nm_sw_reset_st_machine(pll_base);
+
+	dmb();
+
+        /* MMSS_DSI_0_PHY_DSIPHY_CTRL_1 */
+        writel(0x80, pll_base + off + 0x0174);
+
+        /* MMSS_DSI_0_PHY_DSIPHY_CTRL_1 */
+        writel(0x00, pll_base + off + 0x0174);
+        udelay(5000);
+        /* Strength ctrl 0 */
+        writel(0x77, pll_base + off + 0x0184);
+        /* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */
+        writel(0x7f, pll_base + off + 0x0170);
+
+        /* DSI_0_PHY_DSIPHY_GLBL_TEST_CTRL */
+        writel(0x00, pll_base + off + 0x01d4);
+
+        /* MMSS_DSI_0_PHY_DSIPHY_CTRL_2 */
+        writel(0x00, pll_base + off + 0x0178);
+}
+
+static uint32_t dsi_pll_20nm_enable_seq(uint32_t pll_base)
+{
+	uint32_t pll_locked;
+
+        /*
+         * PLL power up sequence.
+         * Add necessary delays recommeded by hardware.
+         */
+        writel(0x0D, pll_base + 0x9c); /* MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN */
+        writel(0x07, pll_base + 0x14); /* MMSS_DSI_PHY_PLL_PLL_CNTRL */
+        writel(0x00, pll_base + 0x2c); /* MMSS_DSI_PHY_PLL_PLL_BKG_KVCO_CAL_EN */
+        udelay(500);
+
+        dsi_pll_20nm_phy_init(pll_base, 0x200); /* Ctrl 0 */
+	dmb();
+
+        pll_locked = mdss_dsi_pll_20nm_lock_status(pll_base);
+        if (!pll_locked)
+                dprintf(INFO, "%s: DSI PLL lock failed\n", __func__);
+        else
+                dprintf(INFO, "%s: DSI PLL lock Success\n", __func__);
+
+	return  pll_locked;
+}
+
+static int msm8994_wled_backlight_ctrl(uint8_t enable)
+{
+	uint8_t slave_id = 3;
+
+	if (enable) {
+		pm8x41_wled_config_slave_id(slave_id);
+		qpnp_wled_enable_backlight(enable);
+	}
+	qpnp_ibb_enable(enable);
+	return NO_ERROR;
+}
+
+static int msm8994_pwm_backlight_ctrl(uint8_t enable)
+{
+	dprintf(INFO, "%s: NOt implemented\n", __func__);
+	return NO_ERROR;
+}
+
+void lcd_reg_en(void)
+{
+       struct pm8x41_gpio gpio = {
+                .direction = PM_GPIO_DIR_OUT,
+                .function = PM_GPIO_FUNC_HIGH,
+                .vin_sel = 2,   /* VIN_2 */
+                .output_buffer = PM_GPIO_OUT_CMOS,
+                .out_strength = PM_GPIO_OUT_DRIVE_MED,
+        };
+
+        pm8x41_gpio_config(14, &gpio);
+	pm8x41_gpio_set(14, 1);
+}
+
+int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
+{
+	uint32_t ret = NO_ERROR;
+	struct pm8x41_mpp mpp;
+	int rc;
+
+	if (!bl) {
+		dprintf(CRITICAL, "backlight structure is not available\n");
+		return ERR_INVALID_ARGS;
+	}
+
+	switch (bl->bl_interface_type) {
+	case BL_WLED:
+		/* Enable MPP4 */
+		pmi8994_config_mpp_slave_id(PMIC_MPP_SLAVE_ID);
+	        mpp.base = PM8x41_MMP4_BASE;
+		mpp.vin = MPP_VIN2;
+		if (enable) {
+			pm_pwm_enable(false);
+			rc = pm_pwm_config(PWM_DUTY_US, PWM_PERIOD_US);
+			if (rc < 0) {
+				mpp.mode = MPP_HIGH;
+			} else {
+				mpp.mode = MPP_DTEST1;
+				pm_pwm_enable(true);
+			}
+			pm8x41_config_output_mpp(&mpp);
+			pm8x41_enable_mpp(&mpp, MPP_ENABLE);
+		} else {
+			pm_pwm_enable(false);
+			pm8x41_enable_mpp(&mpp, MPP_DISABLE);
+		}
+		/* Need delay before power on regulators */
+		mdelay(20);
+		/* Enable WLED backlight control */
+		ret = msm8994_wled_backlight_ctrl(enable);
+		break;
+	case BL_PWM:
+		ret = msm8994_pwm_backlight_ctrl(enable);
+		break;
+	default:
+		dprintf(CRITICAL, "backlight type:%d not supported\n",
+						bl->bl_interface_type);
+		return ERR_NOT_SUPPORTED;
+	}
+
+	return ret;
+}
+
+int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
+{
+	uint32_t ret;
+	struct mdss_dsi_pll_config *pll_data;
+	uint32_t dual_dsi = pinfo->mipi.dual_dsi;
+
+	pll_data = pinfo->mipi.dsi_pll_config;
+	if (enable) {
+		mdp_gdsc_ctrl(enable);
+		mmss_bus_clock_enable();
+		mdp_clock_enable();
+		ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
+		if (ret) {
+			dprintf(CRITICAL,
+				"%s: Failed to restore MDP security configs",
+				__func__);
+			mdp_clock_disable();
+			mmss_bus_clock_disable();
+			mdp_gdsc_ctrl(0);
+			return ret;
+		}
+		mdss_dsi_auto_pll_20nm_config(DSI0_PLL_BASE,
+						MIPI_DSI0_BASE, pll_data);
+		dsi_pll_20nm_enable_seq(DSI0_PLL_BASE);
+		mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, dual_dsi,
+					pll_data->pclk_m,
+					pll_data->pclk_n,
+					pll_data->pclk_d);
+	} else if(!target_cont_splash_screen()) {
+		/* Disable clocks if continuous splash off */
+		mmss_dsi_clock_disable(dual_dsi);
+		mdp_clock_disable();
+		mmss_bus_clock_disable();
+		mdp_gdsc_ctrl(enable);
+	}
+
+	return NO_ERROR;
+}
+
+int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
+					struct msm_panel_info *pinfo)
+{
+	uint32_t i = 0;
+
+	if (enable) {
+		gpio_tlmm_config(reset_gpio.pin_id, 0,
+				reset_gpio.pin_direction, reset_gpio.pin_pull,
+				reset_gpio.pin_strength, reset_gpio.pin_state);
+		/* reset */
+		for (i = 0; i < RESET_GPIO_SEQ_LEN; i++) {
+			if (resetseq->pin_state[i] == GPIO_STATE_LOW)
+				gpio_set(reset_gpio.pin_id, GPIO_STATE_LOW);
+			else
+				gpio_set(reset_gpio.pin_id, GPIO_STATE_HIGH);
+			mdelay(resetseq->sleep[i]);
+		}
+	} else {
+		gpio_set(reset_gpio.pin_id, 0);
+	}
+
+	return NO_ERROR;
+}
+
+int target_ldo_ctrl(uint8_t enable)
+{
+	if (enable) {
+		regulator_enable();	/* L2, L12, L14, and L28 */
+		mdelay(10);
+		qpnp_ibb_enable(true);	/* +5V and -5V */
+		mdelay(50);
+	} else {
+		regulator_disable();
+	}
+
+	return NO_ERROR;
+}
+
+int target_display_pre_on()
+{
+	writel(0x000000FA, MDP_QOS_REMAPPER_CLASS_0);
+	writel(0x00000055, MDP_QOS_REMAPPER_CLASS_1);
+	writel(0xC0000CCD, MDP_CLK_CTRL0);
+	writel(0xD0000CCC, MDP_CLK_CTRL1);
+	writel(0x00CCCCCC, MDP_CLK_CTRL2);
+	writel(0x000000CC, MDP_CLK_CTRL6);
+	writel(0x0CCCC0C0, MDP_CLK_CTRL3);
+	writel(0xCCCCC0C0, MDP_CLK_CTRL4);
+	writel(0xCCCCC0C0, MDP_CLK_CTRL5);
+	writel(0x00CCC000, MDP_CLK_CTRL7);
+
+	writel(0x00080808, VBIF_VBIF_IN_RD_LIM_CONF0);
+	writel(0x08000808, VBIF_VBIF_IN_RD_LIM_CONF1);
+	writel(0x00080808, VBIF_VBIF_IN_RD_LIM_CONF2);
+	writel(0x00000808, VBIF_VBIF_IN_RD_LIM_CONF3);
+	writel(0x10000000, VBIF_VBIF_IN_WR_LIM_CONF0);
+	writel(0x00100000, VBIF_VBIF_IN_WR_LIM_CONF1);
+	writel(0x10000000, VBIF_VBIF_IN_WR_LIM_CONF2);
+	writel(0x00000000, VBIF_VBIF_IN_WR_LIM_CONF3);
+	writel(0x00013fff, VBIF_VBIF_ABIT_SHORT);
+	writel(0x000000A4, VBIF_VBIF_ABIT_SHORT_CONF);
+	writel(0x00003FFF, VBIF_VBIF_GATE_OFF_WRREQ_EN);
+	writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB);
+
+	return NO_ERROR;
+}
+
+bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size)
+{
+	int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX);
+	bool ret = true;
+
+	ret = gcdb_display_cmdline_arg(panel_name, pbuf, buf_size);
+
+	return ret;
+}
+
+void target_display_init(const char *panel_name)
+{
+	if (gcdb_display_init(panel_name, MDP_REV_50, MIPI_FB_ADDR))
+		msm_display_off();
+}
+
+void target_display_shutdown(void)
+{
+	gcdb_display_shutdown();
+}
diff --git a/target/msmzirc/rules.mk b/target/msmzirc/rules.mk
index a69e059..c0831cc 100644
--- a/target/msmzirc/rules.mk
+++ b/target/msmzirc/rules.mk
@@ -4,14 +4,14 @@
 
 PLATFORM := msmzirc
 
-MEMBASE                             := 0x8F100000
+MEMBASE                             := 0x87C00000
 MEMSIZE                             := 0x00100000 # 1MB
 BASE_ADDR                           := 0x80000000
-SCRATCH_ADDR                        := 0x90000000
-SCRATCH_REGION1                     := 0x90000000
-SCRATCH_REGION1_SIZE                := 0x01000000 #16MB
-SCRATCH_REGION2                     := 0x91300000
-SCRATCH_REGION2_SIZE                := 0x06B00000 # 107MB
+SCRATCH_ADDR                        := 0x80000000
+SCRATCH_REGION1                     := 0x80000000
+SCRATCH_REGION1_SIZE                := 0x07C00000 # 124MB
+SCRATCH_REGION2                     := 0x88000000
+SCRATCH_REGION2_SIZE                := 0x08000000 # 128MB
 
 DEFINES += NO_KEYPAD_DRIVER=1
 DEFINES += PERIPH_BLK_BLSP=1