| commit | 36e609fdf79d307c40c5b6991c160b8ccdff2c55 | [log] [tgz] |
|---|---|---|
| author | Padmanabhan Komanduru <pkomandu@codeaurora.org> | Mon May 04 12:52:26 2015 -0700 |
| committer | Padmanabhan Komanduru <pkomandu@codeaurora.org> | Wed May 06 13:10:46 2015 -0700 |
| tree | 513285acc0506db7f0eca676832bcee31511d745 | |
| parent | 59dddaa6e73ec796ad8671f268138f4676457690 [diff] |
platform: correct the sequence for enabling DSI pixel clock In the current implementation, the M,N,D values for DSI pixel clock is set after setting the update RCG bit in DSI_PCLK_CMD_RCGR register. This causes the dirty bits for M,N,D to be set in PCLK_CMD_RCGR causing issues during handoff in kernel for DSI pixel clock. Update the sequence to take care of this for multiple targets. Change-Id: Ifcc53ca1787b710cd1a154738a7c1ccd472d22c7