[platform/msm7x30]: Add ISB instruction after updating Cache settings.
Add code replace delay loop with ISB instruction after updating
the L1 and L2 Cache settings.
Change-Id: I35a2c063e3b2dec596e4b07a2b018a75267104a7
CR-Fixed: 230511
diff --git a/platform/msm7x30/arch_init.S b/platform/msm7x30/arch_init.S
index 52c5f61..de44532 100644
--- a/platform/msm7x30/arch_init.S
+++ b/platform/msm7x30/arch_init.S
@@ -288,13 +288,7 @@
WRITE_L2_SA_SETTINGS:
//;WCP15_L2VR3F1 r0
MCR p15, 0x3, r0, c15, c15, 0x1 //;write r0 to L2VR3F1
-
- LDR r0, =0x20 //;additional delay for amp setting
- LDR r1, =0x0
-loop:
- SUBS r0, r0, #0x1
- CMP r0, r1
- BNE loop
+ ISB
LDR r0, =0 //;make sure the registers we touched
LDR r1, =0 //;are cleared when we return