platform: apq8084: Fix the M, N & D setting for dsi_1
Fix M, N and D registers setting for DSI_1
Change-Id: I4ae6470b1eda1484a0b43e0b46ed4e76e9c19d56
diff --git a/platform/apq8084/acpuclock.c b/platform/apq8084/acpuclock.c
index bfae903..386b558 100644
--- a/platform/apq8084/acpuclock.c
+++ b/platform/apq8084/acpuclock.c
@@ -391,9 +391,9 @@
writel(0x1, DSI_PIXEL1_CMD_RCGR);
writel(0x1, DSI_PIXEL1_CBCR);
- writel(pclk0_m, DSI_PIXEL0_M);
- writel(pclk0_n, DSI_PIXEL0_N);
- writel(pclk0_d, DSI_PIXEL0_D);
+ writel(pclk0_m, DSI_PIXEL1_M);
+ writel(pclk0_n, DSI_PIXEL1_N);
+ writel(pclk0_d, DSI_PIXEL1_D);
/* Configure ESC clock */
ret = clk_get_set_enable("mdss_esc1_clk", 0, 1);