commit 3dcc4ed8a60bb7b6c30b964ec476728d999f9427
author Channagoud Kadabi <ckadabi@codeaurora.org> Thu Apr 10 14:59:41 2014 -0700
committer Gerrit - the friendly Code Review server <code-review@localhost> Tue May 13 10:44:20 2014 -0700
tree 2cd19342052a71c45c025a28994f80860132a53c
parent 75fe3ea00fe3a581471d73bad522d1650243d6cd

target/platform: msm8994: Add usb30 support

Add support for usb30 clocks, phy and target init
code.

CRs-Fixed: 636135
Change-Id: I260eef5fff73a431ba89b095def92fe0070b1662

platform/msm8994/include/platform/iomap.h

diff --git a/platform/msm8994/include/platform/iomap.h b/platform/msm8994/include/platform/iomap.h
index 4a6c22d..592a369 100644
--- a/platform/msm8994/include/platform/iomap.h
+++ b/platform/msm8994/include/platform/iomap.h
@@ -76,6 +76,12 @@
 
 #define MSM_USB_BASE                (PERIPH_SS_BASE + 0x00255000)
 
+#define MSM_USB30_BASE              0xF9200000
+#define MSM_USB30_QSCRATCH_BASE     0xF92F8800
+
+/* SS QMP (Qulacomm Multi Protocol) */
+#define QMP_PHY_BASE                0xF9B38000
+
 /* Clocks */
 #define CLK_CTL_BASE                0xFC400000
 
@@ -109,6 +115,29 @@
 #define USB_HS_SYSTEM_CMD_RCGR      (CLK_CTL_BASE + 0x490)
 #define USB_HS_SYSTEM_CFG_RCGR      (CLK_CTL_BASE + 0x494)
 
+/* USB3 clocks */
+#define SYS_NOC_USB3_AXI_CBCR       (CLK_CTL_BASE + 0x03FC)
+#define USB2B_PHY_SLEEP_CBCR        (CLK_CTL_BASE + 0x04AC)
+#define USB2B_PHY_BCR               (CLK_CTL_BASE + 0x04A8)
+#define USB30_MASTER_CMD_RCGR       (CLK_CTL_BASE + 0x03D4)
+#define USB30_MASTER_CFG_RCGR       (CLK_CTL_BASE + 0x03D8)
+#define USB30_MASTER_M              (CLK_CTL_BASE + 0x03DC)
+#define USB30_MASTER_N              (CLK_CTL_BASE + 0x03E0)
+#define USB30_MASTER_D              (CLK_CTL_BASE + 0x03E4)
+#define USB30_MASTER_CBCR           (CLK_CTL_BASE + 0x03C8)
+#define USB_30_BCR                  (CLK_CTL_BASE + 0x03C0)
+#define USB30_MOCK_UTMI_CMD_RCGR    (CLK_CTL_BASE + 0x03E8)
+#define USB30_MOCK_UTMI_CFG_RCGR    (CLK_CTL_BASE + 0x03EC)
+#define USB30_MOCK_UTMI_CBCR        (CLK_CTL_BASE + 0x03D0)
+#define USB30_SLEEP_CBCR            (CLK_CTL_BASE + 0x03CC)
+#define USB30_PHY_AUX_CMD_RCGR      (CLK_CTL_BASE + 0x1414)
+#define USB30_PHY_AUX_CFG_RCGR      (CLK_CTL_BASE + 0x1418)
+#define USB30_PHY_AUX_CBCR          (CLK_CTL_BASE + 0x1408)
+#define USB30_PHY_PIPE_CBCR         (CLK_CTL_BASE + 0x140C)
+#define USB30_PHY_BCR               (CLK_CTL_BASE + 0x1400)
+#define USB30PHY_PHY_BCR            (CLK_CTL_BASE + 0x1404)
+#define GCC_USB30_GDSCR             (CLK_CTL_BASE + 0x03C4)
+
 /* SDCC */
 #define SDCC1_BCR                   (CLK_CTL_BASE + 0x4C0) /* block reset */
 #define SDCC1_APPS_CBCR             (CLK_CTL_BASE + 0x4C4) /* branch control */
@@ -167,4 +196,7 @@
 
 #define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL    0xFC4A3000
 
+#define TCSR_PHSS_USB2_PHY_SEL               0xFD4AB000
+#define PLATFORM_QMP_OFFSET                  0x8
+
 #endif