diff --git a/dev/keys/gpio_keypad.c b/dev/keys/gpio_keypad.c
index 4fc2e4e..02e86fb 100644
--- a/dev/keys/gpio_keypad.c
+++ b/dev/keys/gpio_keypad.c
@@ -348,6 +348,64 @@
     return 0;
 }
 
+int pa2_ssbi2_read_bytes(unsigned char  *buffer, unsigned short length,
+        unsigned short slave_addr)
+{
+    unsigned val = 0x0;
+    unsigned temp = 0x0000;
+    unsigned char *buf = buffer;
+    unsigned short len = length;
+    unsigned short addr = slave_addr;
+    unsigned long timeout = SSBI_TIMEOUT_US;
+
+    while(len)
+    {
+        val |= ((addr << PA2_SSBI2_REG_ADDR_SHIFT) |
+                (PA2_SSBI2_CMD_READ << PA2_SSBI2_CMD_RDWRN_SHIFT));
+        writel(val, PA2_SSBI2_CMD);
+        while(!((temp = readl(PA2_SSBI2_RD_STATUS)) & (1 << PA2_SSBI2_TRANS_DONE_SHIFT))) {
+            if (--timeout == 0) {
+                dprintf(INFO, "In Device ready function:Timeout\n");
+                return 1;
+            }
+        }
+        len--;
+        *buf++ = (temp & (PA2_SSBI2_REG_DATA_MASK << PA2_SSBI2_REG_DATA_SHIFT));
+    }
+    return 0;
+}
+
+int pa2_ssbi2_write_bytes(unsigned char  *buffer, unsigned short length,
+        unsigned short slave_addr)
+{
+    unsigned val;
+    unsigned char *buf = buffer;
+    unsigned short len = length;
+    unsigned short addr = slave_addr;
+    unsigned temp = 0x00;
+    unsigned char written_data1 = 0x00;
+    unsigned long timeout = SSBI_TIMEOUT_US;
+
+    while(len)
+    {
+        temp = 0x00;
+        written_data1 = 0x00;
+        val = (addr << PA2_SSBI2_REG_ADDR_SHIFT) |
+            (PA2_SSBI2_CMD_WRITE << PA2_SSBI2_CMD_RDWRN_SHIFT) |
+            (*buf & 0xFF);
+        writel(val, PA2_SSBI2_CMD);
+        while(!((temp = readl(PA2_SSBI2_RD_STATUS)) & (1 << PA2_SSBI2_TRANS_DONE_SHIFT))) {
+            if (--timeout == 0) {
+                dprintf(INFO, "In Device write function:Timeout\n");
+                return 1;
+            }
+        }
+        len--;
+        buf++;
+    }
+    return 0;
+}
+
 int pm8058_gpio_config(int gpio, struct pm8058_gpio *param)
 {
 	int	rc;
diff --git a/include/dev/gpio_keypad.h b/include/dev/gpio_keypad.h
index feada32..f467729 100644
--- a/include/dev/gpio_keypad.h
+++ b/include/dev/gpio_keypad.h
@@ -182,6 +182,19 @@
 #define PA1_SSBI2_CMD_READ              1
 #define PA1_SSBI2_CMD_WRITE             0
 
+/* PMIC Arbiter 2: SSBI2 Configuration Micro ARM registers */
+#define PA2_SSBI2_CMD                   0x00C00000
+#define PA2_SSBI2_RD_STATUS             0x00C00004
+
+#define PA2_SSBI2_REG_ADDR_SHIFT        8
+#define PA2_SSBI2_CMD_RDWRN_SHIFT       24
+#define PA2_SSBI2_TRANS_DONE_SHIFT      27
+
+#define PA2_SSBI2_REG_DATA_MASK         0xFF
+#define PA2_SSBI2_REG_DATA_SHIFT        0
+
+#define PA2_SSBI2_CMD_READ              1
+#define PA2_SSBI2_CMD_WRITE             0
 
 struct pm8058_gpio {
 	int		direction;
diff --git a/platform/msm8x60/acpuclock.c b/platform/msm8x60/acpuclock.c
index 4e5695d..402f844 100755
--- a/platform/msm8x60/acpuclock.c
+++ b/platform/msm8x60/acpuclock.c
@@ -30,8 +30,183 @@
 #include <debug.h>
 #include <kernel/thread.h>
 #include <platform/iomap.h>
+#include <platform/clock.h>
 #include <reg.h>
 
+/* Read, modify, then write-back a register. */
+static void rmwreg(uint32_t val, uint32_t reg, uint32_t mask)
+{
+    uint32_t regval = readl(reg);
+    regval &= ~mask;
+    regval |= val;
+    writel(regval, reg);
+}
+
+
+void config_mdp_axi_clk(uint8_t use_pxo){
+    /* Program MM_PLL0 (PLL1) @ 1320 MHz and turn it on. */
+    rmwreg(0,  MM_PLL0_MODE_REG, (1<<0)); /* Disable output */
+    writel(48, MM_PLL0_L_VAL_REG);
+    writel(8, MM_PLL0_M_VAL_REG);
+    writel(9, MM_PLL0_N_VAL_REG);
+    /* Set ref, enable. */
+    if (use_pxo)
+        rmwreg((1<<1),      MM_PLL0_MODE_REG, (1<<4)|(1<<1)); /* PXO */
+    else
+        rmwreg((1<<4)|(1<<1), MM_PLL0_MODE_REG, (1<<4)|(1<<1)); /* MXO */
+    udelay(10);
+    writel(0x14580, MM_PLL0_CONFIG_REG);  /* Enable MN, set VCO, misc */
+    rmwreg((1<<2), MM_PLL0_MODE_REG, (1<<2)); /* Deassert reset */
+    rmwreg((1<<0), MM_PLL0_MODE_REG, (1<<0)); /* Enable output */
+
+    /* Set up MM AHB clock to PLL8/5. */
+    //local_src_enable(PLL_8);
+    rmwreg(0x0102, AHB_NS_REG, 0x43C7);
+    udelay(200); /* Wait before using registers clocked by MM AHB_CLK. */
+
+    /* Set up MM Fabric (AXI). */
+    writel(0x4248451, AXI_NS_REG);
+}
+
+
+/* Enable/disable for non-shared NT PLLs. */
+int nt_pll_enable(uint8_t src, uint8_t enable)
+{
+    static const struct {
+        uint32_t const mode_reg;
+        uint32_t const status_reg;
+    } pll_reg[] = {
+        [PLL_1] = { MM_PLL0_MODE_REG, MM_PLL0_STATUS_REG },
+        [PLL_2] = { MM_PLL1_MODE_REG, MM_PLL1_STATUS_REG },
+        [PLL_3] = { MM_PLL2_MODE_REG, MM_PLL2_STATUS_REG },
+    };
+    uint32_t pll_mode;
+
+    pll_mode = readl(pll_reg[src].mode_reg);
+    if (enable) {
+        /* Disable PLL bypass mode. */
+        pll_mode |= (1<<1);
+        writel( pll_mode, pll_reg[src].mode_reg);
+
+        /* H/W requires a 5us delay between disabling the bypass and
+         * de-asserting the reset. Delay 10us just to be safe. */
+        udelay(10);
+
+        /* De-assert active-low PLL reset. */
+        pll_mode |= (1<<2);
+        writel( pll_mode, pll_reg[src].mode_reg);
+
+        /* Enable PLL output. */
+        pll_mode |= (1<<0);
+        writel( pll_mode, pll_reg[src].mode_reg);
+
+        /* Wait until PLL is enabled. */
+        while (!readl(pll_reg[src].status_reg));
+    } else {
+        /* Disable the PLL output, disable test mode, enable
+         * the bypass mode, and assert the reset. */
+        pll_mode &= 0xFFFFFFF0;
+        writel( pll_mode, pll_reg[src].mode_reg);
+    }
+
+    return 0;
+}
+
+
+/* Write the M,N,D values and enable the MDP Core Clock */
+void config_mdp_clk(    uint32_t ns,
+        uint32_t md,
+        uint32_t cc,
+        uint32_t ns_addr,
+        uint32_t md_addr,
+        uint32_t cc_addr)
+{
+    int val = 0;
+
+    /* MN counter reset */
+    val = 1 << 31;
+    writel(val, ns_addr);
+
+    /* Write the MD and CC register values */
+    writel(md, md_addr);
+    writel(cc, cc_addr);
+
+    /* Reset the clk control, and Write ns val */
+    val = 1 << 31;
+    val |= ns;
+    writel(val, ns_addr);
+
+    /* Clear MN counter reset */
+    val = 1 << 31;
+    val = ~val;
+    val = val & readl(ns_addr);
+    writel(val, ns_addr);
+
+    /* Enable MND counter */
+    val = 1 << 8;
+    val = val | readl(cc_addr);
+    writel(val, cc_addr);
+
+    /* Enable the root of the clock tree */
+    val = 1 << 2;
+    val = val | readl(cc_addr);
+    writel(val, cc_addr);
+
+    /* Enable the MDP Clock */
+    val = 1 << 0;
+    val = val | readl(cc_addr);
+    writel(val, cc_addr);
+}
+
+/* Write the M,N,D values and enable the Pixel Core Clock */
+void config_pixel_clk(  uint32_t ns,
+        uint32_t md,
+        uint32_t cc,
+        uint32_t ns_addr,
+        uint32_t md_addr,
+        uint32_t cc_addr){
+    unsigned int val = 0;
+
+    /* Activate the reset for the M/N Counter */
+    val = 1 << 7;
+    writel(val, ns_addr);
+
+    /* Write the MD and CC register values */
+    writel(md, md_addr);
+    writel(cc, cc_addr);
+
+    /* Write the ns value, and active reset for M/N Counter, again */
+    val = 1 << 7;
+    val |= ns;
+    writel(val, ns_addr);
+
+    /* De-activate the reset for M/N Counter */
+    val = 1 << 7;
+    val = ~val;
+    val = val & readl(ns_addr);
+    writel(val, ns_addr);
+
+    /* Enable MND counter */
+    val = 1 << 5;
+    val = val | readl(cc_addr);
+    writel(val, cc_addr);
+
+    /* Enable the root of the clock tree */
+    val = 1 << 2;
+    val = val | readl(cc_addr);
+    writel(val, cc_addr);
+
+    /* Enable the MDP Clock */
+    val = 1 << 0;
+    val = val | readl(cc_addr);
+    writel(val, cc_addr);
+
+    /* Enable the LCDC Clock */
+    val = 1 << 8;
+    val = val | readl(cc_addr);
+    writel(val, cc_addr);
+}
+
 /* Set rate and enable the clock */
 void clock_config(uint32_t ns,
         uint32_t md,
diff --git a/platform/msm8x60/include/platform/clock.h b/platform/msm8x60/include/platform/clock.h
new file mode 100755
index 0000000..7763f18
--- /dev/null
+++ b/platform/msm8x60/include/platform/clock.h
@@ -0,0 +1,98 @@
+/*
+ * * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ *  * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __PLATFORM_MSM8X60_CLOCK_H
+#define __PLATFORM_MSM8X60_CLOCK_H
+
+/* MMSS CLK CTR base address */
+#define MSM_MMSS_CLK_CTL    0x04000000
+#define REG_MM(off)     (MSM_MMSS_CLK_CTL + (off))
+
+#define AHB_NS_REG                              REG_MM(0x0004)
+#define AXI_NS_REG                              REG_MM(0x0014)
+#define MM_PLL0_CONFIG_REG                      REG_MM(0x0310)
+#define MM_PLL0_L_VAL_REG                       REG_MM(0x0304)
+#define MM_PLL0_M_VAL_REG                       REG_MM(0x0308)
+#define MM_PLL0_MODE_REG                        REG_MM(0x0300)
+#define MM_PLL0_N_VAL_REG                       REG_MM(0x030C)
+#define MM_PLL0_STATUS_REG                      REG_MM(0x0318)
+#define MM_PLL1_CONFIG_REG                      REG_MM(0x032C)
+#define MM_PLL1_L_VAL_REG                       REG_MM(0x0320)
+#define MM_PLL1_M_VAL_REG                       REG_MM(0x0324)
+#define MM_PLL1_MODE_REG                        REG_MM(0x031C)
+#define MM_PLL1_N_VAL_REG                       REG_MM(0x0328)
+#define MM_PLL1_STATUS_REG                      REG_MM(0x0334)
+#define MM_PLL2_CONFIG_REG                      REG_MM(0x0348)
+#define MM_PLL2_L_VAL_REG                       REG_MM(0x033C)
+#define MM_PLL2_M_VAL_REG                       REG_MM(0x0340)
+#define MM_PLL2_MODE_REG                        REG_MM(0x0338)
+#define MM_PLL2_N_VAL_REG                       REG_MM(0x0344)
+#define MM_PLL2_STATUS_REG                      REG_MM(0x0350)
+
+/* LCD related clock defines */
+#define MMSS_AHB_NS_REG     (MSM_MMSS_CLK_CTL + 0x04)
+#define MMSS_AHB_EN_REG     (MSM_MMSS_CLK_CTL + 0x08)
+#define MMSS_AXI_NS_REG     (MSM_MMSS_CLK_CTL + 0x14)
+#define MMSS_MAXI_EN_REG    (MSM_MMSS_CLK_CTL + 0x18)
+#define MMSS_MAXI_EN2_REG   (MSM_MMSS_CLK_CTL + 0x20)
+#define MMSS_SAXI_EN_REG    (MSM_MMSS_CLK_CTL + 0x30)
+
+#define MDP_CC_REG      (MSM_MMSS_CLK_CTL + 0xC0)
+#define MDP_MD_REG      (MSM_MMSS_CLK_CTL + 0xC4)
+#define MDP_NS_REG      (MSM_MMSS_CLK_CTL + 0xD0)
+#define LCD_PIXEL_CC_REG    (MSM_MMSS_CLK_CTL + 0xD4)
+#define LCD_PIXEL_NS_REG    (MSM_MMSS_CLK_CTL + 0xDC)
+#define LCD_PIXEL_MD_REG    (MSM_MMSS_CLK_CTL + 0xD8)
+
+/* Configured at 200 MHz */
+#define MDP_NS_VAL              0x3F000008
+#define MDP_MD_VAL              0x000001FB
+#define MDP_CC_VAL              0x00000400
+
+/* Configured at 53.99 MHz */
+#define PIXEL_NS_VAL            0xFE4F4002
+#define PIXEL_MD_VAL            0x00A9FDA6
+#define PIXEL_CC_VAL            0x00000080
+
+enum clk_sources {
+    PLL_0 = 0,
+    PLL_1,
+    PLL_2,
+    PLL_3,
+    PLL_4,
+    PLL_5,
+    PLL_6,
+    PLL_7,
+    PLL_8,
+    MXO,
+    PXO,
+    CXO,
+    NUM_SRC
+};
+
+#endif
diff --git a/platform/msm8x60/include/platform/pmic.h b/platform/msm8x60/include/platform/pmic.h
new file mode 100755
index 0000000..d761d9c
--- /dev/null
+++ b/platform/msm8x60/include/platform/pmic.h
@@ -0,0 +1,85 @@
+/*
+ * * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ *  * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __PLATFORM_MSM8X60_PMIC_H
+#define __PLATFORM_MSM8X60_PMIC_H
+
+/* PMIC 8901 LDO Module defines */
+#define PM8901_LDO_BASE (0x2F)
+
+#define PM8901_LDO_L0           (PM8901_LDO_BASE + 0x00)
+#define PM8901_LDO_L0_TEST_BANK     (PM8901_LDO_BASE + 0x01)
+#define PM8901_LDO_L1           (PM8901_LDO_BASE + 0x02)
+#define PM8901_LDO_L1_TEST_BANK     (PM8901_LDO_BASE + 0x03)
+#define PM8901_LDO_L2           (PM8901_LDO_BASE + 0x04)
+#define PM8901_LDO_L2_TEST_BANK     (PM8901_LDO_BASE + 0x05)
+#define PM8901_LDO_L3           (PM8901_LDO_BASE + 0x06)
+#define PM8901_LDO_L3_TEST_BANK     (PM8901_LDO_BASE + 0x07)
+#define PM8901_LDO_L4           (PM8901_LDO_BASE + 0x08)
+#define PM8901_LDO_L4_TEST_BANK     (PM8901_LDO_BASE + 0x09)
+#define PM8901_LDO_L5           (PM8901_LDO_BASE + 0x0A)
+#define PM8901_LDO_L5_TEST_BANK     (PM8901_LDO_BASE + 0x0B)
+#define PM8901_LDO_L6           (PM8901_LDO_BASE + 0x0C)
+#define PM8901_LDO_L6_TEST_BANK     (PM8901_LDO_BASE + 0x0D)
+#define PM8901_LDO_L7           (PM8901_LDO_BASE + 0x0E)
+#define PM8901_LDO_L7_TEST_BANK     (PM8901_LDO_BASE + 0x0F)
+
+#define PM8901_LDO_TEST_BANK(n) ((n)<<4)
+
+#define PM8901_LDO_CTL_ENABLE__S    (7)
+#define PM8901_LDO_CTL_PULL_DOWN__S (6)
+#define PM8901_LDO_CTL_MODE__S      (5)
+/* LDO CTL */
+#define LDO_CTL_ENABLE_MASK     (0x80)
+#define LDO_CTL_PULL_DOWN_MASK      (0x40)
+#define LDO_CTL_NORMAL_POWER_MODE_MASK  (0x20)
+#define LDO_CTL_VOLTAGE_SET_MASK    (0x1F)
+
+/* LDO TEST BANK 2 */
+#define LDO_TEST_RANGE_SELECT_MASK (0x01)
+
+/* LDO TEST BANK 4 */
+#define LDO_TEST_OUTPUT_RANGE_MASK (0x01)
+
+/* LDO TEST BANK 5 */
+#define LDO_TEST_XO_EN_ALL_MASK (0x1F)
+
+/* PMIC 8058 defines */
+#define LPG_CTL_0         (0x13C)
+#define LPG_CTL_1         (0x13D)
+#define LPG_CTL_2         (0x13E)
+#define LPG_CTL_3         (0x13F)
+#define LPG_CTL_4         (0x140)
+#define LPG_CTL_5         (0x141)
+#define LPG_CTL_6         (0x142)
+#define LPG_BANK_SEL      (0x143)
+#define LPG_BANK_ENABLE   (0x144)
+#define GPIO24_GPIO_CNTRL (0x167)
+#define GPIO25_GPIO_CNTRL (0x168)
+
+#endif
diff --git a/platform/msm8x60/panel.c b/platform/msm8x60/panel.c
new file mode 100755
index 0000000..bc29095
--- /dev/null
+++ b/platform/msm8x60/panel.c
@@ -0,0 +1,366 @@
+/*
+ * * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ *  * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <kernel/thread.h>
+#include <i2c_qup.h>
+#include <platform/iomap.h>
+#include <platform/gpio_hw.h>
+#include <platform/clock.h>
+#include <platform/pmic.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static struct qup_i2c_dev *dev = NULL;
+
+uint8_t expander_read(uint8_t addr)
+{
+    uint8_t ret = 0;
+    /* Create a i2c_msg buffer, that is used to put the controller into read
+       mode and then to read some data. */
+    struct i2c_msg msg_buf[] = {
+        {CORE_GPIO_EXPANDER_I2C_ADDRESS, I2C_M_WR, 1, &addr},
+        {CORE_GPIO_EXPANDER_I2C_ADDRESS, I2C_M_RD, 1, &ret}
+    };
+
+    qup_i2c_xfer(dev, msg_buf, 2);
+
+    return ret;
+}
+
+uint8_t expander_write(uint8_t addr, uint8_t val)
+{
+    uint8_t data_buf[] = { addr, val };
+
+    /* Create a i2c_msg buffer, that is used to put the controller into write
+       mode and then to write some data. */
+    struct i2c_msg msg_buf[] = { {CORE_GPIO_EXPANDER_I2C_ADDRESS,
+                                  I2C_M_WR, 2, data_buf}
+    };
+
+    qup_i2c_xfer(dev, msg_buf, 1);
+
+    /* Double check that the write worked. */
+    if (val != expander_read(addr)) {
+        return -1;
+    }
+
+    return 0;
+}
+
+void panel_poweron(void)
+{
+    panel_backlight(1);
+    lcdc_on();
+}
+
+void panel_backlight(int on)
+{
+}
+
+static int display_common_power(int on)
+{
+}
+
+static int lcd_power_on()
+{
+    uint8_t buffer = 0x0, mask = 0x0, prev_val = 0x0;
+    int ret = 0;
+
+    /* Configure LDO L2 TEST Bank 2, to Range Select 0 */
+    buffer = (0x80);            /* Write mode */
+    buffer |= (PM8901_LDO_TEST_BANK(2));    /* Test Bank 2 */
+    mask = buffer | LDO_TEST_RANGE_SELECT_MASK;
+
+    if ((ret = pm8901_test_bank_read(&prev_val,
+                                     PM8901_LDO_TEST_BANK(2),
+                                     PM8901_LDO_L2_TEST_BANK))) {
+        return ret;
+    }
+    if ((ret = pm8901_vreg_write(&buffer, mask, PM8901_LDO_L2_TEST_BANK,
+                                 prev_val))) {
+        return ret;
+    }
+
+    /* Configure LDO L2 TEST Bank 4, for High Range Mode */
+    buffer = (0x80);            /* Write mode */
+    buffer |= (PM8901_LDO_TEST_BANK(4));    /* Test Bank 4 */
+    buffer |= (0x01);           /* Put into High Range Mode */
+    mask = buffer | LDO_TEST_OUTPUT_RANGE_MASK;
+
+    if ((ret = pm8901_test_bank_read(&prev_val,
+                                     PM8901_LDO_TEST_BANK(4),
+                                     PM8901_LDO_L2_TEST_BANK))) {
+        return ret;
+    }
+    if ((ret = pm8901_vreg_write(&buffer, mask, PM8901_LDO_L2_TEST_BANK,
+                                 prev_val))) {
+        return ret;
+    }
+
+    /* Configure LDO L2 TEST Bank 5, for XO_EN<3-0> to 1 */
+    buffer = (0x80);            /* Write mode */
+    buffer |= (PM8901_LDO_TEST_BANK(5));    /* Test Bank 5 */
+    buffer |= (0x0F);           /* Enable XO_EN */
+    mask = buffer | LDO_TEST_XO_EN_ALL_MASK;
+
+    if ((ret = pm8901_test_bank_read(&prev_val,
+                                     PM8901_LDO_TEST_BANK(5),
+                                     PM8901_LDO_L2_TEST_BANK))) {
+        return ret;
+    }
+    if ((ret = pm8901_vreg_write(&buffer, mask, PM8901_LDO_L2_TEST_BANK,
+                                 prev_val))) {
+        return ret;
+    }
+
+    /* Enable LDO L2 at Max Voltage (should be around 3.3v) */
+    buffer = (0x1 << PM8901_LDO_CTL_ENABLE__S);
+    /* Disable Pull Down */
+    buffer |= (0x0 << PM8901_LDO_CTL_PULL_DOWN__S);
+    /* Put LDO into normal mode instead of low power mode */
+    buffer |= (0x0 << PM8901_LDO_CTL_MODE__S);
+    /* Write a 31 into the Voltage Programming value to obtain 3.3v VREG =
+       1.75V + X * 100mV */
+    buffer |= (0x1F);
+    mask = buffer | LDO_CTL_ENABLE_MASK |
+        LDO_CTL_PULL_DOWN_MASK |
+        LDO_CTL_NORMAL_POWER_MODE_MASK | LDO_CTL_VOLTAGE_SET_MASK;
+
+    /* Do a normal read here, as to not destroy the value in LDO control */
+    if ((ret = pm8901_read(&prev_val, 1, PM8901_LDO_L2))) {
+        return ret;
+    }
+    /* Configure the LDO2 for 3.3v */
+    ret = pm8901_vreg_write(&buffer, mask, PM8901_LDO_L2, prev_val);
+    return ret;
+}
+
+/* Configures the GPIO that are needed to enable LCD.
+ * This function also configures the PMIC for PWM control of the LCD backlight.
+ */
+static void lcd_gpio_cfg(uint8_t on)
+{
+    uint32_t func;
+    uint32_t pull;
+    uint32_t dir;
+    uint32_t enable = 0;        /* not used in gpio_tlmm_config */
+    uint32_t drv;
+    if (on) {
+        func = 1;               /* Configure GPIO for LCDC function */
+        pull = GPIO_NO_PULL;
+        dir = 1;                /* doesn't matter since it is not configured as
+                                   GPIO */
+        drv = GPIO_16MA;
+    } else {
+        /* As discussed in the MSM8660 FFA HW SW Control Doc configure these
+           GPIO as input and pull down. */
+        func = 0;               /* GPIO */
+        pull = GPIO_PULL_DOWN;
+        dir = 0;                /* Input */
+        drv = 0;                /* does not matter configured as input */
+    }
+
+    gpio_tlmm_config(0, func, dir, pull, drv, enable);  /* lcdc_pclk */
+    gpio_tlmm_config(1, func, dir, pull, drv, enable);  /* lcdc_hsync */
+    gpio_tlmm_config(2, func, dir, pull, drv, enable);  /* lcdc_vsync */
+    gpio_tlmm_config(3, func, dir, pull, drv, enable);  /* lcdc_den */
+    gpio_tlmm_config(4, func, dir, pull, drv, enable);  /* lcdc_red7 */
+    gpio_tlmm_config(5, func, dir, pull, drv, enable);  /* lcdc_red6 */
+    gpio_tlmm_config(6, func, dir, pull, drv, enable);  /* lcdc_red5 */
+    gpio_tlmm_config(7, func, dir, pull, drv, enable);  /* lcdc_red4 */
+    gpio_tlmm_config(8, func, dir, pull, drv, enable);  /* lcdc_red3 */
+    gpio_tlmm_config(9, func, dir, pull, drv, enable);  /* lcdc_red2 */
+    gpio_tlmm_config(10, func, dir, pull, drv, enable); /* lcdc_red1 */
+    gpio_tlmm_config(11, func, dir, pull, drv, enable); /* lcdc_red0 */
+    gpio_tlmm_config(12, func, dir, pull, drv, enable); /* lcdc_rgn7 */
+    gpio_tlmm_config(13, func, dir, pull, drv, enable); /* lcdc_rgn6 */
+    gpio_tlmm_config(14, func, dir, pull, drv, enable); /* lcdc_rgn5 */
+    gpio_tlmm_config(15, func, dir, pull, drv, enable); /* lcdc_rgn4 */
+    gpio_tlmm_config(16, func, dir, pull, drv, enable); /* lcdc_rgn3 */
+    gpio_tlmm_config(17, func, dir, pull, drv, enable); /* lcdc_rgn2 */
+    gpio_tlmm_config(18, func, dir, pull, drv, enable); /* lcdc_rgn1 */
+    gpio_tlmm_config(19, func, dir, pull, drv, enable); /* lcdc_rgn0 */
+    gpio_tlmm_config(20, func, dir, pull, drv, enable); /* lcdc_blu7 */
+    gpio_tlmm_config(21, func, dir, pull, drv, enable); /* lcdc_blu6 */
+    gpio_tlmm_config(22, func, dir, pull, drv, enable); /* lcdc_blu5 */
+    gpio_tlmm_config(23, func, dir, pull, drv, enable); /* lcdc_blu4 */
+    gpio_tlmm_config(24, func, dir, pull, drv, enable); /* lcdc_blu3 */
+    gpio_tlmm_config(25, func, dir, pull, drv, enable); /* lcdc_blu2 */
+    gpio_tlmm_config(26, func, dir, pull, drv, enable); /* lcdc_blu1 */
+    gpio_tlmm_config(27, func, dir, pull, drv, enable); /* lcdc_blu0 */
+}
+
+/* Backlight duty cycle init is used to configure the PMIC8058 for
+ * PWM output and drive those pins.
+ */
+static void bl_duty_cycle_init(void)
+{
+    /* Disable backlight LPG channels before configuring them and dedicated
+       PMIC GPIOs */
+    pm8058_write_one(0x00, LPG_BANK_ENABLE);
+
+    /* Configure PM8058 GPIO24 as a PWM driver (LPG ch0) for chain 1 of 6 LEDs */
+    pm8058_write_one(0x81, GPIO24_GPIO_CNTRL);  /* Write, Bank0, VIN0, Mode
+                                                   selection enabled */
+    pm8058_write_one(0x98, GPIO24_GPIO_CNTRL);  /* Write, Bank1, OutOn/InOff,
+                                                   CMOS, Don't Invert Output */
+    pm8058_write_one(0xAA, GPIO24_GPIO_CNTRL);  /* Write, Bank2, GPIO no pull */
+    pm8058_write_one(0xB4, GPIO24_GPIO_CNTRL);  /* Write, Bank3, high drv
+                                                   strength */
+    pm8058_write_one(0xC6, GPIO24_GPIO_CNTRL);  /* Write, Bank4, Src: LPG_DRV1
+                                                   (Spec. Fnc 2) */
+    pm8058_write_one(0xD8, GPIO24_GPIO_CNTRL);  /* Write, Bank5, Interrupt
+                                                   polarity noninversion */
+
+    /* Configure PM8058 GPIO25 as a PWM driver (LPG ch1) for chain 2 of 5 LEDs */
+    pm8058_write_one(0x81, GPIO25_GPIO_CNTRL);  /* Write, Bank0, VIN0, Mode
+                                                   selection enabled */
+    pm8058_write_one(0x98, GPIO25_GPIO_CNTRL);  /* Write, Bank1, OutOn/InOff,
+                                                   CMOS, Don't Invert Output */
+    pm8058_write_one(0xAA, GPIO25_GPIO_CNTRL);  /* Write, Bank2, GPIO no pull */
+    pm8058_write_one(0xB4, GPIO25_GPIO_CNTRL);  /* Write, Bank3, high drv
+                                                   strength */
+    pm8058_write_one(0xC6, GPIO25_GPIO_CNTRL);  /* Write, Bank4, Src: LPG_DRV2
+                                                   (Spec. Fnc 2) */
+    pm8058_write_one(0xD8, GPIO25_GPIO_CNTRL);  /* Write, Bank5, Interrupt
+                                                   polarity noninversion */
+
+    /* Configure PM8058 LPG channel 0 as non-LUT PWM for PM8058 GPIO24 */
+    pm8058_write_one(0x0, LPG_BANK_SEL);    /* Select LPG ch0 slice of control
+                                               regs */
+    pm8058_write_one(0x00, LPG_CTL_0);  /* Disable PWM, PWM output, and LPG
+                                           ramp generator */
+    pm8058_write_one(0x40, LPG_CTL_1);  /* Dont Toggle, Enable user PWM value,
+                                           no LUT high value idx */
+    pm8058_write_one(0x00, LPG_CTL_2);  /* Dont Loop, no LUT low value index */
+    pm8058_write_one(0xDE, LPG_CTL_3);  /* LS 8 bits of 9-bit PWM user value */
+    pm8058_write_one(0x7F, LPG_CTL_4);  /* MSbit of 9-bit PWM user value,
+                                           19.2MHz, Dev 6, Expo M = 7 */
+    pm8058_write_one(0x01, LPG_CTL_5);  /* PWM = 9bit, disable pause at high
+                                           value LUT index */
+    pm8058_write_one(0x00, LPG_CTL_6);  /* Disable pause at low value LUT index
+                                         */
+    pm8058_write_one(0x0C, LPG_CTL_0);  /* Enable PWM and PWM output, LPG ramp
+                                           generator remains disabled */
+
+    /* Configure PM8058 LPG chan 1 as PWM for PM8058 GPIO25 */
+    pm8058_write_one(0x1, LPG_BANK_SEL);    /* Select LPG ch1 slice of control
+                                               regs */
+    pm8058_write_one(0x00, LPG_CTL_0);  /* Disable PWM, PWM output, and LPG
+                                           ramp generator */
+    pm8058_write_one(0x40, LPG_CTL_1);  /* Dont Toggle, Enable user PWM value,
+                                           no LUT high value idx */
+    pm8058_write_one(0x00, LPG_CTL_2);  /* Dont Loop, no LUT low value index */
+    pm8058_write_one(0x00, LPG_CTL_3);  /* LS 8 bits of 9-bit PWM user value */
+    pm8058_write_one(0x7F, LPG_CTL_4);  /* MSbit of 9-bit PWM user value,
+                                           19.2MHz, Dev 6, Expo M = 7 */
+    pm8058_write_one(0x01, LPG_CTL_5);  /* PWM = 9bit, disable pause at high
+                                           value LUT index */
+    pm8058_write_one(0x00, LPG_CTL_6);  /* Disable pause at low value LUT index
+                                         */
+    pm8058_write_one(0x0C, LPG_CTL_0);  /* Enable PWM and PWM output, LPG ramp
+                                           generator remains disabled */
+
+    /* Enable both LPG channels to enable backlight driver */
+    pm8058_write_one(0x03, LPG_BANK_ENABLE);    /* Enable LPG ch0 (GPIO24) &
+                                                   ch1 (GPIO25) */
+}
+
+void board_lcd_enable(void)
+{
+    dev = qup_i2c_init(GSBI8_BASE, 100000, 24000000);
+
+    /* Make sure dev is created and initialized properly */
+    if (!dev) {
+        while (1) ;
+        return;
+    }
+
+    /* Store current value of these registers as to not destroy their previous
+       state. */
+    uint8_t open_drain_a = expander_read(GPIO_EXPANDER_REG_OPEN_DRAIN_A);
+    uint8_t dir_b = expander_read(GPIO_EXPANDER_REG_DIR_B);
+    uint8_t dir_a = expander_read(GPIO_EXPANDER_REG_DIR_A);
+    uint8_t data_b = expander_read(GPIO_EXPANDER_REG_DATA_B);
+    uint8_t data_a = expander_read(GPIO_EXPANDER_REG_DATA_A);
+
+    /* Set the LVDS_SHUTDOWN_N to open drain and output low. */
+    dprintf(INFO, "Enable lvds_shutdown_n line for Open Drain.\n");
+    expander_write(GPIO_EXPANDER_REG_OPEN_DRAIN_A, 0x04 | open_drain_a);
+
+    dprintf(INFO, "Enable lvds_shutdown_n line for output.\n");
+    expander_write(GPIO_EXPANDER_REG_DIR_A, ~0x04 & dir_a);
+
+    dprintf(INFO, "Drive the LVDS_SHUTDOWN_N pin high here.\n");
+    expander_write(GPIO_EXPANDER_REG_DATA_A, 0x04 | data_a);
+
+    /* Turn on the VREG_L2B to 3.3V. */
+
+    /* Power on the appropiate PMIC LDO power rails */
+    if (lcd_power_on())
+        return;
+
+    /* Enable the GPIO as LCDC mode LCD. */
+    lcd_gpio_cfg(1);
+
+    /* Arbitrary delay */
+    udelay(20000);
+
+    /* Set the backlight duty cycle via the PM8058 LPG_DRV1 and LPG_DRV2 */
+    bl_duty_cycle_init();
+
+    dprintf(INFO, "Enable BACKLIGHT_EN line for output.\n");
+    expander_write(GPIO_EXPANDER_REG_DIR_B, ~0x10 & dir_b);
+
+    dprintf(INFO, "Drive BACKLIGHT_EN to high\n");
+    expander_write(GPIO_EXPANDER_REG_DATA_B, 0x10 | data_b);
+
+}
+
+void mdp_clock_init(void)
+{
+    /* Set the MDP_AXI_CLK to 165MHz, use MX0 for now */
+    config_mdp_axi_clk(0);
+
+    /* Turn on the PLL2, to ramp up the MDP clock to max (200MHz) */
+    nt_pll_enable(PLL_2, 1);
+
+    config_mdp_clk(MDP_NS_VAL, MDP_MD_VAL,
+                   MDP_CC_VAL, MDP_NS_REG, MDP_MD_REG, MDP_CC_REG);
+
+    config_pixel_clk(PIXEL_NS_VAL, PIXEL_MD_VAL,
+                     PIXEL_CC_VAL, LCD_PIXEL_NS_REG,
+                     LCD_PIXEL_MD_REG, LCD_PIXEL_CC_REG);
+}
+
+void lcdc_on(void)
+{
+    board_lcd_enable();
+}
diff --git a/platform/msm8x60/platform.c b/platform/msm8x60/platform.c
index 28217de..9623664 100755
--- a/platform/msm8x60/platform.c
+++ b/platform/msm8x60/platform.c
@@ -80,6 +80,13 @@
 
 void display_init(void)
 {
+    struct fbcon_config *fb_cfg;
+#if DISPLAY_TYPE_LCDC
+    mdp_clock_init();
+    fb_cfg = lcdc_init();
+    panel_poweron();
+    fbcon_setup(fb_cfg);
+#endif
 }
 
 void secondary_core(unsigned sec_entry)
diff --git a/platform/msm8x60/pmic.c b/platform/msm8x60/pmic.c
new file mode 100755
index 0000000..24c044e
--- /dev/null
+++ b/platform/msm8x60/pmic.c
@@ -0,0 +1,101 @@
+/*
+ * * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ *  * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <platform/pmic.h>
+
+typedef int (*pm8058_write_func) (unsigned char *, unsigned short,
+                                  unsigned short);
+extern int pa1_ssbi2_write_bytes(unsigned char *buffer, unsigned short length,
+                                 unsigned short slave_addr);
+
+/*PM8058*/
+void pm8058_write_one(unsigned data, unsigned address)
+{
+    pm8058_write_func wr_function = &pa1_ssbi2_write_bytes;
+    if (wr_function == NULL)
+        return;
+    if ((*wr_function) (&data, 1, address))
+        dprintf(CRITICAL, "Error in initializing register\n");
+
+}
+
+/*PM8901*/
+extern int pa2_ssbi2_write_bytes(unsigned char *buffer, unsigned short length,
+                                 unsigned short slave_addr);
+extern int pa2_ssbi2_read_bytes(unsigned char *buffer, unsigned short length,
+                                unsigned short slave_addr);
+/*
+ * Write to the control registers on PMIC via the SSBI2 interface.
+ * Returns : (0) on success and (-1) on error.
+ */
+int pm8901_write(uint8_t * buffer, uint32_t length, uint32_t slave_addr)
+{
+    return pa2_ssbi2_write_bytes(buffer, length, slave_addr);
+}
+
+/*
+ * Read from the control registers on PMIC via the SSBI2 interface.
+ * Returns : (0) on success and (-1) on error.
+ */
+int pm8901_read(uint8_t * buffer, uint32_t length, uint32_t slave_addr)
+{
+    return pa2_ssbi2_read_bytes(buffer, length, slave_addr);
+}
+
+/*
+ * PMIC 8901 LDO vreg read.
+ */
+int pm8901_test_bank_read(uint8_t * buffer, uint8_t bank, uint16_t addr)
+{
+    int ret = pm8901_write(&bank, 1, addr);
+    /* if the write does not work we can't read. */
+    if (ret) {
+        return ret;
+    }
+
+    return pm8901_read(buffer, 1, addr);
+}
+
+/*
+ * PMIC 8901 LDO vreg write.
+ */
+int pm8901_vreg_write(uint8_t * buffer, uint8_t mask, uint16_t addr,
+                      uint8_t prev_val)
+{
+    uint8_t reg;
+
+    /* Clear the bits we want to try and set. */
+    reg = (prev_val & ~mask);
+    /* Set the bits we want to set, before writing them to addr */
+    reg |= (*buffer & mask);
+    return pm8901_write(&reg, 1, addr);
+}
diff --git a/platform/msm8x60/rules.mk b/platform/msm8x60/rules.mk
index a732f16..e69b266 100755
--- a/platform/msm8x60/rules.mk
+++ b/platform/msm8x60/rules.mk
@@ -8,7 +8,7 @@
 MMC_SLOT         := 1
 
 DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
-	   MMC_SLOT=$(MMC_SLOT)
+	   MMC_SLOT=$(MMC_SLOT) MDP4=1
 
 INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
 
@@ -20,7 +20,9 @@
 	$(LOCAL_DIR)/interrupts.o \
 	$(LOCAL_DIR)/acpuclock.o \
 	$(LOCAL_DIR)/mmc_init.o \
-	$(LOCAL_DIR)/gpio.o
+	$(LOCAL_DIR)/gpio.o \
+	$(LOCAL_DIR)/panel.o \
+	$(LOCAL_DIR)/pmic.o
 
 LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
 
diff --git a/platform/msm_shared/lcdc.c b/platform/msm_shared/lcdc.c
index 75dfe0c..725804d 100755
--- a/platform/msm_shared/lcdc.c
+++ b/platform/msm_shared/lcdc.c
@@ -35,9 +35,13 @@
 #include <dev/fbcon.h>
 #include <target/display.h>
 
-#if MDP4
+#if PLATFORM_MSM7X30
 #define MSM_MDP_BASE1 0xA3F00000
 #define LCDC_BASE     0xC0000
+#elif PLATFORM_MSM8X60
+#define MSM_MDP_BASE1 0x05100000
+#define LCDC_BASE     0xC0000
+#define LCDC_FB_ADDR  0x43E00000
 #else
 #define MSM_MDP_BASE1 0xAA200000
 #define LCDC_BASE     0xE0000
@@ -90,9 +94,12 @@
 struct fbcon_config *lcdc_init(void)
 {
 	dprintf(INFO, "lcdc_init(): panel is %d x %d\n", fb_cfg.width, fb_cfg.height);
-
+#if PLATFORM_MSM8X60
+	fb_cfg.base = LCDC_FB_ADDR;
+#else
 	fb_cfg.base =
 		memalign(4096, fb_cfg.width * fb_cfg.height * (fb_cfg.bpp / 8));
+#endif
 
 	writel((unsigned) fb_cfg.base, MSM_MDP_BASE1 + 0x90008);
 
diff --git a/target/msm8660_surf/include/target/display.h b/target/msm8660_surf/include/target/display.h
index 951fd5f..805bf48 100644
--- a/target/msm8660_surf/include/target/display.h
+++ b/target/msm8660_surf/include/target/display.h
@@ -29,19 +29,19 @@
 #ifndef _TARGET_QSD8660_SURF_DISPLAY_H
 #define _TARGET_QSD8660_SURF_DISPLAY_H
 
-#define TARGET_XRES 800
-#define TARGET_YRES 480
+#define TARGET_XRES 1024
+#define TARGET_YRES 600
 
-#define LCDC_FB_WIDTH     800
-#define LCDC_FB_HEIGHT    480
+#define LCDC_FB_WIDTH     1024
+#define LCDC_FB_HEIGHT    600
 
-#define LCDC_HSYNC_PULSE_WIDTH_DCLK 60
-#define LCDC_HSYNC_BACK_PORCH_DCLK  81
-#define LCDC_HSYNC_FRONT_PORCH_DCLK 81
+#define LCDC_HSYNC_PULSE_WIDTH_DCLK 32
+#define LCDC_HSYNC_BACK_PORCH_DCLK  80
+#define LCDC_HSYNC_FRONT_PORCH_DCLK 48
 #define LCDC_HSYNC_SKEW_DCLK        0
 
-#define LCDC_VSYNC_PULSE_WIDTH_LINES 2
-#define LCDC_VSYNC_BACK_PORCH_LINES  20
-#define LCDC_VSYNC_FRONT_PORCH_LINES 27
+#define LCDC_VSYNC_PULSE_WIDTH_LINES 1
+#define LCDC_VSYNC_BACK_PORCH_LINES  4
+#define LCDC_VSYNC_FRONT_PORCH_LINES 3
 
 #endif
diff --git a/target/msm8660_surf/rules.mk b/target/msm8660_surf/rules.mk
index a871d8a..83e4386 100755
--- a/target/msm8660_surf/rules.mk
+++ b/target/msm8660_surf/rules.mk
@@ -16,7 +16,8 @@
 
 KEYS_USE_GPIO_KEYPAD := 1
 
-DEFINES += DISPLAY_TYPE_MDDI=1
+DEFINES += DISPLAY_SPLASH_SCREEN=1
+DEFINES += DISPLAY_TYPE_LCDC=1
 
 MODULES += \
 	dev/keys \