[msm8x60]: Enable LCDC display for SURF and FFA devices
Enable LCDC display for MSM8660 SURF and FFA devices.
Change-Id: I74099c7fb8a06bb40d6663066588698ed69cfee0
diff --git a/platform/msm8x60/acpuclock.c b/platform/msm8x60/acpuclock.c
index 4e5695d..402f844 100755
--- a/platform/msm8x60/acpuclock.c
+++ b/platform/msm8x60/acpuclock.c
@@ -30,8 +30,183 @@
#include <debug.h>
#include <kernel/thread.h>
#include <platform/iomap.h>
+#include <platform/clock.h>
#include <reg.h>
+/* Read, modify, then write-back a register. */
+static void rmwreg(uint32_t val, uint32_t reg, uint32_t mask)
+{
+ uint32_t regval = readl(reg);
+ regval &= ~mask;
+ regval |= val;
+ writel(regval, reg);
+}
+
+
+void config_mdp_axi_clk(uint8_t use_pxo){
+ /* Program MM_PLL0 (PLL1) @ 1320 MHz and turn it on. */
+ rmwreg(0, MM_PLL0_MODE_REG, (1<<0)); /* Disable output */
+ writel(48, MM_PLL0_L_VAL_REG);
+ writel(8, MM_PLL0_M_VAL_REG);
+ writel(9, MM_PLL0_N_VAL_REG);
+ /* Set ref, enable. */
+ if (use_pxo)
+ rmwreg((1<<1), MM_PLL0_MODE_REG, (1<<4)|(1<<1)); /* PXO */
+ else
+ rmwreg((1<<4)|(1<<1), MM_PLL0_MODE_REG, (1<<4)|(1<<1)); /* MXO */
+ udelay(10);
+ writel(0x14580, MM_PLL0_CONFIG_REG); /* Enable MN, set VCO, misc */
+ rmwreg((1<<2), MM_PLL0_MODE_REG, (1<<2)); /* Deassert reset */
+ rmwreg((1<<0), MM_PLL0_MODE_REG, (1<<0)); /* Enable output */
+
+ /* Set up MM AHB clock to PLL8/5. */
+ //local_src_enable(PLL_8);
+ rmwreg(0x0102, AHB_NS_REG, 0x43C7);
+ udelay(200); /* Wait before using registers clocked by MM AHB_CLK. */
+
+ /* Set up MM Fabric (AXI). */
+ writel(0x4248451, AXI_NS_REG);
+}
+
+
+/* Enable/disable for non-shared NT PLLs. */
+int nt_pll_enable(uint8_t src, uint8_t enable)
+{
+ static const struct {
+ uint32_t const mode_reg;
+ uint32_t const status_reg;
+ } pll_reg[] = {
+ [PLL_1] = { MM_PLL0_MODE_REG, MM_PLL0_STATUS_REG },
+ [PLL_2] = { MM_PLL1_MODE_REG, MM_PLL1_STATUS_REG },
+ [PLL_3] = { MM_PLL2_MODE_REG, MM_PLL2_STATUS_REG },
+ };
+ uint32_t pll_mode;
+
+ pll_mode = readl(pll_reg[src].mode_reg);
+ if (enable) {
+ /* Disable PLL bypass mode. */
+ pll_mode |= (1<<1);
+ writel( pll_mode, pll_reg[src].mode_reg);
+
+ /* H/W requires a 5us delay between disabling the bypass and
+ * de-asserting the reset. Delay 10us just to be safe. */
+ udelay(10);
+
+ /* De-assert active-low PLL reset. */
+ pll_mode |= (1<<2);
+ writel( pll_mode, pll_reg[src].mode_reg);
+
+ /* Enable PLL output. */
+ pll_mode |= (1<<0);
+ writel( pll_mode, pll_reg[src].mode_reg);
+
+ /* Wait until PLL is enabled. */
+ while (!readl(pll_reg[src].status_reg));
+ } else {
+ /* Disable the PLL output, disable test mode, enable
+ * the bypass mode, and assert the reset. */
+ pll_mode &= 0xFFFFFFF0;
+ writel( pll_mode, pll_reg[src].mode_reg);
+ }
+
+ return 0;
+}
+
+
+/* Write the M,N,D values and enable the MDP Core Clock */
+void config_mdp_clk( uint32_t ns,
+ uint32_t md,
+ uint32_t cc,
+ uint32_t ns_addr,
+ uint32_t md_addr,
+ uint32_t cc_addr)
+{
+ int val = 0;
+
+ /* MN counter reset */
+ val = 1 << 31;
+ writel(val, ns_addr);
+
+ /* Write the MD and CC register values */
+ writel(md, md_addr);
+ writel(cc, cc_addr);
+
+ /* Reset the clk control, and Write ns val */
+ val = 1 << 31;
+ val |= ns;
+ writel(val, ns_addr);
+
+ /* Clear MN counter reset */
+ val = 1 << 31;
+ val = ~val;
+ val = val & readl(ns_addr);
+ writel(val, ns_addr);
+
+ /* Enable MND counter */
+ val = 1 << 8;
+ val = val | readl(cc_addr);
+ writel(val, cc_addr);
+
+ /* Enable the root of the clock tree */
+ val = 1 << 2;
+ val = val | readl(cc_addr);
+ writel(val, cc_addr);
+
+ /* Enable the MDP Clock */
+ val = 1 << 0;
+ val = val | readl(cc_addr);
+ writel(val, cc_addr);
+}
+
+/* Write the M,N,D values and enable the Pixel Core Clock */
+void config_pixel_clk( uint32_t ns,
+ uint32_t md,
+ uint32_t cc,
+ uint32_t ns_addr,
+ uint32_t md_addr,
+ uint32_t cc_addr){
+ unsigned int val = 0;
+
+ /* Activate the reset for the M/N Counter */
+ val = 1 << 7;
+ writel(val, ns_addr);
+
+ /* Write the MD and CC register values */
+ writel(md, md_addr);
+ writel(cc, cc_addr);
+
+ /* Write the ns value, and active reset for M/N Counter, again */
+ val = 1 << 7;
+ val |= ns;
+ writel(val, ns_addr);
+
+ /* De-activate the reset for M/N Counter */
+ val = 1 << 7;
+ val = ~val;
+ val = val & readl(ns_addr);
+ writel(val, ns_addr);
+
+ /* Enable MND counter */
+ val = 1 << 5;
+ val = val | readl(cc_addr);
+ writel(val, cc_addr);
+
+ /* Enable the root of the clock tree */
+ val = 1 << 2;
+ val = val | readl(cc_addr);
+ writel(val, cc_addr);
+
+ /* Enable the MDP Clock */
+ val = 1 << 0;
+ val = val | readl(cc_addr);
+ writel(val, cc_addr);
+
+ /* Enable the LCDC Clock */
+ val = 1 << 8;
+ val = val | readl(cc_addr);
+ writel(val, cc_addr);
+}
+
/* Set rate and enable the clock */
void clock_config(uint32_t ns,
uint32_t md,