diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index 2e3d475..adeca41 100644
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -345,18 +345,15 @@
 {
 	int cmdline_length = 0;
 	int n;
-	unsigned char *cmdline_final = NULL;
 	char *dest;
 
-	cmdline_final = update_cmdline(cmdline);
-
-	cmdline_length =strlen((const char*)cmdline_final);
+	cmdline_length = strlen((const char*)cmdline);
 	n = (cmdline_length + 4) & (~3);
 
 	*ptr++ = (n / 4) + 2;
 	*ptr++ = 0x54410009;
 	dest = (char *) ptr;
-	while ((*dest++ = *cmdline_final++));
+	while ((*dest++ = *cmdline++));
 	ptr += (n / 4);
 
 	return ptr;
@@ -393,6 +390,7 @@
 		const char *cmdline, unsigned machtype,
 		void *ramdisk, unsigned ramdisk_size)
 {
+	unsigned char *final_cmdline;
 #if DEVICE_TREE
 	int ret = 0;
 #endif
@@ -402,11 +400,13 @@
 
 	ramdisk = PA(ramdisk);
 
+	final_cmdline = update_cmdline((const char*)cmdline);
+
 #if DEVICE_TREE
 	dprintf(INFO, "Updating device tree: start\n");
 
 	/* Update the Device Tree */
-	ret = update_device_tree((void *)tags, cmdline, ramdisk, ramdisk_size);
+	ret = update_device_tree((void *)tags, final_cmdline, ramdisk, ramdisk_size);
 	if(ret)
 	{
 		dprintf(CRITICAL, "ERROR: Updating Device Tree Failed \n");
@@ -416,7 +416,7 @@
 	dprintf(INFO, "Updating device tree: done\n");
 #else
 	/* Generating the Atags */
-	generate_atags(tags, cmdline, ramdisk, ramdisk_size);
+	generate_atags(tags, final_cmdline, ramdisk, ramdisk_size);
 #endif
 
 	dprintf(INFO, "booting linux @ %p, ramdisk @ %p (%d)\n",
diff --git a/arch/arm/cache-ops.S b/arch/arm/cache-ops.S
index f89a60c..974fb9b 100644
--- a/arch/arm/cache-ops.S
+++ b/arch/arm/cache-ops.S
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2008 Travis Geiselbrecht
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining
  * a copy of this software and associated documentation files
@@ -134,7 +135,11 @@
 	beq		.Ldcache_already_disabled
 
 	bic		r0, #(1<<2)
+	// make sure all data operations are completed
+	dsb
 	mcr		p15, 0, r0, c1, c0, 0		// disable dcache
+	// make sure previous instruction finishes before we clean and flush
+	isb
 
 	// flush and invalidate the dcache
 	// NOTE: trashes a bunch of registers, can't be spilling stuff to the stack
@@ -163,11 +168,15 @@
 	mrc     p15, 0, r0, c1, c0, 0		// cr1
 	bic		r0, #(1<<12)
 	mcr		p15, 0, r0, c1, c0, 0		// disable icache
+	// make sure previous instruction finishes
+	isb
 
 .Ldone_disable:
 	// make sure the icache is always invalidated
 	mov		r0, #0
 	mcr		p15, 0, r0, c7, c5, 0		// invalidate icache to PoU
+	// make sure that data is in sync
+	dsb
 
 	msr		cpsr, r12
 	ldmfd	sp!, {r4-r11, pc}
@@ -220,6 +229,7 @@
 
 // flush & invalidate cache routine, trashes r0-r6, r9-r11
 flush_invalidate_cache_v7:
+	DMB
 	/* from ARMv7 manual, B2-17 */
 	MRC 	p15, 1, R0, c0, c0, 1 		// Read CLIDR 
 	ANDS 	R3, R0, #0x7000000 
@@ -260,6 +270,7 @@
 .Lfinished:
 	mov		r10, #0
 	mcr		p15, 2, r10, c0, c0, 0		// select cache level 0
+	dsb
 	.word	0xf57ff06f	// isb
 
 	bx		lr
@@ -306,6 +317,7 @@
 .Lfinished_invalidate:
 	mov		r10, #0
 	mcr		p15, 2, r10, c0, c0, 0		// select cache level 0
+	dsb
 	.word	0xf57ff06f	// isb
 
 	bx		lr
diff --git a/dev/panel/msm/mipi_toshiba_video_720p.c b/dev/panel/msm/mipi_toshiba_video_720p.c
new file mode 100644
index 0000000..2e02edd
--- /dev/null
+++ b/dev/panel/msm/mipi_toshiba_video_720p.c
@@ -0,0 +1,174 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <stdint.h>
+#include <msm_panel.h>
+#include <mipi_dsi.h>
+#include <sys/types.h>
+#include <err.h>
+#include <reg.h>
+#include <mdp4.h>
+
+int mipi_toshiba_video_720p_config(void *pdata)
+{
+	int ret = NO_ERROR;
+
+	/* 3 Lanes -- Enables Data Lane0, 1, 2 */
+	uint8_t lane_en = 0xf;
+	uint64_t low_pwr_stop_mode = 0;
+
+	/* Needed or else will have blank line at top of display */
+	uint8_t eof_bllp_pwr = 0x8;
+
+	uint8_t interleav = 0;
+	struct lcdc_panel_info *lcdc = NULL;
+	struct msm_panel_info *pinfo = (struct msm_panel_info *)pdata;
+
+	if (pinfo == NULL)
+		return ERR_INVALID_ARGS;
+
+	lcdc =  &(pinfo->lcdc);
+	if (lcdc == NULL)
+		return ERR_INVALID_ARGS;
+
+	ret = mipi_dsi_video_mode_config((pinfo->xres + lcdc->xres_pad),
+			(pinfo->yres + lcdc->yres_pad),
+			(pinfo->xres),
+			(pinfo->yres),
+			(lcdc->h_front_porch),
+			(lcdc->h_back_porch + lcdc->h_pulse_width),
+			(lcdc->v_front_porch),
+			(lcdc->v_back_porch + lcdc->v_pulse_width),
+			(lcdc->h_pulse_width),
+			(lcdc->v_pulse_width),
+			pinfo->mipi.dst_format,
+			pinfo->mipi.traffic_mode,
+			lane_en,
+			low_pwr_stop_mode,
+			eof_bllp_pwr,
+			interleav);
+	return ret;
+}
+
+int mipi_toshiba_video_720p_on()
+{
+	int ret = NO_ERROR;
+	return ret;
+}
+
+int mipi_toshiba_video_720p_off()
+{
+	int ret = NO_ERROR;
+	return ret;
+}
+
+static struct mdss_dsi_phy_ctrl dsi_video_mode_phy_db = {
+	/* 720x1280, RGB888, 4 Lane 60 fps video mode */
+	/* regulator */
+	{0x03, 0x01, 0x01, 0x00, 0x20, 0x00, 0x01},
+	/* timing */
+	{0x69, 0x29, 0x1f, 0x00, 0x55, 0x55, 0x19, 0x2a,
+		0x2a, 0x03, 0x04, 0x00},
+	/* phy ctrl */
+	{0x5f, 0x00, 0x00, 0x10},
+	/* strength */
+	{0x77, 0x06},
+	/* bist control */
+	{0x00, 0x00, 0xb1, 0xff, 0x00, 0x00},
+	/* lanes config */
+	{0x00, 0xc2, 0x45, 0x00, 0x00, 0x00, 0x00, 0x01, 0x75,
+	 0x00, 0xc2, 0x45, 0x00, 0x00, 0x00, 0x00, 0x01, 0x75,
+	 0x00, 0xc2, 0x45, 0x00, 0x00, 0x00, 0x00, 0x01, 0x75,
+	 0x00, 0xc2, 0x45, 0x00, 0x00, 0x00, 0x00, 0x01, 0x75,
+	 0x00, 0x02, 0x45, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97},
+};
+
+void mipi_toshiba_video_720p_init(struct msm_panel_info *pinfo)
+{
+	if (!pinfo)
+		return;
+
+	pinfo->xres = 720;
+	pinfo->yres = 1280;
+	/*
+	 *
+	 * Panel's Horizontal input timing requirement is to
+	 * include dummy(pad) data of 200 clk in addition to
+	 * width and porch/sync width values
+	 */
+
+	pinfo->type = MIPI_VIDEO_PANEL;
+	pinfo->wait_cycle = 0;
+	pinfo->bpp = 24;
+	pinfo->lcdc.h_back_porch = 32;
+	pinfo->lcdc.h_front_porch = 144;
+	pinfo->lcdc.h_pulse_width = 12;
+	pinfo->lcdc.v_back_porch = 3;
+	pinfo->lcdc.v_front_porch = 9;
+	pinfo->lcdc.v_pulse_width = 4;
+	pinfo->lcdc.border_clr = 0;	/* blk */
+	pinfo->lcdc.underflow_clr = 0xff;	/* blue */
+	pinfo->lcdc.hsync_skew = 0;
+	pinfo->clk_rate = 424000000;
+
+	pinfo->mipi.mode = DSI_VIDEO_MODE;
+	pinfo->mipi.pulse_mode_hsa_he = FALSE;
+	pinfo->mipi.hfp_power_stop = FALSE;
+	pinfo->mipi.hbp_power_stop = FALSE;
+	pinfo->mipi.hsa_power_stop = FALSE;
+	pinfo->mipi.eof_bllp_power_stop = FALSE;
+	pinfo->mipi.bllp_power_stop = FALSE;
+	pinfo->mipi.traffic_mode = DSI_NON_BURST_SYNCH_EVENT;
+	pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888;
+	pinfo->mipi.vc = 0;
+	pinfo->mipi.rgb_swap = DSI_RGB_SWAP_RGB;
+	pinfo->mipi.data_lane0 = TRUE;
+	pinfo->mipi.data_lane1 = TRUE;
+	pinfo->mipi.data_lane2 = TRUE;
+	pinfo->mipi.data_lane3 = TRUE;
+	pinfo->mipi.t_clk_post = 0x04;
+	pinfo->mipi.t_clk_pre = 0x1b;
+	pinfo->mipi.stream = 0; /* dma_p */
+	pinfo->mipi.mdp_trigger = 0;
+	pinfo->mipi.dma_trigger = DSI_CMD_TRIGGER_SW;
+	pinfo->mipi.frame_rate = 60;
+	pinfo->mipi.mdss_dsi_phy_db = &dsi_video_mode_phy_db;
+	pinfo->mipi.tx_eot_append = TRUE;
+
+	pinfo->mipi.num_of_lanes = 4;
+	pinfo->mipi.panel_cmds = toshiba_mdv24_video_mode_cmds;
+	pinfo->mipi.num_of_panel_cmds =
+				 ARRAY_SIZE(toshiba_mdv24_video_mode_cmds);
+
+	pinfo->on = mipi_toshiba_video_720p_on;
+	pinfo->off = mipi_toshiba_video_720p_off;
+	pinfo->config = mipi_toshiba_video_720p_config;
+
+	return;
+}
diff --git a/dev/panel/msm/rules.mk b/dev/panel/msm/rules.mk
index 87c67a4..c2bb53f 100644
--- a/dev/panel/msm/rules.mk
+++ b/dev/panel/msm/rules.mk
@@ -20,3 +20,8 @@
 	$(LOCAL_DIR)/mipi_nt35510_cmd_wvga.o \
 	$(LOCAL_DIR)/lcdc_truly_hvga.o
 endif
+
+ifeq ($(PLATFORM),copper)
+OBJS += \
+	$(LOCAL_DIR)/mipi_toshiba_video_720p.o
+endif
\ No newline at end of file
diff --git a/dev/pmic/pm8x41/include/pm8x41.h b/dev/pmic/pm8x41/include/pm8x41.h
index 94436b1..eada6cc 100644
--- a/dev/pmic/pm8x41/include/pm8x41.h
+++ b/dev/pmic/pm8x41/include/pm8x41.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
 
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -43,8 +43,26 @@
 #define PM_GPIO_PULL_RESV_1     4
 #define PM_GPIO_PULL_RESV_2     5
 
+
+#define PM_GPIO_OUT_CMOS        0x00
+#define PM_GPIO_OUT_DRAIN_NMOS  0x01
+#define PM_GPIO_OUT_DRAIN_PMOS  0x02
+
+#define PM_GPIO_OUT_DRIVE_LOW   0x01
+#define PM_GPIO_OUT_DRIVE_MED   0x02
+#define PM_GPIO_OUT_DRIVE_HIGH  0x03
+
+
+#define PM_GPIO_FUNC_LOW        0x00
+#define PM_GPIO_FUNC_HIGH       0x01
+
+#define PM_GPIO_MODE_MASK       0x70
+#define PM_GPIO_OUTPUT_MASK     0x0F
+
 #define PON_PSHOLD_WARM_RESET   0x1
 
+#define PMIC_VERSION_V2         1
+
 struct pm8x41_gpio {
 	int direction;
 	int output_buffer;
@@ -58,12 +76,15 @@
 };
 
 int pm8x41_gpio_get(uint8_t gpio, uint8_t *status);
+int pm8x41_gpio_set(uint8_t gpio, uint8_t value);
 int pm8x41_gpio_config(uint8_t gpio, struct pm8x41_gpio *config);
 void pm8x41_set_boot_done();
-int pm8x41_vol_down_key_status();
+uint32_t pm8x41_resin_status();
+uint32_t pm8x41_resin_bark_workaround_status();
 void pm8x41_reset_configure(uint8_t);
 int pm8x41_ldo_set_voltage(const char *, uint32_t);
 int pm8x41_ldo_control(const char *, uint8_t);
+uint8_t pm8x41_get_pmic_rev();
 
 struct pm8x41_ldo {
 	const char *name;
diff --git a/dev/pmic/pm8x41/include/pm8x41_hw.h b/dev/pmic/pm8x41/include/pm8x41_hw.h
index 9cb3d43..86cfee5 100644
--- a/dev/pmic/pm8x41/include/pm8x41_hw.h
+++ b/dev/pmic/pm8x41/include/pm8x41_hw.h
@@ -35,6 +35,7 @@
 /* SMBB bit values */
 #define BOOT_DONE_BIT                         7
 
+#define REVID_REVISION4                       0x103
 
 /* GPIO Registers */
 #define GPIO_PERIPHERAL_BASE                  0xC000
@@ -69,6 +70,7 @@
 #define PON_PS_HOLD_RESET_CTL                 0x85A  /* bit 7: S2_RESET_EN, bit 0:3 : RESET_TYPE  */
 
 /* PON Peripheral register bit values */
+#define RESIN_ON_INT_BIT                      1
 #define RESIN_BARK_INT_BIT                    4
 #define S2_RESET_EN_BIT                       7
 
diff --git a/dev/pmic/pm8x41/include/pm8x41_wled.h b/dev/pmic/pm8x41/include/pm8x41_wled.h
new file mode 100644
index 0000000..74c91bc
--- /dev/null
+++ b/dev/pmic/pm8x41/include/pm8x41_wled.h
@@ -0,0 +1,69 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+ *   * Neither the name of The Linux Foundation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bits.h>
+#include <debug.h>
+#include <reg.h>
+
+#define PM_WLED_BASE                 0x1D800
+#define PM_WLED_CTNL_REG(n)          (PM_WLED_BASE + n)
+
+#define PM_WLED_LED1_BRIGHTNESS_LSB  PM_WLED_CTNL_REG(0x40)
+#define PM_WLED_LED1_BRIGHTNESS_MSB  PM_WLED_CTNL_REG(0x41)
+#define PM_WLED_LED2_BRIGHTNESS_LSB  PM_WLED_CTNL_REG(0x42)
+#define PM_WLED_LED2_BRIGHTNESS_MSB  PM_WLED_CTNL_REG(0x43)
+#define PM_WLED_LED3_BRIGHTNESS_LSB  PM_WLED_CTNL_REG(0x44)
+#define PM_WLED_LED3_BRIGHTNESS_MSB  PM_WLED_CTNL_REG(0x45)
+#define PM_WLED_ENABLE               PM_WLED_CTNL_REG(0x46)
+#define PM_WLED_ILED_SYNC_BIT        PM_WLED_CTNL_REG(0x47)
+#define PM_WLED_MODULATION_SCHEME    PM_WLED_CTNL_REG(0x4A)
+#define PM_WLED_MAX_DUTY_CYCLE       PM_WLED_CTNL_REG(0x4B)
+#define PM_WLED_CURRENT_SINK         PM_WLED_CTNL_REG(0x4F)
+
+#define PM_WLED_LED1_SINK_MASK       BIT(7)
+#define PM_WLED_LED2_SINK_MASK       BIT(6)
+#define PM_WLED_LED3_SINK_MASK       BIT(5)
+
+#define PM_WLED_LED1_ILED_SYNC_MASK  BIT(2)
+#define PM_WLED_LED2_ILED_SYNC_MASK  BIT(1)
+#define PM_WLED_LED3_ILED_SYNC_MASK  BIT(0)
+
+#define PM_WLED_ENABLE_MODULE_MASK   BIT(7)
+
+struct pm8x41_wled_data{
+	uint8_t mod_scheme;
+	uint16_t led1_brightness;
+	uint16_t led2_brightness;
+	uint16_t led3_brightness;
+	uint8_t max_duty_cycle;
+};
+
+void pm8x41_wled_config(struct pm8x41_wled_data *wled_ctrl);
+void pm8x41_wled_iled_sync_control(uint8_t enable);
+void pm8x41_wled_sink_control(uint8_t enable);
+void pm8x41_wled_enable(uint8_t enable);
diff --git a/dev/pmic/pm8x41/pm8x41.c b/dev/pmic/pm8x41/pm8x41.c
index c547a75..62014ad 100644
--- a/dev/pmic/pm8x41/pm8x41.c
+++ b/dev/pmic/pm8x41/pm8x41.c
@@ -95,9 +95,6 @@
 	uint8_t  val;
 	uint32_t gpio_base = GPIO_N_PERIPHERAL_BASE(gpio);
 
-	/* Only input configuration is implemented at this time. */
-	ASSERT(config->direction == PM_GPIO_DIR_IN);
-
 	/* Disable the GPIO */
 	val  = REG_READ(gpio_base + GPIO_EN_CTL);
 	val &= ~BIT(PERPH_EN_BIT);
@@ -115,12 +112,18 @@
 	val = config->vin_sel;
 	REG_WRITE(gpio_base + GPIO_DIG_VIN_CTL, val);
 
+	if (config->direction == PM_GPIO_DIR_OUT) {
+		/* Set the right dig out control */
+		val = config->out_strength | (config->output_buffer << 4);
+		REG_WRITE(gpio_base + GPIO_DIG_OUT_CTL, val);
+	}
+
 	/* Enable the GPIO */
 	val  = REG_READ(gpio_base + GPIO_EN_CTL);
 	val |= BIT(PERPH_EN_BIT);
 	REG_WRITE(gpio_base + GPIO_EN_CTL, val);
 
-	return 1;
+	return 0;
 }
 
 /* Reads the status of requested gpio */
@@ -135,11 +138,25 @@
 
 	dprintf(SPEW, "GPIO %d status is %d\n", gpio, *status);
 
-	return 1;
+	return 0;
 }
 
-/* Prepare PON RESIN S2 reset */
-void pm8x41_vol_down_key_prepare()
+/* Write the output value of the requested gpio */
+int pm8x41_gpio_set(uint8_t gpio, uint8_t value)
+{
+	uint32_t gpio_base = GPIO_N_PERIPHERAL_BASE(gpio);
+	uint8_t val;
+
+	/* Set the output value of the gpio */
+	val = REG_READ(gpio_base + GPIO_MODE_CTL);
+	val = (val & ~PM_GPIO_OUTPUT_MASK) | value;
+	REG_WRITE(gpio_base + GPIO_MODE_CTL, val);
+
+	return 0;
+}
+
+/* Prepare PON RESIN S2 reset (bite) */
+void pm8x41_resin_s2_reset_enable()
 {
 	uint8_t val;
 
@@ -165,8 +182,8 @@
 	REG_WRITE(PON_RESIN_N_RESET_S2_CTL, val);
 }
 
-/* Volume_Down key detect cleanup */
-void pm8x41_vol_down_key_done()
+/* Disable PON RESIN S2 reset. (bite)*/
+void pm8x41_resin_s2_reset_disable()
 {
 	/* disable s2 reset */
 	REG_WRITE(PON_RESIN_N_RESET_S2_CTL, 0x0);
@@ -175,13 +192,13 @@
 	udelay(300);
 }
 
-/* Volume_Down key status */
-int pm8x41_vol_down_key_status()
+/* Resin irq status for faulty pmic*/
+uint32_t pm8x41_resin_bark_workaround_status()
 {
 	uint8_t rt_sts = 0;
 
 	/* Enable S2 reset so we can detect the volume down key press */
-	pm8x41_vol_down_key_prepare();
+	pm8x41_resin_s2_reset_enable();
 
 	/* Delay before interrupt triggering.
 	 * See PON_DEBOUNCE_CTL reg.
@@ -193,11 +210,21 @@
 	/* Must disable S2 reset otherwise PMIC will reset if key
 	 * is held longer than S2 timer.
 	 */
-	pm8x41_vol_down_key_done();
+	pm8x41_resin_s2_reset_disable();
 
 	return (rt_sts & BIT(RESIN_BARK_INT_BIT));
 }
 
+/* Resin pin status */
+uint32_t pm8x41_resin_status()
+{
+	uint8_t rt_sts = 0;
+
+	rt_sts = REG_READ(PON_INT_RT_STS);
+
+	return (rt_sts & BIT(RESIN_ON_INT_BIT));
+}
+
 void pm8x41_reset_configure(uint8_t reset_type)
 {
 	uint8_t val;
@@ -317,3 +344,9 @@
 
 	return 0;
 }
+
+uint8_t pm8x41_get_pmic_rev()
+{
+	return REG_READ(REVID_REVISION4);
+}
+
diff --git a/dev/pmic/pm8x41/pm8x41_wled.c b/dev/pmic/pm8x41/pm8x41_wled.c
new file mode 100644
index 0000000..5693590
--- /dev/null
+++ b/dev/pmic/pm8x41/pm8x41_wled.c
@@ -0,0 +1,99 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+ *   * Neither the name of The Linux Foundation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bits.h>
+#include <reg.h>
+#include <pm8x41_hw.h>
+#include <pm8x41_wled.h>
+
+void pm8x41_wled_config(struct pm8x41_wled_data *wled_ctrl) {
+
+	if (!wled_ctrl) {
+		dprintf(CRITICAL, "Error: Invalid WLED data.\n");
+		return;
+	}
+
+	REG_WRITE(PM_WLED_MODULATION_SCHEME, wled_ctrl->mod_scheme);
+
+	REG_WRITE(PM_WLED_LED1_BRIGHTNESS_LSB, (wled_ctrl->led1_brightness & 0xFF));
+	REG_WRITE(PM_WLED_LED1_BRIGHTNESS_MSB, ((wled_ctrl->led1_brightness >> 8) & 0xFF));
+	REG_WRITE(PM_WLED_LED2_BRIGHTNESS_LSB, (wled_ctrl->led2_brightness & 0xFF));
+	REG_WRITE(PM_WLED_LED2_BRIGHTNESS_MSB, ((wled_ctrl->led2_brightness >> 8) & 0xFF));
+	REG_WRITE(PM_WLED_LED3_BRIGHTNESS_LSB, (wled_ctrl->led3_brightness & 0xFF));
+	REG_WRITE(PM_WLED_LED3_BRIGHTNESS_MSB, ((wled_ctrl->led3_brightness >> 8) & 0xFF));
+
+	REG_WRITE(PM_WLED_MAX_DUTY_CYCLE, wled_ctrl->max_duty_cycle);
+
+	dprintf(SPEW, "WLED Configuration Success.\n");
+
+}
+
+void pm8x41_wled_sink_control(uint8_t enable) {
+
+	uint8_t value = 0x0;
+
+	if (enable) {
+		value = PM_WLED_LED1_SINK_MASK |
+			PM_WLED_LED2_SINK_MASK |
+			PM_WLED_LED3_SINK_MASK;
+	}
+
+	REG_WRITE(PM_WLED_CURRENT_SINK, value);
+
+	dprintf(SPEW, "WLED Sink Success\n");
+
+}
+
+void pm8x41_wled_iled_sync_control(uint8_t enable) {
+
+	uint8_t value = 0x0;
+
+	if (enable) {
+		value = PM_WLED_LED1_ILED_SYNC_MASK |
+			PM_WLED_LED1_ILED_SYNC_MASK |
+			PM_WLED_LED1_ILED_SYNC_MASK;
+	}
+
+	REG_WRITE(PM_WLED_ILED_SYNC_BIT, value);
+
+	dprintf(SPEW, "WLED ILED Sync Success\n");
+
+}
+
+void pm8x41_wled_enable(uint8_t enable) {
+
+	uint8_t value = 0x0;
+
+	if (enable)
+		value = PM_WLED_ENABLE_MODULE_MASK;
+
+	REG_WRITE(PM_WLED_ENABLE, value);
+
+	dprintf(SPEW, "WLED Enable Success\n");
+
+}
diff --git a/dev/pmic/pm8x41/rules.mk b/dev/pmic/pm8x41/rules.mk
index af7f394..1cecf27 100644
--- a/dev/pmic/pm8x41/rules.mk
+++ b/dev/pmic/pm8x41/rules.mk
@@ -4,4 +4,5 @@
 
 OBJS += \
 	$(LOCAL_DIR)/pm8x41.o \
-	$(LOCAL_DIR)/pm8x41_adc.o
+	$(LOCAL_DIR)/pm8x41_adc.o \
+	$(LOCAL_DIR)/pm8x41_wled.o
diff --git a/platform/copper/acpuclock.c b/platform/copper/acpuclock.c
index 540a532..d1805bc 100644
--- a/platform/copper/acpuclock.c
+++ b/platform/copper/acpuclock.c
@@ -330,3 +330,99 @@
 		return;
 	}
 }
+
+void mdp_gdsc_ctrl(uint8_t enable)
+{
+	uint32_t reg = 0;
+	reg = readl(MDP_GDSCR);
+	if (enable) {
+		if (reg & 0x1)
+			writel((reg & ~0x1), MDP_GDSCR);
+
+		while(readl(MDP_GDSCR) & ((GDSC_POWER_ON_BIT) | (GDSC_POWER_ON_STATUS_BIT)));
+	} else
+		ASSERT(1);
+}
+
+/* Configure MDP clock */
+void mdp_clock_init(void)
+{
+	int ret;
+
+	/* Set MDP clock to 200MHz */
+	ret = clk_get_set_enable("mdp_ahb_clk", 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set mdp_ahb_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	ret = clk_get_set_enable("mdss_mdp_clk_src", 75000000, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set mdp_clk_src ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	ret = clk_get_set_enable("mdss_mdp_clk", 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set mdp_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	ret = clk_get_set_enable("mdss_mdp_lut_clk", 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set lut_mdp clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+}
+
+/* Initialize all clocks needed by Display */
+void mmss_clock_init(void)
+{
+	int ret;
+
+	/* Configure Byte clock */
+	writel(0x100, DSI_BYTE0_CFG_RCGR);
+	writel(0x1, DSI_BYTE0_CMD_RCGR);
+	writel(0x1, DSI_BYTE0_CBCR);
+
+	/* Configure ESC clock */
+	ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	/* Configure MMSSNOC AXI clock */
+	ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	/* Configure MMSSNOC AXI clock */
+	ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	/* Configure AXI clock */
+	ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	/* Configure Pixel clock */
+	writel(0x102, DSI_PIXEL0_CFG_RCGR);
+	writel(0x1, DSI_PIXEL0_CMD_RCGR);
+	writel(0x1, DSI_PIXEL0_CBCR);
+}
diff --git a/platform/copper/copper-clock.c b/platform/copper/copper-clock.c
index ccee342..cb7981b 100644
--- a/platform/copper/copper-clock.c
+++ b/platform/copper/copper-clock.c
@@ -39,6 +39,11 @@
 /* Mux source select values */
 #define cxo_source_val    0
 #define gpll0_source_val  1
+#define cxo_mm_source_val 0
+#define mmpll0_mm_source_val 1
+#define mmpll1_mm_source_val 2
+#define mmpll3_mm_source_val 3
+#define gpll0_mm_source_val 5
 
 struct clk_freq_tbl rcg_dummy_freq = F_END;
 
@@ -339,6 +344,136 @@
 	},
 };
 
+/* Display clocks */
+static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = {
+	F_MM(19200000,    cxo,   1,   0,   0),
+	F_END
+};
+
+static struct clk_freq_tbl ftbl_mmss_axi_clk[] = {
+	F_MM(19200000,     cxo,     1,   0,   0),
+	F_MM(100000000,  gpll0,     6,   0,   0),
+	F_END
+};
+
+static struct clk_freq_tbl ftbl_mdp_clk[] = {
+	F_MM( 75000000,  gpll0,   8,   0,   0),
+	F_END
+};
+
+static struct rcg_clk dsi_esc0_clk_src = {
+	.cmd_reg  = (uint32_t *) DSI_ESC0_CMD_RCGR,
+	.cfg_reg  = (uint32_t *) DSI_ESC0_CFG_RCGR,
+	.set_rate = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl = ftbl_mdss_esc0_1_clk,
+
+	.c        = {
+		.dbg_name = "dsi_esc0_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct rcg_clk mdp_axi_clk_src = {
+	.cmd_reg  = (uint32_t *) MDP_AXI_CMD_RCGR,
+	.cfg_reg  = (uint32_t *) MDP_AXI_CFG_RCGR,
+	.set_rate = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl = ftbl_mmss_axi_clk,
+
+	.c        = {
+		.dbg_name = "mdp_axi_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct branch_clk mdss_esc0_clk = {
+	.cbcr_reg    = (uint32_t *) DSI_ESC0_CBCR,
+	.parent      = &dsi_esc0_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mdss_esc0_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mdss_axi_clk = {
+	.cbcr_reg    = (uint32_t *) MDP_AXI_CBCR,
+	.parent      = &mdp_axi_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mdss_axi_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mmss_mmssnoc_axi_clk = {
+	.cbcr_reg    = (uint32_t *) MMSS_MMSSNOC_AXI_CBCR,
+	.parent      = &mdp_axi_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mmss_mmssnoc_axi_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mmss_s0_axi_clk = {
+	.cbcr_reg    = (uint32_t *) MMSS_S0_AXI_CBCR,
+	.parent      = &mdp_axi_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mmss_s0_axi_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mdp_ahb_clk = {
+	.cbcr_reg    = (uint32_t *) MDP_AHB_CBCR,
+	.has_sibling = 1,
+
+	.c           = {
+		.dbg_name = "mdp_ahb_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct rcg_clk mdss_mdp_clk_src = {
+	.cmd_reg      = (uint32_t *) MDP_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) MDP_CFG_RCGR,
+	.set_rate     = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl     = ftbl_mdp_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c            = {
+		.dbg_name = "mdss_mdp_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct branch_clk mdss_mdp_clk = {
+	.cbcr_reg    = (uint32_t *) MDP_CBCR,
+	.parent      = &mdss_mdp_clk_src.c,
+	.has_sibling = 1,
+
+	.c           = {
+		.dbg_name = "mdss_mdp_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mdss_mdp_lut_clk = {
+	.cbcr_reg    = MDP_LUT_CBCR,
+	.parent      = &mdss_mdp_clk_src.c,
+	.has_sibling = 1,
+
+	.c           = {
+		.dbg_name = "mdss_mdp_lut_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
 /* Clock lookup table */
 static struct clk_lookup msm_clocks_8974[] =
 {
@@ -358,6 +493,15 @@
 
 	CLK_LOOKUP("blsp2_ahb_clk",           gcc_blsp2_ahb_clk.c),
 	CLK_LOOKUP("blsp2_qup5_i2c_apps_clk", gcc_blsp2_qup5_i2c_apps_clk.c),
+
+	CLK_LOOKUP("mdp_ahb_clk",          mdp_ahb_clk.c),
+	CLK_LOOKUP("mdss_esc0_clk",        mdss_esc0_clk.c),
+	CLK_LOOKUP("mdss_axi_clk",         mdss_axi_clk.c),
+	CLK_LOOKUP("mmss_mmssnoc_axi_clk", mmss_mmssnoc_axi_clk.c),
+	CLK_LOOKUP("mmss_s0_axi_clk",      mmss_s0_axi_clk.c),
+	CLK_LOOKUP("mdss_mdp_clk_src",     mdss_mdp_clk_src.c),
+	CLK_LOOKUP("mdss_mdp_clk",         mdss_mdp_clk.c),
+	CLK_LOOKUP("mdss_mdp_lut_clk",     mdss_mdp_lut_clk.c),
 };
 
 
diff --git a/platform/copper/gpio.c b/platform/copper/gpio.c
index 53c3621..13097da 100644
--- a/platform/copper/gpio.c
+++ b/platform/copper/gpio.c
@@ -9,7 +9,7 @@
  *    copyright notice, this list of conditions and the following
  *    disclaimer in the documentation and/or other materials provided
  *    with the distribution.
- *  * Neither the name of The Linux Foundation, Inc. nor the names of its
+ *  * Neither the name of The Linux Foundation nor the names of its
  *    contributors may be used to endorse or promote products derived
  *    from this software without specific prior written permission.
  *
@@ -48,7 +48,7 @@
 
 void gpio_set(uint32_t gpio, uint32_t dir)
 {
-	writel(dir, (unsigned int *)GPIO_CONFIG_ADDR(gpio));
+	writel(dir, (unsigned int *)GPIO_IN_OUT_ADDR(gpio));
 	return;
 }
 
diff --git a/platform/copper/include/platform/clock.h b/platform/copper/include/platform/clock.h
index e2d8ac9..1bb371b 100644
--- a/platform/copper/include/platform/clock.h
+++ b/platform/copper/include/platform/clock.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -34,6 +34,35 @@
 
 #define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
 
+#define REG_MM(off)                     (MSM_MMSS_CLK_CTL_BASE + (off))
+
+#define MDP_GDSCR                       REG_MM(0x2304)
+#define GDSC_POWER_ON_BIT               BIT(31)
+#define GDSC_POWER_ON_STATUS_BIT        BIT(29)
+
+#define MDP_CMD_RCGR                    REG_MM(0x2040)
+#define MDP_CFG_RCGR                    REG_MM(0x2044)
+#define MDP_CBCR                        REG_MM(0x231C)
+#define MDP_LUT_CBCR                    REG_MM(0x2320)
+#define MDP_AHB_CBCR                    REG_MM(0x2308)
+
+#define MDP_AXI_CMD_RCGR                REG_MM(0x5040)
+#define MDP_AXI_CFG_RCGR                REG_MM(0x5044)
+
+#define MDP_AXI_CBCR                    REG_MM(0x2310)
+#define MMSS_S0_AXI_CBCR                REG_MM(0x5064)
+#define MMSS_MMSSNOC_AXI_CBCR           REG_MM(0x506C)
+
+#define DSI_BYTE0_CMD_RCGR              REG_MM(0x2120)
+#define DSI_BYTE0_CFG_RCGR              REG_MM(0x2124)
+#define DSI_BYTE0_CBCR                  REG_MM(0x233C)
+#define DSI_ESC0_CMD_RCGR               REG_MM(0x2160)
+#define DSI_ESC0_CFG_RCGR               REG_MM(0x2164)
+#define DSI_ESC0_CBCR                   REG_MM(0x2344)
+#define DSI_PIXEL0_CMD_RCGR             REG_MM(0x2000)
+#define DSI_PIXEL0_CFG_RCGR             REG_MM(0x2004)
+#define DSI_PIXEL0_CBCR                 REG_MM(0x2314)
+
 void platform_clock_init(void);
 
 void clock_init_mmc(uint32_t interface);
@@ -41,5 +70,7 @@
 void clock_config_uart_dm(uint8_t id);
 void hsusb_clock_init(void);
 void clock_config_ce(uint8_t instance);
+void mdp_clock_init(void);
+void mdp_gdsc_ctrl(uint8_t enable);
 
 #endif
diff --git a/platform/copper/include/platform/iomap.h b/platform/copper/include/platform/iomap.h
index 6235d06..a0052e1 100644
--- a/platform/copper/include/platform/iomap.h
+++ b/platform/copper/include/platform/iomap.h
@@ -144,4 +144,13 @@
                                          + (qup_id * 0x1000)) :\
                                          (PERIPH_SS_BASE + 0x00163000 + \
                                          (qup_id * 0x1000)))
+
+#define MSM_MMSS_CLK_CTL_BASE       0xFD8C0000
+
+#define MIPI_DSI_BASE               (0xFD922800)
+#define REG_DSI(off)                (MIPI_DSI_BASE + 0x04 + (off))
+
+#define MDP_BASE                    (0xfd900000)
+#define REG_MDP(off)                (MDP_BASE + (off))
+
 #endif
diff --git a/platform/copper/platform.c b/platform/copper/platform.c
index f6ef822..368b590 100644
--- a/platform/copper/platform.c
+++ b/platform/copper/platform.c
@@ -71,6 +71,10 @@
 
 void platform_uninit(void)
 {
+#if DISPLAY_SPLASH_SCREEN
+	display_shutdown();
+#endif
+
 	qtimer_uninit();
 }
 
diff --git a/platform/copper/rules.mk b/platform/copper/rules.mk
index 0941eb8..35cbe7b 100644
--- a/platform/copper/rules.mk
+++ b/platform/copper/rules.mk
@@ -14,6 +14,9 @@
 
 INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
 
+DEVS += fbcon
+MODULES += dev/fbcon
+
 OBJS += \
 	$(LOCAL_DIR)/platform.o \
 	$(LOCAL_DIR)/acpuclock.o \
diff --git a/platform/mdm9x25/include/platform/iomap.h b/platform/mdm9x25/include/platform/iomap.h
index 350cae3..a19fdd0 100644
--- a/platform/mdm9x25/include/platform/iomap.h
+++ b/platform/mdm9x25/include/platform/iomap.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -40,6 +40,9 @@
 #define MSM_SHARED_IMEM_BASE      0xFC42B000
 #define RESTART_REASON_ADDR       (MSM_SHARED_IMEM_BASE + 0x65C)
 
+#define MSM_SHARED_IMEM_BASE_V2   0xFE807800
+#define RESTART_REASON_ADDR_V2    (MSM_SHARED_IMEM_BASE_V2 + 0x65C)
+
 #define ELAN_A5SS_BASE            0xF9000000
 
 /* Peripheral subsystem */
diff --git a/platform/msm8226/acpuclock.c b/platform/msm8226/acpuclock.c
new file mode 100644
index 0000000..f1b3d41
--- /dev/null
+++ b/platform/msm8226/acpuclock.c
@@ -0,0 +1,177 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <err.h>
+#include <assert.h>
+#include <debug.h>
+#include <reg.h>
+#include <platform/timer.h>
+#include <platform/iomap.h>
+#include <mmc.h>
+#include <clock.h>
+#include <platform/clock.h>
+
+void hsusb_clock_init(void)
+{
+	int ret;
+	struct clk *iclk, *cclk;
+
+	ret = clk_get_set_enable("usb_iface_clk", 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	ret = clk_get_set_enable("usb_core_clk", 75000000, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	mdelay(20);
+
+	iclk = clk_get("usb_iface_clk");
+	cclk = clk_get("usb_core_clk");
+
+	/* Disable USB all clock init */
+	writel(0, USB_BOOT_CLOCK_CTL);
+
+	clk_disable(iclk);
+	clk_disable(cclk);
+
+	mdelay(20);
+
+	/* Start the block reset for usb */
+	writel(1, USB_HS_BCR);
+
+	mdelay(20);
+
+	/* Take usb block out of reset */
+	writel(0, USB_HS_BCR);
+
+	mdelay(20);
+
+	ret = clk_enable(iclk);
+
+	if(ret)
+    {
+        dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+        ASSERT(0);
+    }
+
+	ret = clk_enable(cclk);
+
+	if(ret)
+    {
+        dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+        ASSERT(0);
+    }
+
+}
+
+void clock_init_mmc(uint32_t interface)
+{
+	char clk_name[64];
+	int ret;
+
+	snprintf(clk_name, 64, "sdc%u_iface_clk", interface);
+
+	/* enable interface clock */
+	ret = clk_get_set_enable(clk_name, 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set sdc1_iface_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+}
+
+/* Configure MMC clock */
+void clock_config_mmc(uint32_t interface, uint32_t freq)
+{
+	int ret;
+	uint32_t reg;
+	char clk_name[64];
+
+	snprintf(clk_name, 64, "sdc%u_core_clk", interface);
+
+	if(freq == MMC_CLK_400KHZ)
+	{
+		ret = clk_get_set_enable(clk_name, 400000, 1);
+	}
+	else if(freq == MMC_CLK_50MHZ)
+	{
+		ret = clk_get_set_enable(clk_name, 50000000, 1);
+	}
+	else
+	{
+		dprintf(CRITICAL, "sdc frequency (%d) is not supported\n", freq);
+		ASSERT(0);
+	}
+
+
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set sdc1_core_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	reg = 0;
+	reg |= MMC_BOOT_MCI_CLK_ENABLE;
+	reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
+	reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
+	writel(reg, MMC_BOOT_MCI_CLK);
+
+	/* Wait for the MMC_BOOT_MCI_CLK write to go through. */
+	mmc_mclk_reg_wr_delay();
+
+	/* Wait 1 ms to provide the free running SD CLK to the card. */
+	mdelay(1);
+}
+
+/* Configure UART clock based on the UART block id*/
+void clock_config_uart_dm(uint8_t id)
+{
+	int ret;
+
+     ret = clk_get_set_enable("uart3_iface_clk", 0, 1);
+    if(ret)
+	{
+		dprintf(CRITICAL, "failed to set uart3_iface_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+    ret = clk_get_set_enable("uart3_core_clk", 7372800, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set uart3_core_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+}
+
diff --git a/platform/msm8226/gpio.c b/platform/msm8226/gpio.c
new file mode 100644
index 0000000..b869367
--- /dev/null
+++ b/platform/msm8226/gpio.c
@@ -0,0 +1,64 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <platform/gpio.h>
+
+void gpio_tlmm_config(uint32_t gpio, uint8_t func,
+                      uint8_t dir, uint8_t pull,
+                      uint8_t drvstr, uint32_t enable)
+{
+	uint32_t val = 0;
+	val |= pull;
+	val |= func << 2;
+	val |= drvstr << 6;
+	val |= enable << 9;
+	writel(val, (uint32_t *)GPIO_CONFIG_ADDR(gpio));
+	return;
+}
+
+void gpio_set(uint32_t gpio, uint32_t dir)
+{
+	writel(dir, (uint32_t *)GPIO_IN_OUT_ADDR(gpio));
+	return;
+}
+
+/* Configure gpio for blsp uart 2 */
+void gpio_config_uart_dm(uint8_t id)
+{
+	/* Configure GPIOs for BLSP1 UART3. */
+	/* configure rx gpio */
+	gpio_tlmm_config(9, 2, GPIO_INPUT, GPIO_NO_PULL,
+                         GPIO_8MA, GPIO_DISABLE);
+
+	/* configure tx gpio */
+	gpio_tlmm_config(8, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+                         GPIO_8MA, GPIO_DISABLE);
+}
diff --git a/platform/msm8226/include/platform/clock.h b/platform/msm8226/include/platform/clock.h
new file mode 100644
index 0000000..b549dd1
--- /dev/null
+++ b/platform/msm8226/include/platform/clock.h
@@ -0,0 +1,44 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MSM8226_CLOCK_H
+#define __MSM8226_CLOCK_H
+
+#include <clock.h>
+#include <clock_lib2.h>
+
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
+
+void platform_clock_init(void);
+
+void clock_init_mmc(uint32_t interface);
+void clock_config_mmc(uint32_t interface, uint32_t freq);
+void clock_config_uart_dm(uint8_t id);
+void hsusb_clock_init(void);
+
+#endif
diff --git a/platform/msm8226/include/platform/gpio.h b/platform/msm8226/include/platform/gpio.h
new file mode 100644
index 0000000..51a1ce0
--- /dev/null
+++ b/platform/msm8226/include/platform/gpio.h
@@ -0,0 +1,58 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_MSM8226_GPIO_H
+#define __PLATFORM_MSM8226_GPIO_H
+
+/* GPIO TLMM: Direction */
+#define GPIO_INPUT      0
+#define GPIO_OUTPUT     1
+
+/* GPIO TLMM: Pullup/Pulldown */
+#define GPIO_NO_PULL    0
+#define GPIO_PULL_DOWN  1
+#define GPIO_KEEPER     2
+#define GPIO_PULL_UP    3
+
+/* GPIO TLMM: Drive Strength */
+#define GPIO_2MA        0
+#define GPIO_4MA        1
+#define GPIO_6MA        2
+#define GPIO_8MA        3
+#define GPIO_10MA       4
+#define GPIO_12MA       5
+#define GPIO_14MA       6
+#define GPIO_16MA       7
+
+/* GPIO TLMM: Status */
+#define GPIO_ENABLE     0
+#define GPIO_DISABLE    1
+
+void gpio_config_uart_dm(uint8_t id);
+
+#endif
diff --git a/platform/msm8226/include/platform/iomap.h b/platform/msm8226/include/platform/iomap.h
new file mode 100644
index 0000000..7f3d1a1
--- /dev/null
+++ b/platform/msm8226/include/platform/iomap.h
@@ -0,0 +1,123 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PLATFORM_MSM8226_IOMAP_H_
+#define _PLATFORM_MSM8226_IOMAP_H_
+
+#define MSM_IOMAP_BASE              0xF9000000
+#define MSM_IOMAP_END               0xFEFFFFFF
+
+#define SDRAM_START_ADDR            0x00000000
+
+#define MSM_SHARED_BASE             0x0FA00000
+
+#define APPS_SS_BASE                0xF9000000
+
+#define MSM_GIC_DIST_BASE           APPS_SS_BASE
+#define MSM_GIC_CPU_BASE            (APPS_SS_BASE + 0x2000)
+#define APPS_APCS_QTMR_AC_BASE      (APPS_SS_BASE + 0x00020000)
+#define APPS_APCS_F0_QTMR_V1_BASE   (APPS_SS_BASE + 0x00021000)
+#define QTMR_BASE                   APPS_APCS_F0_QTMR_V1_BASE
+
+#define PERIPH_SS_BASE              0xF9800000
+
+#define MSM_SDC1_BAM_BASE           (PERIPH_SS_BASE + 0x00004000)
+#define MSM_SDC1_BASE               (PERIPH_SS_BASE + 0x00024000)
+#define MSM_SDC1_DML_BASE           (PERIPH_SS_BASE + 0x00024800)
+#define MSM_SDC3_BAM_BASE           (PERIPH_SS_BASE + 0x00044000)
+#define MSM_SDC3_BASE               (PERIPH_SS_BASE + 0x00064000)
+#define MSM_SDC3_DML_BASE           (PERIPH_SS_BASE + 0x00064800)
+#define MSM_SDC2_BAM_BASE           (PERIPH_SS_BASE + 0x00084000)
+#define MSM_SDC2_BASE               (PERIPH_SS_BASE + 0x000A4000)
+#define MSM_SDC2_DML_BASE           (PERIPH_SS_BASE + 0x000A4800)
+#define MSM_SDC4_BAM_BASE           (PERIPH_SS_BASE + 0x000C4000)
+#define MSM_SDC4_BASE               (PERIPH_SS_BASE + 0x000E4000)
+#define MSM_SDC4_DML_BASE           (PERIPH_SS_BASE + 0x000E4800)
+
+#define BLSP1_UART0_BASE            (PERIPH_SS_BASE + 0x0011D000)
+#define BLSP1_UART1_BASE            (PERIPH_SS_BASE + 0x0011E000)
+#define BLSP1_UART2_BASE            (PERIPH_SS_BASE + 0x0011F000)
+#define BLSP1_UART3_BASE            (PERIPH_SS_BASE + 0x00120000)
+#define BLSP1_UART4_BASE            (PERIPH_SS_BASE + 0x00121000)
+#define BLSP1_UART5_BASE            (PERIPH_SS_BASE + 0x00122000)
+#define MSM_USB_BASE                (PERIPH_SS_BASE + 0x00255000)
+
+#define CLK_CTL_BASE                0xFC400000
+
+#define GCC_WDOG_DEBUG              (CLK_CTL_BASE +  0x00001780)
+
+#define USB_HS_BCR                  (CLK_CTL_BASE + 0x480)
+#define USB_BOOT_CLOCK_CTL          (CLK_CTL_BASE + 0x1A00)
+
+#define SPMI_BASE                   0xFC4C0000
+#define SPMI_GENI_BASE              (SPMI_BASE + 0xA000)
+#define SPMI_PIC_BASE               (SPMI_BASE + 0xB000)
+
+#define MSM_CE1_BAM_BASE            0xFD404000
+#define MSM_CE1_BASE                0xFD41A000
+
+#define TLMM_BASE_ADDR              0xFD510000
+#define GPIO_CONFIG_ADDR(x)         (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
+#define GPIO_IN_OUT_ADDR(x)         (TLMM_BASE_ADDR + 0x1004 + (x)*0x10)
+
+#define MPM2_MPM_CTRL_BASE          0xFC4A1000
+#define MPM2_MPM_PS_HOLD            0xFC4AB000
+
+/* GPLL */
+#define GPLL0_MODE                  CLK_CTL_BASE
+#define GPLL0_STATUS                (CLK_CTL_BASE + 0x001C)
+#define APCS_GPLL_ENA_VOTE          (CLK_CTL_BASE + 0x1480)
+#define APCS_CLOCK_BRANCH_ENA_VOTE  (CLK_CTL_BASE + 0x1484)
+
+/* SDCC */
+#define SDCC1_BCR                   (CLK_CTL_BASE + 0x4C0) /* block reset */
+#define SDCC1_APPS_CBCR             (CLK_CTL_BASE + 0x4C4) /* branch control */
+#define SDCC1_AHB_CBCR              (CLK_CTL_BASE + 0x4C8)
+#define SDCC1_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x4CC)
+#define SDCC1_CMD_RCGR              (CLK_CTL_BASE + 0x4D0) /* cmd */
+#define SDCC1_CFG_RCGR              (CLK_CTL_BASE + 0x4D4) /* cfg */
+#define SDCC1_M                     (CLK_CTL_BASE + 0x4D8) /* m */
+#define SDCC1_N                     (CLK_CTL_BASE + 0x4DC) /* n */
+#define SDCC1_D                     (CLK_CTL_BASE + 0x4E0) /* d */
+
+/* UART */
+#define BLSP1_AHB_CBCR              (CLK_CTL_BASE + 0x5C4)
+#define BLSP1_UART3_APPS_CBCR       (CLK_CTL_BASE + 0x784)
+#define BLSP1_UART3_APPS_CMD_RCGR   (CLK_CTL_BASE + 0x78C)
+#define BLSP1_UART3_APPS_CFG_RCGR   (CLK_CTL_BASE + 0x790)
+#define BLSP1_UART3_APPS_M          (CLK_CTL_BASE + 0x794)
+#define BLSP1_UART3_APPS_N          (CLK_CTL_BASE + 0x798)
+#define BLSP1_UART3_APPS_D          (CLK_CTL_BASE + 0x79C)
+
+/* USB */
+#define USB_HS_SYSTEM_CBCR          (CLK_CTL_BASE + 0x484)
+#define USB_HS_AHB_CBCR             (CLK_CTL_BASE + 0x488)
+#define USB_HS_SYSTEM_CMD_RCGR      (CLK_CTL_BASE + 0x490)
+#define USB_HS_SYSTEM_CFG_RCGR      (CLK_CTL_BASE + 0x494)
+
+#endif
diff --git a/platform/msm8226/include/platform/irqs.h b/platform/msm8226/include/platform/irqs.h
new file mode 100644
index 0000000..c490a0b
--- /dev/null
+++ b/platform/msm8226/include/platform/irqs.h
@@ -0,0 +1,61 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __IRQS_MSM8226_H
+#define __IRQS_MSM8226_H
+
+/* MSM ACPU Interrupt Numbers */
+
+/* 0-15:  STI/SGI (software triggered/generated interrupts)
+ * 16-31: PPI (private peripheral interrupts)
+ * 32+:   SPI (shared peripheral interrupts)
+ */
+
+#define GIC_PPI_START                          16
+#define GIC_SPI_START                          32
+
+#define INT_QTMR_NON_SECURE_PHY_TIMER_EXP      (GIC_PPI_START + 3)
+#define INT_QTMR_VIRTUAL_TIMER_EXP             (GIC_PPI_START + 4)
+
+#define INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP      (GIC_SPI_START + 8)
+
+#define USB1_HS_BAM_IRQ                        (GIC_SPI_START + 135)
+#define USB1_HS_IRQ                            (GIC_SPI_START + 134)
+
+/* Retrofit universal macro names */
+#define INT_USB_HS                             USB1_HS_IRQ
+
+#define EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ         (GIC_SPI_START + 190)
+
+#define NR_MSM_IRQS                            256
+#define NR_GPIO_IRQS                           173
+#define NR_BOARD_IRQS                          0
+
+#define NR_IRQS                                (NR_MSM_IRQS + NR_GPIO_IRQS + \
+                                               NR_BOARD_IRQS)
+#endif	/* __IRQS_MSM8226_H */
diff --git a/platform/msm8226/msm8226-clock.c b/platform/msm8226/msm8226-clock.c
new file mode 100644
index 0000000..9f5818b
--- /dev/null
+++ b/platform/msm8226/msm8226-clock.c
@@ -0,0 +1,289 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <reg.h>
+#include <err.h>
+#include <clock.h>
+#include <clock_pll.h>
+#include <clock_lib2.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+
+
+/* Mux source select values */
+#define cxo_source_val    0
+#define gpll0_source_val  1
+#define cxo_mm_source_val 0
+#define mmpll0_mm_source_val 1
+#define mmpll1_mm_source_val 2
+#define mmpll3_mm_source_val 3
+#define gpll0_mm_source_val 5
+
+struct clk_freq_tbl rcg_dummy_freq = F_END;
+
+
+/* Clock Operations */
+static struct clk_ops clk_ops_branch =
+{
+	.enable     = clock_lib2_branch_clk_enable,
+	.disable    = clock_lib2_branch_clk_disable,
+	.set_rate   = clock_lib2_branch_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg_mnd =
+{
+	.enable     = clock_lib2_rcg_enable,
+	.set_rate   = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg =
+{
+	.enable     = clock_lib2_rcg_enable,
+	.set_rate   = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_cxo =
+{
+	.enable     = cxo_clk_enable,
+	.disable    = cxo_clk_disable,
+};
+
+static struct clk_ops clk_ops_pll_vote =
+{
+	.enable     = pll_vote_clk_enable,
+	.disable    = pll_vote_clk_disable,
+	.auto_off   = pll_vote_clk_disable,
+	.is_enabled = pll_vote_clk_is_enabled,
+};
+
+static struct clk_ops clk_ops_vote =
+{
+	.enable     = clock_lib2_vote_clk_enable,
+	.disable    = clock_lib2_vote_clk_disable,
+};
+
+/* Clock Sources */
+static struct fixed_clk cxo_clk_src =
+{
+	.c = {
+		.rate     = 19200000,
+		.dbg_name = "cxo_clk_src",
+		.ops      = &clk_ops_cxo,
+	},
+};
+
+static struct pll_vote_clk gpll0_clk_src =
+{
+	.en_reg       = (void *) APCS_GPLL_ENA_VOTE,
+	.en_mask      = BIT(0),
+	.status_reg   = (void *) GPLL0_STATUS,
+	.status_mask  = BIT(17),
+	.parent       = &cxo_clk_src.c,
+
+	.c = {
+		.rate     = 600000000,
+		.dbg_name = "gpll0_clk_src",
+		.ops      = &clk_ops_pll_vote,
+	},
+};
+
+/* SDCC Clocks */
+static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] =
+{
+	F(   144000,    cxo,  16,   3,  25),
+	F(   400000,    cxo,  12,   1,   4),
+	F( 20000000,  gpll0,  15,   1,   2),
+	F( 25000000,  gpll0,  12,   1,   2),
+	F( 50000000,  gpll0,  12,   0,   0),
+	F(100000000,  gpll0,   6,   0,   0),
+	F(200000000,  gpll0,   3,   0,   0),
+	F_END
+};
+
+static struct rcg_clk sdcc1_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) SDCC1_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) SDCC1_CFG_RCGR,
+	.m_reg        = (uint32_t *) SDCC1_M,
+	.n_reg        = (uint32_t *) SDCC1_N,
+	.d_reg        = (uint32_t *) SDCC1_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_sdcc1_2_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "sdc1_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_sdcc1_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) SDCC1_APPS_CBCR,
+	.parent       = &sdcc1_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_sdcc1_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk gcc_sdcc1_ahb_clk =
+{
+	.cbcr_reg     = (uint32_t *) SDCC1_AHB_CBCR,
+	.has_sibling  = 1,
+
+	.c = {
+		.dbg_name = "gcc_sdcc1_ahb_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+/* UART Clocks */
+static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] =
+{
+	F( 3686400,  gpll0,    1,  96,  15625),
+	F( 7372800,  gpll0,    1, 192,  15625),
+	F(14745600,  gpll0,    1, 384,  15625),
+	F(16000000,  gpll0,    5,   2,     15),
+	F(19200000,    cxo,    1,   0,      0),
+	F(24000000,  gpll0,    5,   1,      5),
+	F(32000000,  gpll0,    1,   4,     75),
+	F(40000000,  gpll0,   15,   0,      0),
+	F(46400000,  gpll0,    1,  29,    375),
+	F(48000000,  gpll0, 12.5,   0,      0),
+	F(51200000,  gpll0,    1,  32,    375),
+	F(56000000,  gpll0,    1,   7,     75),
+	F(58982400,  gpll0,    1, 1536, 15625),
+	F(60000000,  gpll0,   10,   0,      0),
+	F_END
+};
+
+static struct rcg_clk blsp1_uart3_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) BLSP1_UART3_APPS_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) BLSP1_UART3_APPS_CFG_RCGR,
+	.m_reg        = (uint32_t *) BLSP1_UART3_APPS_M,
+	.n_reg        = (uint32_t *) BLSP1_UART3_APPS_N,
+	.d_reg        = (uint32_t *) BLSP1_UART3_APPS_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "blsp1_uart3_apps_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_blsp1_uart3_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) BLSP1_UART3_APPS_CBCR,
+	.parent       = &blsp1_uart3_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp1_uart3_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct vote_clk gcc_blsp1_ahb_clk = {
+	.cbcr_reg     = (uint32_t *) BLSP1_AHB_CBCR,
+	.vote_reg     = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+	.en_mask      = BIT(17),
+
+	.c = {
+		.dbg_name = "gcc_blsp1_ahb_clk",
+		.ops      = &clk_ops_vote,
+	},
+};
+
+/* USB Clocks */
+static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] =
+{
+	F(75000000,  gpll0,   8,   0,   0),
+	F_END
+};
+
+static struct rcg_clk usb_hs_system_clk_src =
+{
+	.cmd_reg      = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR,
+
+	.set_rate     = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl     = ftbl_gcc_usb_hs_system_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "usb_hs_system_clk",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct branch_clk gcc_usb_hs_system_clk =
+{
+	.cbcr_reg     = (uint32_t *) USB_HS_SYSTEM_CBCR,
+	.parent       = &usb_hs_system_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_usb_hs_system_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk gcc_usb_hs_ahb_clk =
+{
+	.cbcr_reg     = (uint32_t *) USB_HS_AHB_CBCR,
+	.has_sibling  = 1,
+
+	.c = {
+		.dbg_name = "gcc_usb_hs_ahb_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+/* Clock lookup table */
+static struct clk_lookup msm_clocks_8226[] =
+{
+	CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
+	CLK_LOOKUP("sdc1_core_clk",  gcc_sdcc1_apps_clk.c),
+
+	CLK_LOOKUP("uart3_iface_clk", gcc_blsp1_ahb_clk.c),
+	CLK_LOOKUP("uart3_core_clk",  gcc_blsp1_uart3_apps_clk.c),
+
+	CLK_LOOKUP("usb_iface_clk",  gcc_usb_hs_ahb_clk.c),
+	CLK_LOOKUP("usb_core_clk",   gcc_usb_hs_system_clk.c),
+};
+
+void platform_clock_init(void)
+{
+	clk_init(msm_clocks_8226, ARRAY_SIZE(msm_clocks_8226));
+}
diff --git a/platform/msm8226/platform.c b/platform/msm8226/platform.c
new file mode 100644
index 0000000..1be05ed
--- /dev/null
+++ b/platform/msm8226/platform.c
@@ -0,0 +1,51 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <platform/clock.h>
+#include <qgic.h>
+#include <qtimer.h>
+
+void platform_early_init(void)
+{
+	platform_clock_init();
+	qgic_init();
+	qtimer_init();
+}
+
+void platform_init(void)
+{
+	dprintf(INFO, "platform_init()\n");
+}
+
+void platform_uninit(void)
+{
+	qtimer_uninit();
+}
diff --git a/platform/msm8226/rules.mk b/platform/msm8226/rules.mk
new file mode 100644
index 0000000..6645153
--- /dev/null
+++ b/platform/msm8226/rules.mk
@@ -0,0 +1,26 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+ARCH    := arm
+#Compiling this as cortex-a8 until the compiler supports cortex-a7
+ARM_CPU := cortex-a8
+CPU     := generic
+
+DEFINES += ARM_CPU_CORE_A7
+
+MMC_SLOT         := 1
+
+DEFINES += PERIPH_BLK_BLSP=1
+DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
+	   MMC_SLOT=$(MMC_SLOT)
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
+
+OBJS += \
+	$(LOCAL_DIR)/platform.o \
+	$(LOCAL_DIR)/acpuclock.o \
+	$(LOCAL_DIR)/msm8226-clock.o \
+	$(LOCAL_DIR)/gpio.o
+
+LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
+
+include platform/msm_shared/rules.mk
diff --git a/platform/msm_shared/dev_tree.c b/platform/msm_shared/dev_tree.c
index 82a4dab..04caeb1 100644
--- a/platform/msm_shared/dev_tree.c
+++ b/platform/msm_shared/dev_tree.c
@@ -36,7 +36,6 @@
 #include <platform.h>
 #include <board.h>
 
-extern unsigned char *update_cmdline(const char * cmdline);
 extern int target_is_emmc_boot(void);
 extern uint32_t target_dev_tree_mem(void *fdt, uint32_t memory_node_offset);
 
@@ -172,6 +171,8 @@
 	/* Get block size. */
 	blk_size = flash_block_size();
 
+	dprintf(INFO, "Add %d flash partitions to dt: start\n", ptable->count);
+
 	/* Need to add partitions in reverse order since libfdt adds
 	 * new nodes on the top.
 	 * Kernel looks to mount the partitions in the order specified in
@@ -246,6 +247,7 @@
 	}
 
 dev_tree_add_ptable_nodes_err:
+	dprintf(INFO, "Add %d flash partitions to dt: done\n", ptable->count);
 	free(ptn_name_array);
 	return dt_ret;
 }
@@ -369,7 +371,6 @@
 {
 	int ret = 0;
 	uint32_t offset;
-	unsigned char *final_cmdline;
 
 	/* Check the device tree header */
 	ret = fdt_check_header(fdt);
@@ -411,8 +412,7 @@
 
 	offset = ret;
 	/* Adding the cmdline to the chosen node */
-	final_cmdline = update_cmdline((const char*)cmdline);
-	ret = fdt_setprop_string(fdt, offset, (const char*)"bootargs", (const void*)final_cmdline);
+	ret = fdt_setprop_string(fdt, offset, (const char*)"bootargs", (const void*)cmdline);
 	if (ret)
 	{
 		dprintf(CRITICAL, "ERROR: Cannot update chosen node [bootargs]\n");
diff --git a/platform/msm_shared/display.c b/platform/msm_shared/display.c
index a3d77ce..c005bc9 100644
--- a/platform/msm_shared/display.c
+++ b/platform/msm_shared/display.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -9,7 +9,7 @@
  *       copyright notice, this list of conditions and the following
  *       disclaimer in the documentation and/or other materials provided
  *       with the distribution.
- *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *     * Neither the name of The Linux Foundation nor the names of its
  *       contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
  *
@@ -74,7 +74,12 @@
 		break;
 	case MIPI_VIDEO_PANEL:
 		dprintf(INFO, "Config MIPI_VIDEO_PANEL.\n");
-		ret = mipi_config(panel);
+
+		if (mdp_get_revision() == MDP_REV_50)
+			ret = mdss_dsi_config(panel);
+		else
+			ret = mipi_config(panel);
+
 		if (ret)
 			goto msm_display_config_out;
 
diff --git a/platform/msm_shared/include/clock_lib2.h b/platform/msm_shared/include/clock_lib2.h
index 2f6deb7..a7606bc 100644
--- a/platform/msm_shared/include/clock_lib2.h
+++ b/platform/msm_shared/include/clock_lib2.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2012-2013, Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -8,7 +8,7 @@
  *   * Redistributions in binary form must reproduce the above copyright
  *     notice, this list of conditions and the following disclaimer in the
  *     documentation and/or other materials provided with the distribution.
- *   * Neither the name of Code Aurora nor
+ *   * Neither the name of Linux Foundation nor
  *     the names of its contributors may be used to endorse or promote
  *     products derived from this software without specific prior written
  *     permission.
@@ -58,6 +58,17 @@
                               | BVAL(10, 8, s##_source_val), \
         }
 
+/* F_MM(frequency, source, div, m, n) */
+#define F_MM(f, s, div, m, n) \
+	{ \
+		.freq_hz = (f), \
+		.src_clk = &s##_clk_src.c, \
+		.m_val = (m), \
+		.n_val = ~((n)-(m)) * !!(n), \
+		.d_val = ~(n),\
+		.div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \
+			| BVAL(10, 8, s##_mm_source_val), \
+	}
 
 /* Branch Clock Bits */
 #define CBCR_BRANCH_ENABLE_BIT  BIT(0)
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
new file mode 100644
index 0000000..2091ed1
--- /dev/null
+++ b/platform/msm_shared/include/mdp5.h
@@ -0,0 +1,113 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  * Neither the name of The Linux Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PLATFORM_MSM_SHARED_MDP_5_H_
+#define _PLATFORM_MSM_SHARED_MDP_5_H_
+
+#include <msm_panel.h>
+
+#define MDP_VP_0_RGB_0_SSPP_SRC0_ADDR           REG_MDP(0x1E14)
+#define MDP_VP_0_RGB_0_SSPP_SRC_YSTRIDE         REG_MDP(0x1E24)
+#define MDP_VP_0_RGB_0_SSPP_SRC_IMG_SIZE        REG_MDP(0x1E04)
+#define MDP_VP_0_RGB_0_SSPP_SRC_SIZE            REG_MDP(0x1E00)
+#define MDP_VP_0_RGB_0_SSPP_SRC_OUT_SIZE        REG_MDP(0x1E0C)
+#define MDP_VP_0_RGB_0_SSPP_SRC_XY              REG_MDP(0x1E08)
+#define MDP_VP_0_RGB_0_SSPP_OUT_XY              REG_MDP(0x1E10)
+#define MDP_VP_0_RGB_0_SSPP_SRC_FORMAT          REG_MDP(0x1E30)
+#define MDP_VP_0_RGB_0_SSPP_SRC_UNPACK_PATTERN  REG_MDP(0x1E34)
+#define MDP_VP_0_RGB_0_SSPP_SRC_OP_MODE         REG_MDP(0x1E38)
+
+#define MDP_VP_0_LAYER_0_OUT_SIZE               REG_MDP(0x3204)
+#define MDP_VP_0_LAYER_0_OP_MODE                REG_MDP(0x3200)
+#define MDP_VP_0_LAYER_0_BLEND_OP               REG_MDP(0x3220)
+#define MDP_VP_0_LAYER_0_BLEND0_FG_ALPHA        REG_MDP(0x3224)
+#define MDP_VP_0_LAYER_1_BLEND_OP               REG_MDP(0x3250)
+#define MDP_VP_0_LAYER_1_BLEND0_FG_ALPHA        REG_MDP(0x3254)
+#define MDP_VP_0_LAYER_2_BLEND_OP               REG_MDP(0x3280)
+#define MDP_VP_0_LAYER_2_BLEND0_FG_ALPHA        REG_MDP(0x3284)
+#define MDP_VP_0_LAYER_3_BLEND_OP               REG_MDP(0x32B0)
+#define MDP_VP_0_LAYER_3_BLEND0_FG_ALPHA        REG_MDP(0x32B4)
+
+#define MDP_INTR_EN                             REG_MDP(0x0110)
+#define MDP_INTR_CLEAR                          REG_MDP(0x0118)
+#define MDP_HIST_INTR_EN                        REG_MDP(0x011C)
+
+#define MDP_DISP_INTF_SEL                       REG_MDP(0x0104)
+#define MDP_VIDEO_INTF_UNDERFLOW_CTL            REG_MDP(0x03E0)
+#define MDP_UPPER_NEW_ROI_PRIOR_RO_START        REG_MDP(0x02EC)
+#define MDP_LOWER_NEW_ROI_PRIOR_TO_START        REG_MDP(0x04F8)
+
+#define MDP_INTF_1_TIMING_ENGINE_EN             REG_MDP(0x21300)
+
+#define MDP_CTL_0_LAYER_0                       REG_MDP(0x600)
+#define MDP_CTL_0_TOP                           REG_MDP(0x614)
+#define MDP_CTL_0_FLUSH                         REG_MDP(0x618)
+
+#define MDP_INTF_1_HSYNC_CTL                    REG_MDP(0x21308)
+#define MDP_INTF_1_VSYNC_PERIOD_F0              REG_MDP(0x2130C)
+#define MDP_INTF_1_VSYNC_PERIOD_F1              REG_MDP(0x21310)
+#define MDP_INTF_1_VSYNC_PULSE_WIDTH_F0         REG_MDP(0x21314)
+#define MDP_INTF_1_VSYNC_PULSE_WIDTH_F1         REG_MDP(0x21318)
+#define MDP_INTF_1_DISPLAY_HCTL                 REG_MDP(0x2133C)
+#define MDP_INTF_1_DISPLAY_V_START_F0           REG_MDP(0x2131C)
+#define MDP_INTF_1_DISPLAY_V_START_F1           REG_MDP(0x21320)
+#define MDP_INTF_1_DISPLAY_V_END_F0             REG_MDP(0x21324)
+#define MDP_INTF_1_DISPLAY_V_END_F1             REG_MDP(0x21328)
+#define MDP_INTF_1_ACTIVE_HCTL                  REG_MDP(0x21340)
+#define MDP_INTF_1_ACTIVE_V_START_F0            REG_MDP(0x2132C)
+#define MDP_INTF_1_ACTIVE_V_START_F1            REG_MDP(0x21330)
+#define MDP_INTF_1_ACTIVE_V_END_F0              REG_MDP(0x21334)
+#define MDP_INTF_1_ACTIVE_V_END_F1              REG_MDP(0x21338)
+#define MDP_INTF_1_UNDERFFLOW_COLOR             REG_MDP(0x21348)
+#define MDP_INTF_1_PANEL_FORMAT                 REG_MDP(0x21390)
+
+#define MDP_CLK_CTRL0                           REG_MDP(0x03AC)
+#define MDP_CLK_CTRL1                           REG_MDP(0x03B4)
+#define MDP_CLK_CTRL2                           REG_MDP(0x03BC)
+#define MDP_CLK_CTRL3                           REG_MDP(0x04A8)
+#define MDP_CLK_CTRL4                           REG_MDP(0x04B0)
+
+#define MMSS_MDP_SMP_ALLOC_W_0                  REG_MDP(0x0180)
+#define MMSS_MDP_SMP_ALLOC_W_1                  REG_MDP(0x0184)
+#define MMSS_MDP_SMP_ALLOC_R_0                  REG_MDP(0x0230)
+#define MMSS_MDP_SMP_ALLOC_R_1                  REG_MDP(0x0234)
+
+#define VBIF_VBIF_DDR_FORCE_CLK_ON              REG_MDP(0x24004)
+#define VBIF_VBIF_DDR_OUT_MAX_BURST             REG_MDP(0x240D8)
+
+void mdp_set_revision(int rev);
+int mdp_get_revision();
+int mdp_dsi_video_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
+int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg,
+			unsigned short num_of_lanes);
+int mdp_dsi_video_on(void);
+int mdp_dma_on(void);
+void mdp_disable(void);
+
+#endif
diff --git a/platform/msm_shared/include/mipi_dsi.h b/platform/msm_shared/include/mipi_dsi.h
index 1efb1df..8e44068 100644
--- a/platform/msm_shared/include/mipi_dsi.h
+++ b/platform/msm_shared/include/mipi_dsi.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -9,7 +9,7 @@
  *       copyright notice, this list of conditions and the following
  *       disclaimer in the documentation and/or other materials provided
  *       with the distribution.
- *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *     * Neither the name of The Linux Foundation nor the names of its
  *       contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
  *
@@ -455,6 +455,162 @@
 /* Done Toshiba MDT61 Panel Commands */
 /* Toshiba MDT61 (R69320) End */
 
+/* Toshiba MDV24 panel commands */
+static const unsigned char toshiba_mdv24_mcap[4] = {
+	0xB0, 0x00, DTYPE_GEN_WRITE2, 0x80,
+};
+
+static const unsigned char toshiba_mdv24_acr[4] = {
+	0xB2, 0x00, DTYPE_GEN_WRITE2, 0x80,
+};
+
+static const unsigned char toshiba_mdv24_intf[4] = {
+	0xB3, 0x0c, DTYPE_GEN_WRITE2, 0x80,
+};
+
+static const unsigned char toshiba_mdv24_pixel[4] = {
+	0xB4, 0x02, DTYPE_GEN_WRITE2, 0x80,
+};
+
+static const unsigned char toshiba_mdv24_drive_setting[12] = {
+	0x06, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+	0xC0, 0x40, 0x02, 0x7F,
+	0xC8, 0x08, 0xFF, 0xFF
+};
+
+static const unsigned char toshiba_mdv24_display_h_timing[20] = {
+	0x10, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+	0xC1, 0x00, 0xA8, 0x00,
+	0x00, 0x00, 0x00, 0x00,
+	0x9D, 0x08, 0x27, 0x09,
+	0x00, 0x00, 0x00, 0x00
+};
+
+static const unsigned char toshiba_mdv24_source_output[12] = {
+	0x06, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+	0xC2, 0x00, 0x00, 0x09,
+	0x00, 0x00, 0xFF, 0xFF
+};
+
+static const unsigned char toshiba_mdv24_gate_control[4] = {
+	0xC3, 0x04, DTYPE_GEN_WRITE2, 0x80,
+};
+
+static const unsigned char toshiba_mdv24_ltps_control_c4[8] = {
+	0x04, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+	0xC4, 0x4d, 0x83, 0x00
+};
+
+static const unsigned char toshiba_mdv24_source_output_mode[16] = {
+	0x0B, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+	0xC6, 0x12, 0x00, 0x08,
+	0x71, 0x00, 0x00, 0x00,
+	0x80, 0x00, 0x04, 0xFF
+};
+
+static const unsigned char toshiba_mdv24_ltps_control_c7[4] = {
+	0xC7, 0x22, DTYPE_GEN_WRITE2, 0x80,
+};
+
+static const unsigned char toshiba_mdv24_gamma_ctrl[12] = {
+	0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+	0xC8, 0x4C, 0x0C, 0x0C,
+	0x0C, 0xFF, 0xFF, 0xFF
+};
+
+static const unsigned char toshiba_mdv24_gamma_ctrl_a_pos[20] = {
+	0x0E, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+	0xC9, 0x00, 0x40, 0x00,
+	0x16, 0x32, 0x2E, 0x3A,
+	0x43, 0x3E, 0x3C, 0x45,
+	0x79, 0x3F, 0xFF, 0xFF
+};
+
+static const unsigned char toshiba_mdv24_gamma_ctrl_a_neg[20] = {
+	0x0E, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+	0xCA, 0x00, 0x46, 0x1A,
+	0x23, 0x21, 0x1C, 0x25,
+	0x31, 0x2D, 0x49, 0x5F,
+	0x7F, 0x3F, 0xFF, 0xFF
+};
+
+static const unsigned char toshiba_mdv24_gamma_ctrl_b_pos[20] = {
+	0x0E, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+	0xCb, 0x00, 0x4c, 0x20,
+	0x3A, 0x42, 0x40, 0x47,
+	0x4B, 0x42, 0x3E, 0x46,
+	0x7E, 0x3F, 0xFF, 0xFF
+};
+
+static const unsigned char toshiba_mdv24_gamma_ctrl_b_neg[20] = {
+	0x0E, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+	0xCC, 0x00, 0x41, 0x19,
+	0x21, 0x1D, 0x14, 0x18,
+	0x1F, 0x1D, 0x25, 0x3F,
+	0x73, 0x3F, 0xFF, 0xFF
+};
+
+static const unsigned char toshiba_mdv24_gamma_ctrl_c_pos[20] = {
+	0x0E, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+	0xCD, 0x23, 0x79, 0x5A,
+	0x5F, 0x57, 0x4C, 0x51,
+	0x51, 0x45, 0x3F, 0x4B,
+	0x7F, 0x3F, 0xFF, 0xFF
+};
+
+static const unsigned char toshiba_mdv24_gamma_ctrl_c_neg[20] = {
+	0x0E, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+	0xCE, 0x00, 0x40, 0x14,
+	0x20, 0x1A, 0x0E, 0x0E,
+	0x13, 0x08, 0x00, 0x05,
+	0x46, 0x1C, 0xFF, 0xFF
+};
+
+static const unsigned char toshiba_mdv24_pwr_setting1[8] = {
+	0x04, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+	0xD0, 0x6A, 0x64, 0x01
+};
+
+static const unsigned char toshiba_mdv24_pwr_setting2[8] = {
+	0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+	0xD1, 0x77, 0xd4, 0xFF
+};
+
+static const unsigned char toshiba_mdv24_pwr_setting_internal[4] = {
+	0xD3, 0x33, DTYPE_GEN_WRITE2, 0x80,
+};
+
+static const unsigned char toshiba_mdv24_lvl_setting[8] = {
+	0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+	0xD5, 0x0F, 0x0F, 0xFF
+};
+
+static const unsigned char toshiba_mdv24_vcomdc_setting1[12] = {
+	0x07, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+	0xD8, 0x34, 0x64, 0x23,
+	0x25, 0x62, 0x32, 0xFF
+};
+
+static const unsigned char toshiba_mdv24_vcomdc_setting2[16] = {
+	0x0C, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+	0xDE, 0x10, 0x7B, 0x11,
+	0x0A, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00
+};
+
+static const unsigned char toshiba_mdv24_init_fd[16] = {
+	0x09, 0x00, DTYPE_GEN_LWRITE, 0xC0,
+	0xFD, 0x04, 0x55, 0x53,
+	0x00, 0x70, 0xFF, 0x10,
+	0x73, 0xFF, 0xFF, 0xFF
+};
+
+static const unsigned char toshiba_mdv24_nvm_load_ctrl[4] = {
+	0xE2, 0x00, DTYPE_GEN_WRITE2, 0x80,
+};
+
+/* End of Toshiba MDV24 commands */
+
 static const unsigned char dsi_display_exit_sleep[4] = {
 	0x11, 0x00, 0x15, 0x80,
 };
@@ -463,6 +619,7 @@
 	0x29, 0x00, 0x15, 0x80,
 };
 
+
 #define MIPI_VIDEO_MODE	        1
 #define MIPI_CMD_MODE           2
 
@@ -474,6 +631,15 @@
 	uint32_t pll[21];
 };
 
+struct mdss_dsi_phy_ctrl {
+	uint32_t regulator[7];
+	uint32_t timing[12];
+	uint32_t ctrl[4];
+	uint32_t strength[2];
+	char bistCtrl[6];
+	char laneCfg[45];
+};
+
 struct mipi_dsi_cmd {
 	int size;
 	char *payload;
@@ -483,7 +649,9 @@
 	char mode;
 	char num_of_lanes;
 	char lane_swap;
+	char pack;
 	struct mipi_dsi_phy_ctrl *dsi_phy_config;
+	struct mdss_dsi_phy_ctrl *mdss_dsi_phy_config;
 	struct mipi_dsi_cmd *panel_cmds;
 	int num_of_panel_cmds;
 };
@@ -599,6 +767,60 @@
 	{sizeof(dsi_display_display_on), (char *)dsi_display_display_on},
 };
 
+static struct mipi_dsi_cmd toshiba_mdv24_video_mode_cmds[] = {
+	{sizeof(toshiba_mdv24_mcap), (char *)toshiba_mdv24_mcap},
+	{sizeof(toshiba_mdv24_acr),
+	 (char *)toshiba_mdv24_acr},
+	{sizeof(toshiba_mdv24_intf), (char *)toshiba_mdv24_intf},
+	{sizeof(toshiba_mdv24_pixel), (char *)toshiba_mdv24_pixel},
+	{sizeof(toshiba_mdv24_drive_setting),
+	 (char *)toshiba_mdv24_drive_setting},
+	{sizeof(toshiba_mdv24_display_h_timing),
+	 (char *)toshiba_mdv24_display_h_timing},
+	{sizeof(toshiba_mdv24_source_output),
+	 (char *)toshiba_mdv24_source_output},
+	{sizeof(toshiba_mdv24_gate_control),
+	 (char *)toshiba_mdv24_gate_control},
+	{sizeof(toshiba_mdv24_ltps_control_c4),
+	 (char *)toshiba_mdv24_ltps_control_c4},
+	{sizeof(toshiba_mdv24_source_output_mode),
+	 (char *)toshiba_mdv24_source_output_mode},
+	{sizeof(toshiba_mdv24_ltps_control_c7),
+	 (char *)toshiba_mdv24_ltps_control_c7},
+	{sizeof(toshiba_mdv24_gamma_ctrl),
+	 (char *)toshiba_mdv24_gamma_ctrl},
+	{sizeof(toshiba_mdv24_gamma_ctrl_a_pos),
+	 (char *)toshiba_mdv24_gamma_ctrl_a_pos},
+	{sizeof(toshiba_mdv24_gamma_ctrl_a_neg),
+	 (char *)toshiba_mdv24_gamma_ctrl_a_neg},
+	{sizeof(toshiba_mdv24_gamma_ctrl_a_pos),
+	 (char *)toshiba_mdv24_gamma_ctrl_a_pos},
+	{sizeof(toshiba_mdv24_gamma_ctrl_a_neg),
+	 (char *)toshiba_mdv24_gamma_ctrl_a_neg},
+	{sizeof(toshiba_mdv24_gamma_ctrl_b_pos),
+	 (char *)toshiba_mdv24_gamma_ctrl_b_pos},
+	{sizeof(toshiba_mdv24_gamma_ctrl_c_neg),
+	 (char *)toshiba_mdv24_gamma_ctrl_c_neg},
+	{sizeof(toshiba_mdv24_pwr_setting1),
+	 (char *)toshiba_mdv24_pwr_setting1},
+	{sizeof(toshiba_mdv24_pwr_setting2),
+	 (char *)toshiba_mdv24_pwr_setting2},
+	{sizeof(toshiba_mdv24_pwr_setting_internal),
+	 (char *)toshiba_mdv24_pwr_setting_internal},
+	{sizeof(toshiba_mdv24_lvl_setting),
+	 (char *)toshiba_mdv24_lvl_setting},
+	{sizeof(toshiba_mdv24_vcomdc_setting1),
+	 (char *)toshiba_mdv24_vcomdc_setting1},
+	{sizeof(toshiba_mdv24_vcomdc_setting2),
+	 (char *)toshiba_mdv24_vcomdc_setting2},
+	{sizeof(toshiba_mdv24_init_fd),
+	 (char *)toshiba_mdv24_init_fd},
+	{sizeof(toshiba_mdv24_nvm_load_ctrl),
+	 (char *)toshiba_mdv24_nvm_load_ctrl},
+	{sizeof(dsi_display_exit_sleep), (char *)dsi_display_exit_sleep},
+	{sizeof(dsi_display_display_on), (char *)dsi_display_display_on},
+};
+
 static struct mipi_dsi_phy_ctrl mipi_dsi_toshiba_mdt61_panel_phy_ctrl = {
 	/* 600*1024, RGB888, 3 Lane 55 fps video mode */
 	{0x03, 0x0a, 0x04, 0x00, 0x20},
@@ -696,6 +918,8 @@
 #define DSI_CMD_TRIGGER_SW_TE		0x06
 
 int mipi_config(struct msm_fb_panel_data *panel);
+int mdss_dsi_config(struct msm_fb_panel_data *panel);
+
 int mipi_dsi_video_mode_config(unsigned short disp_width,
 		unsigned short disp_height,
 		unsigned short img_width,
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index 428d406..6e14bd0 100644
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -9,7 +9,7 @@
  *       copyright notice, this list of conditions and the following
  *       disclaimer in the documentation and/or other materials provided
  *       with the distribution.
- *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *     * Neither the name of The Linux Foundation nor the names of its
  *       contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
  *
@@ -61,6 +61,7 @@
 	MDP_REV_42,
 	MDP_REV_43,
 	MDP_REV_44,
+	MDP_REV_50,
 };
 
 /* panel info type */
@@ -113,6 +114,7 @@
 	char t_clk_pre;  /* 0xc0, DSI_CLKOUT_TIMING_CTRL */
 	char vc;	/* virtual channel */
 	struct mipi_dsi_phy_ctrl *dsi_phy_db;
+	struct mdss_dsi_phy_ctrl *mdss_dsi_phy_db;
 	struct mipi_dsi_cmd *panel_cmds;
 	int num_of_panel_cmds;
 	/* video mode */
diff --git a/platform/msm_shared/include/scm.h b/platform/msm_shared/include/scm.h
index 2b7903c..418574b 100644
--- a/platform/msm_shared/include/scm.h
+++ b/platform/msm_shared/include/scm.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
 
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -9,7 +9,7 @@
  *     copyright notice, this list of conditions and the following
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
- *   * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *   * Neither the name of The Linux Foundation nor the names of its
  *     contributors may be used to endorse or promote products derived
  *     from this software without specific prior written permission.
  *
@@ -57,10 +57,20 @@
 	uint32 *img_len_ptr;
 } img_req;
 
+typedef struct {
+	uint32 id;
+	uint32 spare;
+} tz_secure_cfg;
+
 #define SCM_SVC_SSD                 7
 #define SSD_DECRYPT_ID              0x01
 #define SSD_ENCRYPT_ID              0x02
 
+#define SCM_SVC_SSD                 0x0C
+#define IOMMU_SECURE_CFG            0x02
+
+#define SECURE_DEVICE_MDSS          1
+
 static uint32 smc(uint32 cmd_addr);
 
 int decrypt_scm(uint32_t ** img_ptr, uint32_t * img_len_ptr);
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
new file mode 100644
index 0000000..54fc33b
--- /dev/null
+++ b/platform/msm_shared/mdp5.c
@@ -0,0 +1,233 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *   * Neither the name of The Linux Foundation nor
+ *     the names of its contributors may be used to endorse or promote
+ *     products derived from this software without specific prior written
+ *     permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <mdp5.h>
+#include <debug.h>
+#include <reg.h>
+#include <target/display.h>
+#include <platform/timer.h>
+#include <platform/iomap.h>
+#include <dev/lcdc.h>
+#include <dev/fbcon.h>
+#include <bits.h>
+#include <msm_panel.h>
+#include <mipi_dsi.h>
+#include <err.h>
+#include <clock.h>
+#include <mdp5.h>
+#include <scm.h>
+
+int restore_secure_cfg(uint32_t id);
+
+static int mdp_rev;
+
+void mdp_set_revision(int rev)
+{
+	mdp_rev = rev;
+}
+
+int mdp_get_revision()
+{
+	return mdp_rev;
+}
+
+void mdp_clk_gating_ctrl(void)
+{
+	writel(0x40000000, MDP_CLK_CTRL0);
+	udelay(20);
+	writel(0x40000040, MDP_CLK_CTRL0);
+	writel(0x40000000, MDP_CLK_CTRL1);
+	writel(0x00400000, MDP_CLK_CTRL3);
+	udelay(20);
+	writel(0x00404000, MDP_CLK_CTRL3);
+	writel(0x40000000, MDP_CLK_CTRL4);
+}
+
+int mdp_dsi_video_config(struct msm_panel_info *pinfo,
+		struct fbcon_config *fb)
+{
+	int ret = NO_ERROR;
+	uint32_t hsync_period, vsync_period;
+	uint32_t hsync_start_x, hsync_end_x;
+	uint32_t display_hctl, active_hctl, hsync_ctl, display_vstart, display_vend;
+	struct lcdc_panel_info *lcdc = NULL;
+	unsigned mdp_rgb_size;
+	int access_secure = 0;
+
+	if (pinfo == NULL)
+		return ERR_INVALID_ARGS;
+
+	lcdc =  &(pinfo->lcdc);
+	if (lcdc == NULL)
+		return ERR_INVALID_ARGS;
+
+	hsync_period = lcdc->h_pulse_width +
+		lcdc->h_back_porch +
+		pinfo->xres + lcdc->xres_pad + lcdc->h_front_porch;
+	vsync_period = (lcdc->v_pulse_width +
+			lcdc->v_back_porch +
+			pinfo->yres + lcdc->yres_pad +
+			lcdc->v_front_porch);
+
+	hsync_start_x =
+		lcdc->h_pulse_width +
+		lcdc->h_back_porch;
+	hsync_end_x =
+		hsync_period - lcdc->h_front_porch - 1;
+
+	display_vstart = (lcdc->v_pulse_width +
+			lcdc->v_back_porch)
+		* hsync_period + lcdc->hsync_skew;
+	display_vend = ((vsync_period - lcdc->v_front_porch) * hsync_period)
+		+lcdc->hsync_skew - 1;
+
+	hsync_ctl = (hsync_period << 16) | lcdc->h_pulse_width;
+	display_hctl = (hsync_end_x << 16) | hsync_start_x;
+
+	/* write active region size*/
+	mdp_rgb_size = (fb->height << 16) + fb->width;
+
+	/* Ping-Pong done Tear Check Read/Write  */
+	/* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable  */
+	writel(0xFF777713, MDP_INTR_EN);
+
+	access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS);
+
+	mdp_clk_gating_ctrl();
+
+	if (!access_secure) {
+		/* Force VBIF Clocks on  */
+		writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON);
+		/* Configure DDR burst length */
+		writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST);
+	}
+
+	/* Allocate SMP blocks */
+	writel(0x00101010, MMSS_MDP_SMP_ALLOC_W_0);
+	writel(0x00000010, MMSS_MDP_SMP_ALLOC_W_1);
+	writel(0x00101010, MMSS_MDP_SMP_ALLOC_R_0);
+	writel(0x00000010, MMSS_MDP_SMP_ALLOC_R_1);
+
+	writel(hsync_ctl, MDP_INTF_1_HSYNC_CTL);
+	writel(vsync_period*hsync_period, MDP_INTF_1_VSYNC_PERIOD_F0);
+	writel(0x00, MDP_INTF_1_VSYNC_PERIOD_F1);
+	writel(lcdc->v_pulse_width*hsync_period, MDP_INTF_1_VSYNC_PULSE_WIDTH_F0);
+	writel(0x00, MDP_INTF_1_VSYNC_PULSE_WIDTH_F1);
+	writel(display_hctl, MDP_INTF_1_DISPLAY_HCTL);
+	writel(display_vstart, MDP_INTF_1_DISPLAY_V_START_F0);
+	writel(0x00, MDP_INTF_1_DISPLAY_V_START_F1);
+	writel(display_vend, MDP_INTF_1_DISPLAY_V_END_F0);
+	writel(0x00, MDP_INTF_1_DISPLAY_V_END_F1);
+	writel(0x00, MDP_INTF_1_ACTIVE_HCTL);
+	writel(0x00, MDP_INTF_1_ACTIVE_V_START_F0);
+	writel(0x00, MDP_INTF_1_ACTIVE_V_START_F1);
+	writel(0x00, MDP_INTF_1_ACTIVE_V_END_F0);
+	writel(0x00, MDP_INTF_1_ACTIVE_V_END_F1);
+	writel(0xFF, MDP_INTF_1_UNDERFFLOW_COLOR);
+
+	writel(fb->base, MDP_VP_0_RGB_0_SSPP_SRC0_ADDR);
+	writel((fb->stride * fb->bpp/8),MDP_VP_0_RGB_0_SSPP_SRC_YSTRIDE);
+	writel(mdp_rgb_size, MDP_VP_0_RGB_0_SSPP_SRC_IMG_SIZE);
+	writel(mdp_rgb_size, MDP_VP_0_RGB_0_SSPP_SRC_SIZE);
+	writel(mdp_rgb_size, MDP_VP_0_RGB_0_SSPP_SRC_OUT_SIZE);
+	writel(0x00, MDP_VP_0_RGB_0_SSPP_SRC_XY);
+	writel(0x00, MDP_VP_0_RGB_0_SSPP_OUT_XY);
+	/* Tight Packing 3bpp 0-Alpha 8-bit R B G */
+	writel(0x0002243F, MDP_VP_0_RGB_0_SSPP_SRC_FORMAT);
+	writel(0x00020001, MDP_VP_0_RGB_0_SSPP_SRC_UNPACK_PATTERN);
+	writel(0x00, MDP_VP_0_RGB_0_SSPP_SRC_OP_MODE);
+
+	writel(mdp_rgb_size,MDP_VP_0_LAYER_0_OUT_SIZE);
+	writel(0x00, MDP_VP_0_LAYER_0_OP_MODE);
+	writel(0x100, MDP_VP_0_LAYER_0_BLEND_OP);
+	writel(0xFF, MDP_VP_0_LAYER_0_BLEND0_FG_ALPHA);
+	writel(0x100, MDP_VP_0_LAYER_1_BLEND_OP);
+	writel(0xFF, MDP_VP_0_LAYER_1_BLEND0_FG_ALPHA);
+	writel(0x100, MDP_VP_0_LAYER_2_BLEND_OP);
+	writel(0xFF, MDP_VP_0_LAYER_2_BLEND0_FG_ALPHA);
+	writel(0x100, MDP_VP_0_LAYER_3_BLEND_OP);
+	writel(0xFF, MDP_VP_0_LAYER_3_BLEND0_FG_ALPHA);
+
+	/* Baselayer for layer mixer 0 */
+	writel(0x010000200, MDP_CTL_0_LAYER_0);
+
+	writel(0x1F20, MDP_CTL_0_TOP);
+	writel(0x213F, MDP_INTF_1_PANEL_FORMAT);
+
+	writel(0x0100, MDP_DISP_INTF_SEL);
+	writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL);
+	writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START);
+	writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START);
+
+	return 0;
+}
+
+int mdp_dsi_cmd_config(struct msm_panel_info *pinfo,
+                struct fbcon_config *fb)
+{
+
+	int ret = 0;
+	return ret;
+}
+
+int mdp_dsi_video_on(void)
+{
+	int ret = NO_ERROR;
+	writel(0x32048, MDP_CTL_0_FLUSH);
+	writel(0x01, MDP_INTF_1_TIMING_ENGINE_EN);
+	return ret;
+}
+
+int mdp_dsi_video_off()
+{
+	if(!target_cont_splash_screen())
+	{
+		writel(0x00000000, MDP_INTF_1_TIMING_ENGINE_EN);
+		mdelay(60);
+		/* Ping-Pong done Tear Check Read/Write  */
+		/* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable  */
+		writel(0xFF777713, MDP_INTR_CLEAR);
+		writel(0x00000000, MDP_INTR_EN);
+	}
+
+	return NO_ERROR;
+}
+
+int mdp_dsi_cmd_off()
+{
+	return NO_ERROR;
+}
+
+int mdp_dma_on(void)
+{
+	return NO_ERROR;
+}
+
+void mdp_disable(void)
+{
+
+}
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index ba1da29..7a1c4eb 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -9,7 +9,7 @@
  *       copyright notice, this list of conditions and the following
  *       disclaimer in the documentation and/or other materials provided
  *       with the distribution.
- *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *     * Neither the name of The Linux Foundation nor the names of its
  *       contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
  *
@@ -256,15 +256,15 @@
 
 int mipi_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo)
 {
-	unsigned char DMA_STREAM1 = 0;	// for mdp display processor path
-	unsigned char EMBED_MODE1 = 1;	// from frame buffer
-	unsigned char POWER_MODE2 = 1;	// from frame buffer
-	unsigned char PACK_TYPE1 = 1;	// long packet
-	unsigned char VC1 = 0;
-	unsigned char DT1 = 0;	// non embedded mode
-	unsigned short WC1 = 0;	// for non embedded mode only
+	uint8_t DMA_STREAM1 = 0;	// for mdp display processor path
+	uint8_t EMBED_MODE1 = 1;	// from frame buffer
+	uint8_t POWER_MODE2 = 1;	// from frame buffer
+	uint8_t PACK_TYPE1;		// long packet
+	uint8_t VC1 = 0;
+	uint8_t DT1 = 0;	// non embedded mode
+	uint8_t WC1 = 0;	// for non embedded mode only
 	int status = 0;
-	unsigned char DLNx_EN;
+	uint8_t DLNx_EN;
 
 	switch (pinfo->num_of_lanes) {
 	default:
@@ -282,6 +282,8 @@
 		break;
 	}
 
+	PACK_TYPE1 = pinfo->pack;
+
 	writel(0x0001, DSI_SOFT_RESET);
 	writel(0x0000, DSI_SOFT_RESET);
 
@@ -352,14 +354,16 @@
 
 	writel(0x02020202, DSI_INT_CTRL);
 
-	writel(((img_width + hsync_porch0_bp) << 16) | hsync_porch0_bp,
+	writel(((hsync_width + img_width + hsync_porch0_bp) << 16)
+	       | (hsync_width + hsync_porch0_bp),
 	       DSI_VIDEO_MODE_ACTIVE_H);
 
-	writel(((img_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp),
+	writel(((vsync_width + img_height + vsync_porch0_bp) << 16)
+	       | (vsync_width + vsync_porch0_bp),
 	       DSI_VIDEO_MODE_ACTIVE_V);
 
-	writel(((img_height + vsync_porch0_fp + vsync_porch0_bp) << 16)
-	       | img_width + hsync_porch0_fp + hsync_porch0_bp,
+	writel(((vsync_width + img_height + vsync_porch0_fp + vsync_porch0_bp - 1) << 16)
+	       | (hsync_width + img_width + hsync_porch0_fp + hsync_porch0_bp - 1),
 	       DSI_VIDEO_MODE_TOTAL);
 
 	writel((hsync_width << 16) | 0, DSI_VIDEO_MODE_HSYNC);
@@ -588,7 +592,7 @@
 	}
 
 	/* Enable MMSS_AHB_ARB_MATER_PORT_E for arbiter master0 and master 1 request */
-#if (!DISPLAY_MIPI_PANEL_RENESAS)
+#if (!DISPLAY_MIPI_PANEL_RENESAS && !DISPLAY_TYPE_DSI6G)
 	writel(0x00001800, MMSS_SFPB_GPREG);
 #endif
 
@@ -631,10 +635,11 @@
 	mipi_pinfo.panel_cmds = pinfo->mipi.panel_cmds;
 	mipi_pinfo.num_of_panel_cmds = pinfo->mipi.num_of_panel_cmds;
 	mipi_pinfo.lane_swap = pinfo->mipi.lane_swap;
+	mipi_pinfo.pack = 1;
 
 	/* Enable MMSS_AHB_ARB_MATER_PORT_E for
 	   arbiter master0 and master 1 request */
-#if (!DISPLAY_MIPI_PANEL_RENESAS)
+#if (!DISPLAY_MIPI_PANEL_RENESAS && !DISPLAY_TYPE_DSI6G)
 	writel(0x00001800, MMSS_SFPB_GPREG);
 #endif
 
@@ -648,6 +653,34 @@
 	return ret;
 }
 
+int mdss_dsi_config(struct msm_fb_panel_data *panel)
+{
+	int ret = NO_ERROR;
+	struct msm_panel_info *pinfo;
+	struct mipi_dsi_panel_config mipi_pinfo;
+
+	if (!panel)
+		return ERR_INVALID_ARGS;
+
+	pinfo = &(panel->panel_info);
+	mipi_pinfo.mode = pinfo->mipi.mode;
+	mipi_pinfo.num_of_lanes = pinfo->mipi.num_of_lanes;
+	mipi_pinfo.mdss_dsi_phy_config = pinfo->mipi.mdss_dsi_phy_db;
+	mipi_pinfo.panel_cmds = pinfo->mipi.panel_cmds;
+	mipi_pinfo.num_of_panel_cmds = pinfo->mipi.num_of_panel_cmds;
+	mipi_pinfo.lane_swap = pinfo->mipi.lane_swap;
+	mipi_pinfo.pack = 0;
+
+	mdss_dsi_phy_init(&mipi_pinfo);
+
+	ret += mipi_dsi_panel_initialize(&mipi_pinfo);
+
+	if (pinfo->rotate && panel->rotate)
+		pinfo->rotate();
+
+	return ret;
+}
+
 int mipi_dsi_video_mode_config(unsigned short disp_width,
 	unsigned short disp_height,
 	unsigned short img_width,
@@ -835,8 +868,13 @@
 	if(!target_cont_splash_screen())
 	{
 		writel(0, DSI_CLK_CTRL);
+		writel(0x1F1, DSI_CTRL);
+		writel(0x00000001, DSIPHY_SW_RESET);
+		writel(0x00000000, DSIPHY_SW_RESET);
+		mdelay(10);
+		writel(0x0001, DSI_SOFT_RESET);
+		writel(0x0000, DSI_SOFT_RESET);
 		writel(0, DSI_CTRL);
-		writel(0, DSIPHY_PLL_CTRL(0));
 	}
 
 	return NO_ERROR;
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index eabfecf..60a1f97 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -9,7 +9,7 @@
  *       copyright notice, this list of conditions and the following
  *       disclaimer in the documentation and/or other materials provided
  *       with the distribution.
- *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *     * Neither the name of The Linux Foundation nor the names of its
  *       contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
  *
@@ -180,3 +180,131 @@
 	}
 	return 0;
 }
+
+int mdss_dsi_uniphy_pll_config(void)
+{
+	/* Configuring the Pll Vco clk to 424 Mhz */
+
+	/* Loop filter resistance value */
+	writel(0x08, MIPI_DSI_BASE + 0x022c);
+	/* Loop filter capacitance values : c1 and c2 */
+	writel(0x70, MIPI_DSI_BASE + 0x0230);
+	writel(0x15, MIPI_DSI_BASE + 0x0234);
+
+	writel(0x02, MIPI_DSI_BASE + 0x0208); /* ChgPump */
+	writel(0x00, MIPI_DSI_BASE + 0x0204); /* postDiv1 */
+	writel(0x03, MIPI_DSI_BASE + 0x0224); /* postDiv2 */
+	writel(0x03, MIPI_DSI_BASE + 0x0228); /* postDiv3 */
+
+	writel(0x2b, MIPI_DSI_BASE + 0x0278); /* Cal CFG3 */
+	writel(0x06, MIPI_DSI_BASE + 0x027c); /* Cal CFG4 */
+	writel(0x05, MIPI_DSI_BASE + 0x0264); /* Cal CFG4 */
+
+	writel(0x0a, MIPI_DSI_BASE + 0x023c); /* SDM CFG1 */
+	writel(0xab, MIPI_DSI_BASE + 0x0240); /* SDM CFG2 */
+	writel(0x0a, MIPI_DSI_BASE + 0x0244); /* SDM CFG3 */
+	writel(0x00, MIPI_DSI_BASE + 0x0248); /* SDM CFG4 */
+
+	udelay(10);
+
+	writel(0x01, MIPI_DSI_BASE + 0x0200); /* REFCLK CFG */
+	writel(0x00, MIPI_DSI_BASE + 0x0214); /* PWRGEN CFG */
+	writel(0x01, MIPI_DSI_BASE + 0x020c); /* VCOLPF CFG */
+	writel(0x02, MIPI_DSI_BASE + 0x0210); /* VREG CFG */
+	writel(0x00, MIPI_DSI_BASE + 0x0238); /* SDM CFG0 */
+
+	writel(0x5f, MIPI_DSI_BASE + 0x028c); /* CAL CFG8 */
+	writel(0xa8, MIPI_DSI_BASE + 0x0294); /* CAL CFG10 */
+	writel(0x01, MIPI_DSI_BASE + 0x0298); /* CAL CFG11 */
+	writel(0x0a, MIPI_DSI_BASE + 0x026c); /* CAL CFG0 */
+	writel(0x30, MIPI_DSI_BASE + 0x0284); /* CAL CFG6 */
+	writel(0x00, MIPI_DSI_BASE + 0x0288); /* CAL CFG7 */
+	writel(0x00, MIPI_DSI_BASE + 0x0290); /* CAL CFG9 */
+	writel(0x20, MIPI_DSI_BASE + 0x029c); /* EFUSE CFG */
+
+	writel(0x01, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
+	writel(0x05, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
+	udelay(20);
+	writel(0x07, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
+	udelay(20);
+	writel(0x0f, MIPI_DSI_BASE + 0x0220); /* GLB CFG */
+
+	while (!(readl(MIPI_DSI_BASE + 0x02c0) & 0x01))
+		udelay(1);
+
+
+}
+int mdss_dsi_phy_init(struct mipi_dsi_panel_config *pinfo)
+{
+	struct mdss_dsi_phy_ctrl *pd;
+	uint32_t i, off = 0, ln, offset;
+
+	pd = (pinfo->mdss_dsi_phy_config);
+
+	/* Strength ctrl 0 */
+	writel(0x07, MIPI_DSI_BASE + 0x0484);
+	writel(pd->strength[0], MIPI_DSI_BASE + 0x0484);
+
+	off = 0x0580;	/* phy regulator ctrl settings */
+	/* Regulator ctrl - CAL_PWD_CFG */
+	writel(pd->regulator[6], MIPI_DSI_BASE + off + (4 * 6));
+	/* Regulator ctrl - TEST */
+	writel(pd->regulator[5], MIPI_DSI_BASE + off + (4 * 5));
+	/* Regulator ctrl 3 */
+	writel(pd->regulator[3], MIPI_DSI_BASE + off + (4 * 3));
+	/* Regulator ctrl 2 */
+	writel(pd->regulator[2], MIPI_DSI_BASE + off + (4 * 2));
+	/* Regulator ctrl 1 */
+	writel(pd->regulator[1], MIPI_DSI_BASE + off + (4 * 1));
+	/* Regulator ctrl 0 */
+	writel(pd->regulator[0], MIPI_DSI_BASE + off + (4 * 0));
+	/* Regulator ctrl 4 */
+	writel(pd->regulator[4], MIPI_DSI_BASE + off + (4 * 4));
+	dmb();
+
+	off = 0x0440;	/* phy timing ctrl 0 - 11 */
+	for (i = 0; i < 12; i++) {
+		writel(pd->timing[i], MIPI_DSI_BASE + off);
+		dmb();
+		off += 4;
+	}
+
+	/* MMSS_DSI_0_PHY_DSIPHY_CTRL_1 */
+	writel(0x00, MIPI_DSI_BASE + 0x0474);
+	/* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */
+	writel(0x5f, MIPI_DSI_BASE + 0x0470);
+
+	/* Strength ctrl 1 */
+	writel(pd->strength[1], MIPI_DSI_BASE + 0x0488);
+	dmb();
+	/* 4 lanes + clk lane configuration */
+	/* lane config n * (0 - 4) & DataPath setup */
+	for (ln = 0; ln < 5; ln++) {
+		off = 0x0300 + (ln * 0x40);
+		for (i = 0; i < 9; i++) {
+			offset = i + (ln * 9);
+			writel(pd->laneCfg[offset], MIPI_DSI_BASE + off);
+			dmb();
+			off += 4;
+		}
+	}
+
+	/* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */
+	writel(0x7f, MIPI_DSI_BASE + 0x0470);
+
+	/* DSI_0_PHY_DSIPHY_GLBL_TEST_CTRL */
+	writel(0x01, MIPI_DSI_BASE + 0x04d4);
+	dmb();
+
+	off = 0x04b4;	/* phy BIST ctrl 0 - 5 */
+	for (i = 0; i < 6; i++) {
+		writel(pd->bistCtrl[i], MIPI_DSI_BASE + off);
+		off += 4;
+	}
+	dmb();
+
+	/* DSI_0_CLKOUT_TIMING_CTRL */
+	writel(0x41b, MIPI_DSI_BASE + 0x0c4);
+	dmb();
+
+}
diff --git a/platform/msm_shared/partition_parser.c b/platform/msm_shared/partition_parser.c
index b607f3b..cd11632 100644
--- a/platform/msm_shared/partition_parser.c
+++ b/platform/msm_shared/partition_parser.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
 
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -9,7 +9,7 @@
  *     copyright notice, this list of conditions and the following
  *     disclaimer in the documentation and/or other materials provided
  *     with the distribution.
- *   * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *   * Neither the name of The Linux Foundation. nor the names of its
  *     contributors may be used to endorse or promote products derived
  *     from this software without specific prior written permission.
  *
@@ -255,7 +255,7 @@
 	}
 	partition_0 = GET_LLWORD_FROM_BYTE(&data[PARTITION_ENTRIES_OFFSET]);
 	/* Read GPT Entries */
-	for (i = 0; i < (max_partition_count / 4); i++) {
+	for (i = 0; i < ROUNDUP(max_partition_count, 4); i++) {
 		ASSERT(partition_count < NUM_PARTITIONS);
 		ret = mmc_boot_read_from_card(mmc_host, mmc_card,
 					      (partition_0 * BLOCK_SIZE) +
@@ -276,7 +276,7 @@
 			    0x00
 			    && partition_entries[partition_count].
 			    type_guid[1] == 0x00) {
-				i = max_partition_count;
+				i = ROUNDUP(max_partition_count, 4);
 				break;
 			}
 			memcpy(&
diff --git a/platform/msm_shared/qpic_nand.c b/platform/msm_shared/qpic_nand.c
index fb14720..1a34a0c 100644
--- a/platform/msm_shared/qpic_nand.c
+++ b/platform/msm_shared/qpic_nand.c
@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2008, Google Inc.
  * All rights reserved.
- * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
@@ -1553,7 +1553,7 @@
 	{
 		if (count == 0)
 		{
-			dprintf(INFO, "flash_read_image: success (%d errors)\n",
+			dprintf(SPEW, "flash_read_image: success (%d errors)\n",
 					errors);
 			return NANDC_RESULT_SUCCESS;
 		}
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index 13bc253..6a226bd 100644
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -69,6 +69,11 @@
 			$(LOCAL_DIR)/clock_lib2.o \
 			$(LOCAL_DIR)/uart_dm.o \
 			$(LOCAL_DIR)/board.o \
+			$(LOCAL_DIR)/scm.o \
+			$(LOCAL_DIR)/mdp5.o \
+			$(LOCAL_DIR)/display.o \
+			$(LOCAL_DIR)/mipi_dsi.o \
+			$(LOCAL_DIR)/mipi_dsi_phy.o \
 			$(LOCAL_DIR)/spmi.o \
 			$(LOCAL_DIR)/bam.o \
 			$(LOCAL_DIR)/qpic_nand.o \
@@ -81,6 +86,22 @@
 			$(LOCAL_DIR)/i2c_qup.o
 endif
 
+ifeq ($(PLATFORM),msm8226)
+	OBJS += $(LOCAL_DIR)/qgic.o \
+			$(LOCAL_DIR)/qtimer.o \
+			$(LOCAL_DIR)/qtimer_mmap.o \
+			$(LOCAL_DIR)/interrupts.o \
+			$(LOCAL_DIR)/clock.o \
+			$(LOCAL_DIR)/clock_pll.o \
+			$(LOCAL_DIR)/clock_lib2.o \
+			$(LOCAL_DIR)/uart_dm.o \
+			$(LOCAL_DIR)/board.o \
+			$(LOCAL_DIR)/spmi.o \
+			$(LOCAL_DIR)/bam.o \
+			$(LOCAL_DIR)/qpic_nand.o \
+			$(LOCAL_DIR)/dev_tree.o
+endif
+
 ifeq ($(PLATFORM),msm7x27a)
 	OBJS += $(LOCAL_DIR)/uart.o \
 			$(LOCAL_DIR)/nand.o \
diff --git a/platform/msm_shared/scm.c b/platform/msm_shared/scm.c
index 00b48b0..7edcc2b 100644
--- a/platform/msm_shared/scm.c
+++ b/platform/msm_shared/scm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -182,6 +182,27 @@
 	return ret;
 }
 
+int restore_secure_cfg(uint32_t id)
+{
+	int ret, scm_ret = 0;
+	tz_secure_cfg secure_cfg;
+
+	secure_cfg.id    = 1;
+	secure_cfg.spare = 0;
+
+	ret = scm_call(SCM_SVC_SSD, IOMMU_SECURE_CFG, &secure_cfg, sizeof(secure_cfg),
+			&scm_ret, sizeof(scm_ret));
+
+	if (ret || scm_ret) {
+		dprintf(CRITICAL, "Secure Config failed\n");
+		ret = 1;
+	} else
+		ret = 0;
+
+	return ret;
+
+}
+
 /* SCM Encrypt Command */
 int encrypt_scm(uint32_t ** img_ptr, uint32_t * img_len_ptr)
 {
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index 846ebf5..2920ba9 100755
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -266,6 +266,7 @@
 	HW_PLATFORM_RUMI   = 15,
 	HW_PLATFORM_VIRTIO = 16,
 	HW_PLATFORM_BTS = 19,
+	HW_PLATFORM_DMA = 22,
 	HW_PLATFORM_32BITS = 0x7FFFFFFF,
 };
 
diff --git a/project/msm8226.mk b/project/msm8226.mk
new file mode 100644
index 0000000..0ba5aaa
--- /dev/null
+++ b/project/msm8226.mk
@@ -0,0 +1,16 @@
+# top level project rules for the msm8226 project
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+TARGET := msm8226
+
+MODULES += app/aboot
+
+DEBUG := 1
+
+#DEFINES += WITH_DEBUG_DCC=1
+DEFINES += WITH_DEBUG_UART=1
+#DEFINES += WITH_DEBUG_FBCON=1
+DEFINES += DEVICE_TREE=1
+#DEFINES += MMC_BOOT_BAM=1
+#DEFINES += CRYPTO_BAM=1
diff --git a/target/copper/include/target/display.h b/target/copper/include/target/display.h
new file mode 100644
index 0000000..0687d24
--- /dev/null
+++ b/target/copper/include/target/display.h
@@ -0,0 +1,45 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef _TARGET_COPPER_DISPLAY_H
+#define _TARGET_COPPER_DISPLAY_H
+
+#define MIPI_FB_ADDR  0x08400000
+
+#define MIPI_HSYNC_PULSE_WIDTH       12
+#define MIPI_HSYNC_BACK_PORCH_DCLK   32
+#define MIPI_HSYNC_FRONT_PORCH_DCLK  144
+
+#define MIPI_VSYNC_PULSE_WIDTH       4
+#define MIPI_VSYNC_BACK_PORCH_LINES  3
+#define MIPI_VSYNC_FRONT_PORCH_LINES 9
+
+extern int mdss_dsi_phy_init(struct mipi_dsi_panel_config *);
+extern int mdss_dsi_uniphy_pll_config(void);
+
+#endif
diff --git a/target/copper/init.c b/target/copper/init.c
index 2a2d098..e60fbb7 100644
--- a/target/copper/init.c
+++ b/target/copper/init.c
@@ -95,9 +95,13 @@
 }
 
 /* Return 1 if vol_down pressed */
-int target_volume_down()
+uint32_t target_volume_down()
 {
-	return pm8x41_vol_down_key_status();
+	/* Volume down button is tied in with RESIN on MSM8974. */
+	if (pm8x41_get_pmic_rev() == PMIC_VERSION_V2)
+		return pm8x41_resin_bark_workaround_status();
+	else
+		return pm8x41_resin_status();
 }
 
 static void target_keystatus()
@@ -152,6 +156,12 @@
 
 	if (target_use_signed_kernel())
 		target_crypto_init_params();
+	/* Display splash screen if enabled */
+#if DISPLAY_SPLASH_SCREEN
+	dprintf(INFO, "Display Init: Start\n");
+	display_init();
+	dprintf(INFO, "Display Init: Done\n");
+#endif
 
 	/* Trying Slot 1*/
 	slot = 1;
@@ -243,3 +253,15 @@
 
 	dprintf(CRITICAL, "Rebooting failed\n");
 }
+
+/* Returns 1 if target supports continuous splash screen. */
+int target_cont_splash_screen()
+{
+	switch(board_platform_id())
+	{
+	case HW_PLATFORM_SURF:
+	case HW_PLATFORM_FFA:
+	default:
+		return 0;
+	}
+}
diff --git a/target/copper/rules.mk b/target/copper/rules.mk
index 73eb416..0d35f49 100644
--- a/target/copper/rules.mk
+++ b/target/copper/rules.mk
@@ -14,10 +14,15 @@
 RAMDISK_ADDR     := BASE_ADDR+0x01000000
 SCRATCH_ADDR     := 0x11000000
 
+DEFINES += DISPLAY_SPLASH_SCREEN=1
+DEFINES += DISPLAY_TYPE_MIPI=1
+DEFINES += DISPLAY_TYPE_DSI6G=1
+
 MODULES += \
 	dev/keys \
-    lib/ptable \
 	dev/pmic/pm8x41 \
+	dev/panel/msm \
+    lib/ptable \
     lib/libfdt
 
 DEFINES += \
@@ -32,4 +37,5 @@
 
 OBJS += \
     $(LOCAL_DIR)/init.o \
-    $(LOCAL_DIR)/meminfo.o
+    $(LOCAL_DIR)/meminfo.o \
+    $(LOCAL_DIR)/target_display.o
diff --git a/target/copper/target_display.c b/target/copper/target_display.c
new file mode 100644
index 0000000..1f09bb1
--- /dev/null
+++ b/target/copper/target_display.c
@@ -0,0 +1,168 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  * Neither the name of The Linux Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <smem.h>
+#include <msm_panel.h>
+#include <pm8x41.h>
+#include <pm8x41_wled.h>
+#include <board.h>
+#include <mdp5.h>
+#include <platform/gpio.h>
+#include <target/display.h>
+
+static struct msm_fb_panel_data panel;
+static uint8_t display_enable;
+
+extern int msm_display_init(struct msm_fb_panel_data *pdata);
+extern int msm_display_off();
+extern int mdss_dsi_uniphy_pll_config(void);
+
+static int msm8974_backlight_on()
+{
+	static struct pm8x41_wled_data wled_ctrl = {
+		.mod_scheme      = 0xC3,
+		.led1_brightness = (0x0F << 8) | 0xEF,
+		.led2_brightness = (0x0F << 8) | 0xEF,
+		.led3_brightness = (0x0F << 8) | 0xEF,
+		.max_duty_cycle  = 0x01,
+	};
+
+	pm8x41_wled_config(&wled_ctrl);
+	pm8x41_wled_sink_control(1);
+	pm8x41_wled_iled_sync_control(1);
+	pm8x41_wled_enable(1);
+
+	return 0;
+}
+
+static int msm8974_mdss_dsi_panel_clock(uint8_t enable)
+{
+	if (enable) {
+		mdp_gdsc_ctrl(enable);
+		mdp_clock_init();
+		mdss_dsi_uniphy_pll_config();
+		mmss_clock_init();
+	} else if(!target_cont_splash_screen()) {
+		// * Add here for continuous splash  *
+	}
+
+	return 0;
+}
+
+/* Pull DISP_RST_N high to get panel out of reset */
+static void msm8974_mdss_mipi_panel_reset(void)
+{
+	struct pm8x41_gpio gpio19_param = {
+		.direction = PM_GPIO_DIR_OUT,
+		.output_buffer = PM_GPIO_OUT_CMOS,
+		.out_strength = PM_GPIO_OUT_DRIVE_MED,
+	};
+
+	pm8x41_gpio_config(19, &gpio19_param);
+	gpio_tlmm_config(58, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
+
+	pm8x41_gpio_set(19, PM_GPIO_FUNC_HIGH);
+	mdelay(2);
+	pm8x41_gpio_set(19, PM_GPIO_FUNC_LOW);
+	mdelay(5);
+	pm8x41_gpio_set(19, PM_GPIO_FUNC_HIGH);
+	mdelay(2);
+	gpio_set(58, 2);
+}
+
+
+static int msm8974_mipi_panel_power(uint8_t enable)
+{
+	if (enable) {
+
+		/* Enable backlight */
+		msm8974_backlight_on();
+
+		/* Turn on LDO8 for lcd1 mipi vdd */
+		dprintf(SPEW, " Setting LDO22\n");
+		pm8x41_ldo_set_voltage("LDO22", 3000000);
+		pm8x41_ldo_control("LDO22", enable);
+
+		dprintf(SPEW, " Setting LDO12\n");
+		/* Turn on LDO23 for lcd1 mipi vddio */
+		pm8x41_ldo_set_voltage("LDO12", 1800000);
+		pm8x41_ldo_control("LDO12", enable);
+
+		dprintf(SPEW, " Setting LDO2\n");
+		/* Turn on LDO2 for vdda_mipi_dsi */
+		pm8x41_ldo_set_voltage("LDO2", 1200000);
+		pm8x41_ldo_control("LDO2", enable);
+
+		dprintf(SPEW, " Panel Reset \n");
+		/* Panel Reset */
+		msm8974_mdss_mipi_panel_reset();
+		dprintf(SPEW, " Panel Reset Done\n");
+	}
+
+	return 0;
+}
+
+void display_init(void)
+{
+	uint32_t hw_id = board_hardware_id();
+
+	dprintf(INFO, "display_init(),target_id=%d.\n", hw_id);
+
+	switch (hw_id) {
+	case HW_PLATFORM_MTP:
+	case HW_PLATFORM_FLUID:
+		mipi_toshiba_video_720p_init(&(panel.panel_info));
+		panel.clk_func = msm8974_mdss_dsi_panel_clock;
+		panel.power_func = msm8974_mipi_panel_power;
+		panel.fb.base = MIPI_FB_ADDR;
+		panel.fb.width =  panel.panel_info.xres;
+		panel.fb.height =  panel.panel_info.yres;
+		panel.fb.stride =  panel.panel_info.xres;
+		panel.fb.bpp =  panel.panel_info.bpp;
+		panel.fb.format = FB_FORMAT_RGB888;
+		panel.mdp_rev = MDP_REV_50;
+		break;
+	default:
+		return;
+	};
+
+	if (msm_display_init(&panel)) {
+		dprintf(CRITICAL, "Display init failed!\n");
+		return;
+	}
+
+	display_enable = 1;
+}
+
+void display_shutdown(void)
+{
+	if (display_enable)
+		msm_display_off();
+}
diff --git a/target/mdm9625/init.c b/target/mdm9625/init.c
index e17f796..407e3c7 100644
--- a/target/mdm9625/init.c
+++ b/target/mdm9625/init.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -143,8 +143,13 @@
 /* reboot */
 void reboot_device(unsigned reboot_reason)
 {
+	uint32_t version = board_soc_version();
+
 	/* Write the reboot reason */
-	writel(reboot_reason, RESTART_REASON_ADDR);
+	if(version >= 0x20000)
+		writel(reboot_reason, RESTART_REASON_ADDR_V2);
+	else
+		writel(reboot_reason, RESTART_REASON_ADDR);
 
 	/* Configure PMIC for warm reset */
 	pm8x41_reset_configure(PON_PSHOLD_WARM_RESET);
@@ -189,10 +194,17 @@
 unsigned check_reboot_mode(void)
 {
 	unsigned restart_reason = 0;
+	uint32_t version = board_soc_version();
 
 	/* Read reboot reason and scrub it */
-	restart_reason = readl(RESTART_REASON_ADDR);
-	writel(0x00, RESTART_REASON_ADDR);
+	if(version >= 0x20000) {
+		restart_reason = readl(RESTART_REASON_ADDR_V2);
+		writel(0x00, RESTART_REASON_ADDR_V2);
+	}
+	else {
+		restart_reason = readl(RESTART_REASON_ADDR);
+		writel(0x00, RESTART_REASON_ADDR);
+	}
 
 	return restart_reason;
 }
diff --git a/target/msm8226/init.c b/target/msm8226/init.c
new file mode 100644
index 0000000..758df28
--- /dev/null
+++ b/target/msm8226/init.c
@@ -0,0 +1,94 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <platform/iomap.h>
+#include <reg.h>
+#include <target.h>
+#include <platform.h>
+#include <uart_dm.h>
+#include <mmc.h>
+#include <spmi.h>
+#include <board.h>
+
+#define PMIC_ARB_CHANNEL_NUM    0
+#define PMIC_ARB_OWNER_ID       0
+
+static uint32_t mmc_sdc_base[] =
+	{ MSM_SDC1_BASE, MSM_SDC2_BASE, MSM_SDC3_BASE, MSM_SDC4_BASE };
+
+void target_early_init(void)
+{
+#if WITH_DEBUG_UART
+	uart_dm_init(1, 0, BLSP1_UART2_BASE);
+#endif
+}
+
+static void target_keystatus()
+{
+}
+
+void target_init(void)
+{
+	uint32_t base_addr;
+	uint8_t slot;
+
+	dprintf(INFO, "target_init()\n");
+
+	spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
+
+	target_keystatus();
+
+	/* Trying Slot 1*/
+	slot = 1;
+	base_addr = mmc_sdc_base[slot - 1];
+	if (mmc_boot_main(slot, base_addr))
+	{
+
+		/* Trying Slot 2 next */
+		slot = 2;
+		base_addr = mmc_sdc_base[slot - 1];
+		if (mmc_boot_main(slot, base_addr)) {
+			dprintf(CRITICAL, "mmc init failed!");
+			ASSERT(0);
+		}
+	}
+}
+
+void target_serialno(unsigned char *buf)
+{
+	uint32_t serialno;
+	if (target_is_emmc_boot()) {
+		serialno = mmc_get_psn();
+		snprintf((char *)buf, 13, "%x", serialno);
+	}
+}
+
+unsigned board_machtype(void)
+{
+}
diff --git a/target/msm8226/meminfo.c b/target/msm8226/meminfo.c
new file mode 100644
index 0000000..e5a53d2
--- /dev/null
+++ b/target/msm8226/meminfo.c
@@ -0,0 +1,86 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <reg.h>
+#include <debug.h>
+#include <malloc.h>
+#include <smem.h>
+#include <stdint.h>
+#include <libfdt.h>
+#include <platform/iomap.h>
+#include <dev_tree.h>
+
+/* Funtion to add the ram partition entries into device tree.
+ * The function assumes that all the entire fixed memory regions should
+ * be listed in the first bank of the passed in ddr regions.
+ */
+uint32_t target_dev_tree_mem(void *fdt, uint32_t memory_node_offset)
+{
+    struct smem_ram_ptable ram_ptable;
+    uint32_t i;
+	int ret = 0;
+
+	/* Make sure RAM partition table is initialized */
+	ASSERT(smem_ram_ptable_init(&ram_ptable));
+
+     /* Calculating the size of the mem_info_ptr */
+    for (i = 0 ; i < ram_ptable.len; i++)
+    {
+        if((ram_ptable.parts[i].category == SDRAM) &&
+           (ram_ptable.parts[i].type == SYS_MEMORY))
+        {
+
+			/* Pass along all other usable memory regions to Linux */
+			ret = dev_tree_add_mem_info(fdt,
+										memory_node_offset,
+										ram_ptable.parts[i].start,
+										ram_ptable.parts[i].size);
+
+			if (ret)
+			{
+				dprintf(CRITICAL, "Failed to add secondary banks memory addresses\n");
+				goto target_dev_tree_mem_err;
+			}
+
+       }
+    }
+
+target_dev_tree_mem_err:
+
+    return ret;
+}
+
+void *target_get_scratch_address(void)
+{
+	return ((void *)SCRATCH_ADDR);
+}
+
+unsigned target_get_max_flash_size(void)
+{
+	return (512 * 1024 * 1024);
+}
diff --git a/target/msm8226/rules.mk b/target/msm8226/rules.mk
new file mode 100644
index 0000000..cdd9a35
--- /dev/null
+++ b/target/msm8226/rules.mk
@@ -0,0 +1,35 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+
+PLATFORM := msm8226
+
+MEMBASE := 0x0FF00000 # SDRAM
+MEMSIZE := 0x00100000 # 1MB
+
+BASE_ADDR        := 0x00000
+
+TAGS_ADDR        := BASE_ADDR+0x00000100
+KERNEL_ADDR      := BASE_ADDR+0x00008000
+RAMDISK_ADDR     := BASE_ADDR+0x01000000
+SCRATCH_ADDR     := 0x10000000
+
+MODULES += \
+	dev/keys \
+	lib/ptable \
+	dev/pmic/pm8x41 \
+	lib/libfdt
+
+DEFINES += \
+	MEMSIZE=$(MEMSIZE) \
+	MEMBASE=$(MEMBASE) \
+	BASE_ADDR=$(BASE_ADDR) \
+	TAGS_ADDR=$(TAGS_ADDR) \
+	KERNEL_ADDR=$(KERNEL_ADDR) \
+	RAMDISK_ADDR=$(RAMDISK_ADDR) \
+	SCRATCH_ADDR=$(SCRATCH_ADDR)
+
+
+OBJS += \
+    $(LOCAL_DIR)/init.o \
+    $(LOCAL_DIR)/meminfo.o
diff --git a/target/msm8226/tools/makefile b/target/msm8226/tools/makefile
new file mode 100644
index 0000000..2757e07
--- /dev/null
+++ b/target/msm8226/tools/makefile
@@ -0,0 +1,44 @@
+#Makefile to generate appsboot.mbn
+
+ifeq ($(BOOTLOADER_OUT),.)
+APPSBOOTHEADER_DIR  := $(BUILDDIR)
+else
+APPSBOOTHEADER_DIR  := $(BOOTLOADER_OUT)/../..
+endif
+
+SRC_DIR  := target/$(TARGET)/tools
+COMPILER := gcc
+
+ifeq ($(EMMC_BOOT), 1)
+  APPSBOOTHDR_FILES := EMMCBOOT.MBN
+else
+  ifeq ($(BUILD_NANDWRITE), 1)
+    APPSBOOTHDR_FILES :=
+  else
+    APPSBOOTHDR_FILES := appsboot.mbn
+  endif
+endif
+
+APPSBOOTHEADER: $(APPSBOOTHDR_FILES)
+
+
+appsboot.mbn: appsboothd.mbn $(OUTBIN)
+	cp $(OUTBIN) $(APPSBOOTHEADER_DIR)/appsboot.raw
+	cat $(APPSBOOTHEADER_DIR)/appsboothd.mbn $(OUTBIN) > $(APPSBOOTHEADER_DIR)/appsboot.mbn
+	rm -f $(APPSBOOTHEADER_DIR)/appsboothd.mbn
+
+appsboothd.mbn: mkheader $(OUTBIN)
+	$(BUILDDIR)/mkheader $(OUTBIN) $(APPSBOOTHEADER_DIR)/appsboothd.mbn
+
+EMMCBOOT.MBN: emmc_appsboothd.mbn $(OUTBIN)
+	cp $(OUTBIN) $(APPSBOOTHEADER_DIR)/emmc_appsboot.raw
+	cat $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn $(OUTBIN) > $(APPSBOOTHEADER_DIR)/EMMCBOOT.MBN
+	cat $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn $(OUTBIN) > $(APPSBOOTHEADER_DIR)/emmc_appsboot.mbn
+	rm -f $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn
+
+emmc_appsboothd.mbn: mkheader $(OUTBIN)
+	$(BUILDDIR)/mkheader $(OUTBIN) $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn
+
+mkheader: $(SRC_DIR)/mkheader.c
+	@mkdir -p $(BUILDDIR)
+	${COMPILER} -DMEMBASE=$(MEMBASE) $(SRC_DIR)/mkheader.c -o $(BUILDDIR)/mkheader
diff --git a/target/msm8226/tools/mkheader.c b/target/msm8226/tools/mkheader.c
new file mode 100644
index 0000000..7b27dbb
--- /dev/null
+++ b/target/msm8226/tools/mkheader.c
@@ -0,0 +1,343 @@
+/*
+ * Copyright (c) 2007, Google Inc.
+ * All rights reserved.
+ *
+ * Copyright (c) 2009-2011, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *      disclaimer in the documentation and/or other materials provided
+ *      with the distribution.
+ *    * Neither the name of The Linux Foundation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <string.h>
+
+#include <sys/stat.h>
+
+int print_usage()
+{
+	fprintf(stderr, "usage: mkheader <bin> <hdr> <none|unified-boot>\n");
+	fprintf(stderr, "       mkheader <bin> <hdr> <unsecure-boot>"
+		" <outbin>\n");
+	fprintf(stderr, "       mkheader <bin> <hdr> <secure-boot> <outbin>"
+		" <maxsize>\n");
+	fprintf(stderr, "       mkheader <bin> <hdr> <secure-boot> <outbin>"
+		" <maxsize> <certchain> <files...>\n\n");
+	fprintf(stderr, "bin:               Input raw appsbl binary\n");
+	fprintf(stderr,
+		"hdr:               Output of appsbl header location\n");
+	fprintf(stderr,
+		"outbin:            Output of the signed or unsigned"
+		" apps boot location\n");
+	fprintf(stderr,
+		"maxsize:           Maximum size for certificate" " chain\n");
+	fprintf(stderr,
+		"certchain:         Output of the certchain location\n");
+	fprintf(stderr,
+		"files:             Input format <bin signature>"
+		" <certifcate file(s) for certificate chain>...\n");
+	fprintf(stderr,
+		"certificate chain: Files will be concatenated in order"
+		" to create the certificate chain\n\n");
+	return -1;
+}
+
+int cat(FILE * in, FILE * out, unsigned size, unsigned buff_size)
+{
+	unsigned bytes_left = size;
+	char buf[buff_size];
+	int ret = 0;
+
+	while (bytes_left) {
+		fread(buf, sizeof(char), buff_size, in);
+		if (!feof(in)) {
+			bytes_left -= fwrite(buf, sizeof(char), buff_size, out);
+		} else
+			bytes_left = 0;
+	}
+	ret = ferror(in) | ferror(out);
+	if (ret)
+		fprintf(stderr, "ERROR: Occured during file concatenation\n");
+	return ret;
+}
+
+int main(int argc, char *argv[])
+{
+	struct stat s;
+	unsigned size, base;
+	int unified_boot = 0;
+	unsigned unified_boot_magic[20];
+	unsigned non_unified_boot_magic[10];
+	unsigned magic_len = 0;
+	unsigned *magic;
+	unsigned cert_chain_size = 0;
+	unsigned signature_size = 0;
+	int secure_boot = 0;
+	int fd;
+
+	if (argc < 3) {
+		return print_usage();
+	}
+
+	if (argc == 4) {
+		if (!strcmp("unified-boot", argv[3])) {
+			unified_boot = 1;
+		} else if (!strcmp("secure-boot", argv[3])) {
+			fprintf(stderr,
+				"ERROR: Missing arguments: [outbin maxsize] |"
+				" [outbin, maxsize, certchain,"
+				" signature + certifcate(s)]\n");
+			return print_usage();
+		} else if (!strcmp("unsecure-boot", argv[3])) {
+			fprintf(stderr, "ERROR: Missing arguments:"
+				" outbin directory\n");
+			return print_usage();
+		}
+	}
+
+	if (argc > 4) {
+		if (!strcmp("secure-boot", argv[3])) {
+			if (argc < 9 && argc != 6) {
+				fprintf(stderr,
+					"ERROR: Missing argument(s):"
+					" [outbin maxsize] | [outbin, maxsize,"
+					" certchain,"
+					" signature + certifcate(s)]\n");
+				return print_usage();
+			}
+			secure_boot = 1;
+			signature_size = 256;	//Support SHA 256
+			cert_chain_size = atoi(argv[5]);
+		}
+	}
+
+	if (stat(argv[1], &s)) {
+		perror("cannot stat binary");
+		return -1;
+	}
+
+	if (unified_boot) {
+		magic = unified_boot_magic;
+		magic_len = sizeof(unified_boot_magic);
+	} else {
+		magic = non_unified_boot_magic;
+		magic_len = sizeof(non_unified_boot_magic);
+	}
+
+	size = s.st_size;
+#if MEMBASE
+	base = MEMBASE;
+#else
+	base = 0;
+#endif
+
+	printf("Image Destination Pointer: 0x%x\n", base);
+
+	magic[0] = 0x00000005;	/* appsbl */
+	magic[1] = 0x00000003;	//Flash_partition_version /* nand */
+	magic[2] = 0x00000000;	//image source pointer
+	magic[3] = base;	//image destination pointer
+	magic[4] = size + cert_chain_size + signature_size;	//image size
+	magic[5] = size;	//code size
+	magic[6] = base + size;
+	magic[7] = signature_size;
+	magic[8] = size + base + signature_size;
+	magic[9] = cert_chain_size;
+
+	if (unified_boot == 1) {
+		magic[10] = 0x33836685;	/* cookie magic number */
+		magic[11] = 0x00000001;	/* cookie version */
+		magic[12] = 0x00000002;	/* file formats */
+		magic[13] = 0x00000000;
+		magic[14] = 0x00000000;	/* not setting size for boot.img */
+		magic[15] = 0x00000000;
+		magic[16] = 0x00000000;
+		magic[17] = 0x00000000;
+		magic[18] = 0x00000000;
+		magic[19] = 0x00000000;
+	}
+
+	fd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, 0644);
+	if (fd < 0) {
+		perror("cannot open header for writing");
+		return -1;
+	}
+	if (write(fd, magic, magic_len) != magic_len) {
+		perror("cannot write header");
+		close(fd);
+		unlink(argv[2]);
+		return -1;
+	}
+	close(fd);
+
+	if (secure_boot && argc > 6) {
+		FILE *input_file;
+		FILE *output_file;
+		unsigned buff_size = 1;
+		char buf[buff_size];
+		unsigned bytes_left;
+		unsigned current_cert_chain_size = 0;
+		int padding_size = 0;
+		int i;
+
+		if ((output_file = fopen(argv[6], "wb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		printf("Certificate Chain Output File: %s\n", argv[6]);
+
+		for (i = 8; i < argc; i++) {
+			if ((input_file = fopen(argv[i], "rb")) == NULL) {
+				perror("ERROR: Occured during fopen");
+				return -1;
+			}
+			stat(argv[i], &s);
+			bytes_left = s.st_size;
+			current_cert_chain_size += bytes_left;
+			if (cat(input_file, output_file, bytes_left, buff_size))
+				return -1;
+			fclose(input_file);
+		}
+
+		//Pad certifcate chain to the max expected size from input
+		memset(buf, 0xFF, sizeof(buf));
+		padding_size = cert_chain_size - current_cert_chain_size;
+
+		if (padding_size < 0) {
+			fprintf(stderr, "ERROR: Input certificate chain"
+				" (Size=%d) is larger than the maximum"
+				" specified (Size=%d)\n",
+				current_cert_chain_size, cert_chain_size);
+			return -1;
+		}
+
+		bytes_left = (padding_size > 0) ? padding_size : 0;
+		while (bytes_left) {
+			if (!ferror(output_file))
+				bytes_left -= fwrite(buf,
+						     sizeof(buf),
+						     buff_size, output_file);
+			else {
+				fprintf(stderr, "ERROR: Occured during"
+					" certifcate chain padding\n");
+				return -1;
+			}
+		}
+		fclose(output_file);
+
+		/* Concat and combine to signed image.
+		 * Format [HDR][RAW APPSBOOT][PADDED CERT CHAIN]
+		 */
+		if ((output_file = fopen(argv[4], "wb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		printf("Image Output File: %s\n", argv[4]);
+
+		//Header
+		if ((input_file = fopen(argv[2], "rb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		stat(argv[2], &s);
+		if (cat(input_file, output_file, s.st_size, buff_size))
+			return -1;
+		fclose(input_file);
+
+		//Raw Appsbl
+		if ((input_file = fopen(argv[1], "rb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		stat(argv[1], &s);
+		if (cat(input_file, output_file, s.st_size, buff_size))
+			return -1;
+		fclose(input_file);
+
+		//Signature
+		if ((input_file = fopen(argv[7], "rb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		stat(argv[7], &s);
+		if (cat(input_file, output_file, s.st_size, buff_size))
+			return -1;
+		fclose(input_file);
+
+		//Certifcate Chain
+		if ((input_file = fopen(argv[6], "rb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		if (cat(input_file, output_file,
+			(current_cert_chain_size + padding_size), buff_size))
+			return -1;
+		fclose(input_file);
+
+		fclose(output_file);
+
+	} else if (argc == 5 || argc == 6) {
+		FILE *input_file;
+		FILE *output_file;
+		unsigned buff_size = 1;
+		char buf[buff_size];
+
+		/* Concat and combine to unsigned image.
+		 * Format [HDR][RAW APPSBOOT]
+		 */
+		if ((output_file = fopen(argv[4], "wb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		printf("Image Output File: %s\n", argv[4]);
+
+		//Header
+		if ((input_file = fopen(argv[2], "rb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		stat(argv[2], &s);
+		if (cat(input_file, output_file, s.st_size, buff_size))
+			return -1;
+		fclose(input_file);
+
+		//Raw Appsbl
+		if ((input_file = fopen(argv[1], "rb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		stat(argv[1], &s);
+		if (cat(input_file, output_file, s.st_size, buff_size))
+			return -1;
+		fclose(input_file);
+		fclose(output_file);
+	}
+
+	printf("Done execution\n");
+
+	return 0;
+}
diff --git a/target/msm8960/include/target/board.h b/target/msm8960/include/target/board.h
index 1e2606a..9a6f150 100644
--- a/target/msm8960/include/target/board.h
+++ b/target/msm8960/include/target/board.h
@@ -60,5 +60,6 @@
 #define LINUX_MACHTYPE_8064_MPQ_HRD 3994
 #define LINUX_MACHTYPE_8064_MPQ_DTV 3995
 #define LINUX_MACHTYPE_8064_EP      3996
+#define LINUX_MACHTYPE_8064_MPQ_DMA 4511
 
 #endif
diff --git a/target/msm8960/init.c b/target/msm8960/init.c
index 912983b..cf57250 100755
--- a/target/msm8960/init.c
+++ b/target/msm8960/init.c
@@ -308,6 +308,7 @@
 	case LINUX_MACHTYPE_8064_MPQ_CDP:
 	case LINUX_MACHTYPE_8064_MPQ_HRD:
 	case LINUX_MACHTYPE_8064_MPQ_DTV:
+	case LINUX_MACHTYPE_8064_MPQ_DMA:
 		uart_dm_init(5, 0x1A200000, 0x1A240000);
 		break;
 
@@ -397,6 +398,9 @@
 		case HW_PLATFORM_DTV:
 			target_id = LINUX_MACHTYPE_8064_MPQ_DTV;
 			break;
+		case HW_PLATFORM_DMA:
+			target_id = LINUX_MACHTYPE_8064_MPQ_DMA;
+			break;
 		default:
 			target_id = LINUX_MACHTYPE_8064_MPQ_CDP;
 		}