platform: apq8084: Support display clocks for APQ8084
Add dsi clock, mdp clock, bus clock and gdsc clock
enable/disable API for APQ8084 target. It also updates
the APQ8084 display IO mapping.
Change-Id: Ifa746110fb1dcfb8dbad958a8370a54be2293f91
diff --git a/platform/apq8084/apq8084-clock.c b/platform/apq8084/apq8084-clock.c
index a353a15..37e6323 100644
--- a/platform/apq8084/apq8084-clock.c
+++ b/platform/apq8084/apq8084-clock.c
@@ -329,6 +329,194 @@
},
};
+/* Display clocks */
+static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = {
+ F_MM(19200000, cxo, 1, 0, 0),
+ F_END
+};
+
+static struct clk_freq_tbl ftbl_mdss_esc1_1_clk[] = {
+ F_MM(19200000, cxo, 1, 0, 0),
+ F_END
+};
+
+static struct clk_freq_tbl ftbl_mmss_axi_clk[] = {
+ F_MM(19200000, cxo, 1, 0, 0),
+ F_MM(100000000, gpll0, 6, 0, 0),
+ F_END
+};
+
+static struct clk_freq_tbl ftbl_mdp_clk[] = {
+ F_MM( 75000000, gpll0, 8, 0, 0),
+ F_MM( 240000000, gpll0, 2.5, 0, 0),
+ F_END
+};
+
+static struct rcg_clk dsi_esc0_clk_src = {
+ .cmd_reg = (uint32_t *) DSI_ESC0_CMD_RCGR,
+ .cfg_reg = (uint32_t *) DSI_ESC0_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_esc0_1_clk,
+
+ .c = {
+ .dbg_name = "dsi_esc0_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct rcg_clk dsi_esc1_clk_src = {
+ .cmd_reg = (uint32_t *) DSI_ESC1_CMD_RCGR,
+ .cfg_reg = (uint32_t *) DSI_ESC1_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_esc1_1_clk,
+
+ .c = {
+ .dbg_name = "dsi_esc1_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = {
+ F_MM(19200000, cxo, 1, 0, 0),
+ F_END
+};
+
+static struct rcg_clk vsync_clk_src = {
+ .cmd_reg = (uint32_t *) VSYNC_CMD_RCGR,
+ .cfg_reg = (uint32_t *) VSYNC_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_vsync_clk,
+
+ .c = {
+ .dbg_name = "vsync_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct rcg_clk mdp_axi_clk_src = {
+ .cmd_reg = (uint32_t *) MDP_AXI_CMD_RCGR,
+ .cfg_reg = (uint32_t *) MDP_AXI_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mmss_axi_clk,
+
+ .c = {
+ .dbg_name = "mdp_axi_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk mdss_esc0_clk = {
+ .cbcr_reg = (uint32_t *) DSI_ESC0_CBCR,
+ .parent = &dsi_esc0_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mdss_esc0_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mdss_esc1_clk = {
+ .cbcr_reg = (uint32_t *) DSI_ESC1_CBCR,
+ .parent = &dsi_esc1_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mdss_esc1_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mdss_axi_clk = {
+ .cbcr_reg = (uint32_t *) MDP_AXI_CBCR,
+ .parent = &mdp_axi_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mdss_axi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mmss_mmssnoc_axi_clk = {
+ .cbcr_reg = (uint32_t *) MMSS_MMSSNOC_AXI_CBCR,
+ .parent = &mdp_axi_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mmss_mmssnoc_axi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mmss_s0_axi_clk = {
+ .cbcr_reg = (uint32_t *) MMSS_S0_AXI_CBCR,
+ .parent = &mdp_axi_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mmss_s0_axi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mdp_ahb_clk = {
+ .cbcr_reg = (uint32_t *) MDP_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "mdp_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct rcg_clk mdss_mdp_clk_src = {
+ .cmd_reg = (uint32_t *) MDP_CMD_RCGR,
+ .cfg_reg = (uint32_t *) MDP_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdp_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "mdss_mdp_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk mdss_mdp_clk = {
+ .cbcr_reg = (uint32_t *) MDP_CBCR,
+ .parent = &mdss_mdp_clk_src.c,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "mdss_mdp_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mdss_mdp_lut_clk = {
+ .cbcr_reg = MDP_LUT_CBCR,
+ .parent = &mdss_mdp_clk_src.c,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "mdss_mdp_lut_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk mdss_vsync_clk = {
+ .cbcr_reg = MDSS_VSYNC_CBCR,
+ .parent = &vsync_clk_src.c,
+ .has_sibling = 0,
+
+ .c = {
+ .dbg_name = "mdss_vsync_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+
/* Clock lookup table */
static struct clk_lookup msm_clocks_8084[] =
{
@@ -344,6 +532,18 @@
/* USB 3.0 */
CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c),
CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
+
+ /* mdss clocks */
+ CLK_LOOKUP("mdp_ahb_clk", mdp_ahb_clk.c),
+ CLK_LOOKUP("mdss_esc0_clk", mdss_esc0_clk.c),
+ CLK_LOOKUP("mdss_esc1_clk", mdss_esc1_clk.c),
+ CLK_LOOKUP("mdss_axi_clk", mdss_axi_clk.c),
+ CLK_LOOKUP("mmss_mmssnoc_axi_clk", mmss_mmssnoc_axi_clk.c),
+ CLK_LOOKUP("mmss_s0_axi_clk", mmss_s0_axi_clk.c),
+ CLK_LOOKUP("mdss_vsync_clk", mdss_vsync_clk.c),
+ CLK_LOOKUP("mdss_mdp_clk_src", mdss_mdp_clk_src.c),
+ CLK_LOOKUP("mdss_mdp_clk", mdss_mdp_clk.c),
+ CLK_LOOKUP("mdss_mdp_lut_clk", mdss_mdp_lut_clk.c),
};
void platform_clock_init(void)