platform: msm_shared: mdp5: Correct interface base check
For chipsets, where destination split is enabled, the programming
is currently not done properly as interface base address check
is wrong. Interface base address passed to tg_setup function is
sum of INTF_BASE and offset (mdp_set_intf_base), and instead
checking only with INTF_BASE. This is causing boot up issue on
2k panel on 8939. Correct this to fix the issue.
Change-Id: I99271d88cd93710894157eaaedc27441fd701173
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index b48efb7..ffe61e2 100755
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -448,14 +448,14 @@
adjust_xres = pinfo->xres;
if (pinfo->lcdc.split_display) {
adjust_xres /= 2;
- if (intf_base == MDP_INTF_1_BASE) {
+ if (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset())) {
writel(BIT(8), MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL);
writel(BIT(8), MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL);
writel(0x1, MDP_REG_SPLIT_DISPLAY_EN);
}
}
- if (pinfo->lcdc.dst_split && (intf_base == MDP_INTF_1_BASE)) {
+ if (pinfo->lcdc.dst_split && (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset()))) {
uint32_t ppb_offset = mdss_mdp_get_ppb_offset();
writel(BIT(16), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CNTL */
writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CONFIG */
@@ -497,7 +497,7 @@
display_vend = ((vsync_period - itp.v_front_porch) * hsync_period)
+ itp.hsync_skew - 1;
- if (intf_base == MDP_INTF_0_BASE) { /* eDP */
+ if (intf_base == (MDP_INTF_0_BASE + mdss_mdp_intf_offset())) { /* eDP */
display_vstart += itp.hsync_pulse_width + itp.h_back_porch;
display_vend -= itp.h_front_porch;
}