commit 502ed714bcc2d772ff09832155ca488b2dc479a0
author Ajay Singh Parmar <aparmar@codeaurora.org> Wed Jul 23 22:58:43 2014 -0700
committer Ajay Singh Parmar <aparmar@codeaurora.org> Thu Aug 07 22:10:37 2014 -0700
tree f724747929cc11e079738b2c4e394d78272050c7
parent fa6450defb34d4552b9a36505a6c89c915f46a2d

dev: pmic: add mvs support

Add support for MVS1 to enable HDMI

Change-Id: I39b272f34b07a37a9889d139e24148f4a6b3542c

dev/pmic/pm8x41/include/pm8x41.h

diff --git a/dev/pmic/pm8x41/include/pm8x41.h b/dev/pmic/pm8x41/include/pm8x41.h
index 472e69f..8681feb 100644
--- a/dev/pmic/pm8x41/include/pm8x41.h
+++ b/dev/pmic/pm8x41/include/pm8x41.h
@@ -171,6 +171,12 @@
 	MPP_ENABLE,
 };
 
+enum mvs_en_ctl
+{
+	MVS_DISABLE,
+	MVS_ENABLE,
+};
+
 enum mpp_mode
 {
 	MPP_DIGITAL_INPUT,
@@ -190,9 +196,15 @@
 	enum mpp_mode_en_source_select mode;
 };
 
+struct pm8x41_mvs
+{
+	uint32_t                       base;
+};
+
 #define PM8x41_MMP2_BASE                      0xA100
 #define PM8x41_MMP3_BASE                      0xA200
 #define PM8x41_MMP4_BASE                      0xA300
+#define PM8x41_MVS1_BASE                      0x18400
 
 void pm8x41_lpg_write(uint8_t chan, uint8_t off, uint8_t val);
 int pm8x41_gpio_get(uint8_t gpio, uint8_t *status);
@@ -212,6 +224,7 @@
 uint32_t pm8x41_get_pwrkey_is_pressed();
 void pm8x41_config_output_mpp(struct pm8x41_mpp *mpp);
 void pm8x41_enable_mpp(struct pm8x41_mpp *mpp, enum mpp_en_ctl enable);
+void pm8x41_enable_mvs(struct pm8x41_mvs *mvs, enum mvs_en_ctl enable);
 uint8_t pm8x41_get_is_cold_boot();
 void pm8x41_diff_clock_ctrl(uint8_t enable);
 void pm8x41_clear_pmic_watchdog(void);

dev/pmic/pm8x41/include/pm8x41_hw.h

diff --git a/dev/pmic/pm8x41/include/pm8x41_hw.h b/dev/pmic/pm8x41/include/pm8x41_hw.h
index 9d05219..db4473c 100644
--- a/dev/pmic/pm8x41/include/pm8x41_hw.h
+++ b/dev/pmic/pm8x41/include/pm8x41_hw.h
@@ -99,6 +99,10 @@
 #define MPP_MODE_CTL_MODE_SHIFT               4
 #define MPP_EN_CTL_ENABLE_SHIFT               7
 
+/* MVS registers */
+#define MVS_EN_CTL                            0x46
+#define MVS_EN_CTL_ENABLE_SHIFT               7
+
 void pm8x41_reg_write(uint32_t addr, uint8_t val);
 uint8_t pm8x41_reg_read(uint32_t addr);
 

dev/pmic/pm8x41/pm8x41.c

diff --git a/dev/pmic/pm8x41/pm8x41.c b/dev/pmic/pm8x41/pm8x41.c
index 169994a..326505a 100644
--- a/dev/pmic/pm8x41/pm8x41.c
+++ b/dev/pmic/pm8x41/pm8x41.c
@@ -390,6 +390,13 @@
 	return REG_READ(PON_POFF_REASON2);
 }
 
+void pm8x41_enable_mvs(struct pm8x41_mvs *mvs, enum mvs_en_ctl enable)
+{
+	ASSERT(mvs);
+
+	REG_WRITE(mvs->base + MVS_EN_CTL, enable << MVS_EN_CTL_ENABLE_SHIFT);
+}
+
 void pm8x41_enable_mpp(struct pm8x41_mpp *mpp, enum mpp_en_ctl enable)
 {
 	ASSERT(mpp);