platform: msm_shared: fix DSI phy contention detection programming
When dual dsi is enabled, ensure that the register programming related
to phy contention detection is done for both DSI0 and DSI1 phy
registers.
Change-Id: I35c12ad8b44666c4bd82c636b6d2a98b2c454738
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index a014da3..2787960 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -398,7 +398,7 @@
return;
pd = (mipi->mdss_dsi_phy_db);
- writel(pd->strength[1], phy_base + 0x0188);
+ writel(pd->strength[1], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_1);
dmb();
}
@@ -437,9 +437,6 @@
dmb();
}
- writel(pd->strength[1], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_1);
- dmb();
-
for (ln = 0; ln < TOTAL_LANE_COUNT; ln++) {
off = (ln * 0x40);
for (i = 0; i < CONFIG_REG_FOR_EACH_LANE; i++, off += 4) {