platform: msm_shared: Update MDP5 for APQ8084 support
APQ8084 supports MDP 5.3 version and has different base
addresses for rgb0 pipe, rgb1 pipe, mixer0 and mixer1.
This change updates MDP5 with these new addresses and
adds display files for compilation.
Change-Id: I6489f50ff381f2e87699baf92481e88d20a63182
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index 314d19c..b280667 100644
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -177,14 +177,14 @@
ASSERT(0); /* Max 4 SMPs can be allocated per client */
}
- writel(smp_cnt * 0x40, RGB0_REQPRIORITY_FIFO_WATERMARK0);
- writel(smp_cnt * 0x80, RGB0_REQPRIORITY_FIFO_WATERMARK1);
- writel(smp_cnt * 0xc0, RGB0_REQPRIORITY_FIFO_WATERMARK2);
+ writel(smp_cnt * 0x40, MDP_VP_0_RGB_0_BASE + REQPRIORITY_FIFO_WATERMARK0);
+ writel(smp_cnt * 0x80, MDP_VP_0_RGB_0_BASE + REQPRIORITY_FIFO_WATERMARK1);
+ writel(smp_cnt * 0xc0, MDP_VP_0_RGB_0_BASE + REQPRIORITY_FIFO_WATERMARK2);
if (pinfo->lcdc.dual_pipe) {
- writel(smp_cnt * 0x40, RGB1_REQPRIORITY_FIFO_WATERMARK0);
- writel(smp_cnt * 0x80, RGB1_REQPRIORITY_FIFO_WATERMARK1);
- writel(smp_cnt * 0xc0, RGB1_REQPRIORITY_FIFO_WATERMARK2);
+ writel(smp_cnt * 0x40, MDP_VP_0_RGB_1_BASE + REQPRIORITY_FIFO_WATERMARK0);
+ writel(smp_cnt * 0x80, MDP_VP_0_RGB_1_BASE + REQPRIORITY_FIFO_WATERMARK1);
+ writel(smp_cnt * 0xc0, MDP_VP_0_RGB_1_BASE + REQPRIORITY_FIFO_WATERMARK2);
}
while((smp_cnt > 0) && !(shift > 16)) {