msm_shared: mdp: modify dual dsi interface swap implementation
Use the crossbar located before MDSS interfaces to allow ctl0
to send data to DSI1 interface and ctl1 to DSI0 interface. This
aligns with the implementation in the kernel and eliminates display
corruption issues seen with continuous splash screen feature.
Change-Id: Ibc49848d9310ef5211c6840f057732e1bd37775a
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index 848a1c0..b860450 100644
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -125,24 +125,17 @@
static void mdss_source_pipe_config(struct fbcon_config *fb, struct msm_panel_info
*pinfo, uint32_t pipe_base)
{
- uint32_t src_size, out_size, stride, pipe_swap;
+ uint32_t src_size, out_size, stride;
uint32_t fb_off = 0;
/* write active region size*/
src_size = (fb->height << 16) + fb->width;
out_size = src_size;
-
if (pinfo->lcdc.dual_pipe) {
out_size = (fb->height << 16) + (fb->width / 2);
- pipe_swap = (pinfo->lcdc.pipe_swap == TRUE) ? 1 : 0;
-
- if (pipe_swap && ((pipe_base == MDP_VP_0_RGB_0_BASE) ||
- (pipe_base == MDP_VP_0_DMA_0_BASE) ||
- (pipe_base == MDP_VP_0_VIG_0_BASE)))
- fb_off = (pinfo->xres / 2);
- else if (!pipe_swap && ((pipe_base == MDP_VP_0_RGB_1_BASE) ||
- (pipe_base == MDP_VP_0_DMA_1_BASE) ||
- (pipe_base == MDP_VP_0_VIG_1_BASE)))
+ if ((pipe_base == MDP_VP_0_RGB_1_BASE) ||
+ (pipe_base == MDP_VP_0_DMA_1_BASE) ||
+ (pipe_base == MDP_VP_0_VIG_1_BASE))
fb_off = (pinfo->xres / 2);
}
@@ -491,6 +484,22 @@
writel(map, MDP_QOS_REMAPPER_CLASS_0);
}
+static uint32_t mdss_mdp_ctl_out_sel(struct msm_panel_info *pinfo,
+ int is_main_ctl)
+{
+ if (pinfo->lcdc.pipe_swap) {
+ if (is_main_ctl)
+ return BIT(4) | BIT(5); /* Interface 2 */
+ else
+ return BIT(5); /* Interface 1 */
+ } else {
+ if (is_main_ctl)
+ return BIT(5); /* Interface 1 */
+ else
+ return BIT(4) | BIT(5); /* Interface 2 */
+ }
+}
+
int mdp_dsi_video_config(struct msm_panel_info *pinfo,
struct fbcon_config *fb)
{
@@ -498,6 +507,7 @@
struct lcdc_panel_info *lcdc = NULL;
uint32_t intf_sel = 0x100;
uint32_t left_pipe, right_pipe;
+ uint32_t reg;
mdss_intf_tg_setup(pinfo, MDP_INTF_1_BASE);
@@ -519,10 +529,12 @@
mdss_layer_mixer_setup(fb, pinfo);
- writel(0x1F20, MDP_CTL_0_BASE + CTL_TOP);
+ reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo, 1);
+ writel(reg, MDP_CTL_0_BASE + CTL_TOP);
if (pinfo->mipi.dual_dsi) {
- writel(0x1F30, MDP_CTL_1_BASE + CTL_TOP);
+ reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo, 0);
+ writel(reg, MDP_CTL_1_BASE + CTL_TOP);
intf_sel |= BIT(16); /* INTF 2 enable */
}
@@ -574,6 +586,7 @@
struct fbcon_config *fb)
{
uint32_t intf_sel = BIT(8);
+ uint32_t reg;
int ret = NO_ERROR;
uint32_t left_pipe, right_pipe;
@@ -588,8 +601,13 @@
return ERR_INVALID_ARGS;
if (pinfo->lcdc.split_display) {
- writel(0x102, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL);
- writel(0x102, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL);
+ reg = BIT(1); /* Command mode */
+ if (pinfo->lcdc.pipe_swap)
+ reg |= BIT(4); /* Use intf2 as trigger */
+ else
+ reg |= BIT(8); /* Use intf1 as trigger */
+ writel(reg, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL);
+ writel(reg, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL);
writel(0x1, MDP_REG_SPLIT_DISPLAY_EN);
}
@@ -615,11 +633,13 @@
mdss_layer_mixer_setup(fb, pinfo);
writel(0x213F, MDP_INTF_1_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off);
- writel(0x21f20, MDP_CTL_0_BASE + CTL_TOP);
+ reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 1);
+ writel(reg, MDP_CTL_0_BASE + CTL_TOP);
if (pinfo->mipi.dual_dsi) {
writel(0x213F, MDP_INTF_2_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off);
- writel(0x21F30, MDP_CTL_1_BASE + CTL_TOP);
+ reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0);
+ writel(reg, MDP_CTL_1_BASE + CTL_TOP);
}
return ret;