diff --git a/dev/gcdb/display/gcdb_display.c b/dev/gcdb/display/gcdb_display.c
index 26bbe90..dfb6484 100644
--- a/dev/gcdb/display/gcdb_display.c
+++ b/dev/gcdb/display/gcdb_display.c
@@ -501,6 +501,16 @@
 		}
 	}
 
+	if (panelstruct.config && panelstruct.config->use_pingpong_split)
+		panelstruct.paneldata->panel_operating_mode |= DST_SPLIT_FLAG;
+
+	if ((panelstruct.paneldata->panel_operating_mode & DUAL_PIPE_FLAG) &&
+	    (panelstruct.paneldata->panel_operating_mode & DST_SPLIT_FLAG)) {
+		dprintf(CRITICAL, "DUAL_PIPE_FLAG and DST_SPLIT_FLAG cannot be selected togather\n");
+		ret = ERROR;
+		goto error_gcdb_display_init;
+	}
+
 	if (pan_type == PANEL_TYPE_DSI) {
 		target_dsi_phy_config(&dsi_video_mode_phy_db);
 		mdss_dsi_check_swap_status();
diff --git a/dev/gcdb/display/include/panel.h b/dev/gcdb/display/include/panel.h
index 05a79e2..fb03bb3 100755
--- a/dev/gcdb/display/include/panel.h
+++ b/dev/gcdb/display/include/panel.h
@@ -230,6 +230,7 @@
 	int lm_split[2];
 	int num_dsc_enc; /* how many encoder to use */
 	struct dsc_parameters *dsc;
+	int use_pingpong_split;
 };
 
 #endif /*_PANEL_H_ */
diff --git a/dev/gcdb/display/include/panel_nt35597_wqxga_dsc_cmd.h b/dev/gcdb/display/include/panel_nt35597_wqxga_dsc_cmd.h
index 084b983..5945f92 100644
--- a/dev/gcdb/display/include/panel_nt35597_wqxga_dsc_cmd.h
+++ b/dev/gcdb/display/include/panel_nt35597_wqxga_dsc_cmd.h
@@ -338,17 +338,17 @@
 
 /* 1LM + 1 DSC_ENC */
 struct topology_config nt35597_wqxga_dsc_cmd_config0 = {
-	"config0", {-1, -1}, 1, &nt35597_wqxga_dsc_cmd_params0
+	"config0", {-1, -1}, 1, &nt35597_wqxga_dsc_cmd_params0, false
 };
 
 /* 2LM + 3D Mux + 1 DSC_ENC */
 struct topology_config nt35597_wqxga_dsc_cmd_config1 = {
-	"config1", {720, 720}, 1, &nt35597_wqxga_dsc_cmd_params0
+	"config1", {720, 720}, 1, &nt35597_wqxga_dsc_cmd_params0, false
 };
 
 /* 2LM + 2 DSC_ENC + DSC_MERGE */
 struct topology_config nt35597_wqxga_dsc_cmd_config2 = {
-	"config2", {720, 720}, 2, &nt35597_wqxga_dsc_cmd_params0
+	"config2", {720, 720}, 2, &nt35597_wqxga_dsc_cmd_params0, false
 };
 
 #endif
diff --git a/dev/gcdb/display/include/panel_nt35597_wqxga_dsc_video.h b/dev/gcdb/display/include/panel_nt35597_wqxga_dsc_video.h
index afcebfc..a027ae9 100644
--- a/dev/gcdb/display/include/panel_nt35597_wqxga_dsc_video.h
+++ b/dev/gcdb/display/include/panel_nt35597_wqxga_dsc_video.h
@@ -325,17 +325,17 @@
 
 /* 1LM + 1 DSC_ENC */
 struct topology_config nt35597_wqxga_dsc_video_config0 = {
-	"config0", {-1, -1}, 1, &nt35597_wqxga_dsc_video_params0
+	"config0", {-1, -1}, 1, &nt35597_wqxga_dsc_video_params0, false
 };
 
 /* 2LM + 3D Mux + 1 DSC_ENC */
 struct topology_config nt35597_wqxga_dsc_video_config1 = {
-	"config1", {720, 720}, 1, &nt35597_wqxga_dsc_video_params0
+	"config1", {720, 720}, 1, &nt35597_wqxga_dsc_video_params0, false
 };
 
 /* 2LM + 2 DSC_ENC + DSC_MERGE */
 struct topology_config nt35597_wqxga_dsc_video_config2 = {
-	"config2", {720, 720}, 2, &nt35597_wqxga_dsc_video_params0
+	"config2", {720, 720}, 2, &nt35597_wqxga_dsc_video_params0, false
 };
 
 #endif
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index 461a14e..19317ac 100755
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -93,10 +93,12 @@
 
 	/* return MMSS_MDP_PPB0_CONFIG offset from MDSS base */
 	if ((mdss_mdp_rev == MDSS_MDP_HW_REV_108) ||
-		(mdss_mdp_rev == MDSS_MDP_HW_REV_111))
+	    (mdss_mdp_rev == MDSS_MDP_HW_REV_111))
 		mdss_mdp_ppb_off = 0x1420;
 	else if (mdss_mdp_rev == MDSS_MDP_HW_REV_110)
 		mdss_mdp_ppb_off = 0x1334;
+	else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_107))
+		mdss_mdp_ppb_off = 0x1330;
 	else
 		dprintf(CRITICAL,"Invalid PPB0_CONFIG offset\n");
 
@@ -523,10 +525,10 @@
 		}
 	}
 
-	if (pinfo->lcdc.dst_split &&  (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset()))) {
+	if (pinfo->lcdc.dst_split && (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset()))) {
 		uint32_t ppb_offset = mdss_mdp_get_ppb_offset();
-		writel(BIT(16), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CNTL */
-		writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CONFIG */
+		writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CNTL */
+		writel(BIT(16) | (0x3 << 20), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CONFIG */
 	}
 
 	if (pinfo->compression_mode == COMPRESSION_FBC)
@@ -1140,8 +1142,8 @@
 
 	if (pinfo->lcdc.dst_split) {
 		uint32_t ppb_offset = mdss_mdp_get_ppb_offset();
-		writel(BIT(16) | BIT(20) | BIT(21), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CNTL */
-		writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CONFIG */
+		writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CNTL */
+		writel(BIT(16) | (0x3 << 20), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CONFIG */
 	}
 
 	mdp_clk_gating_ctrl();