diff --git a/platform/msm8952/acpuclock.c b/platform/msm8952/acpuclock.c
index ec37789..57e4d0c 100644
--- a/platform/msm8952/acpuclock.c
+++ b/platform/msm8952/acpuclock.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -321,11 +321,35 @@
 	}
 }
 
+void gcc_dsi_lp_clock_enable(uint32_t flags)
+{
+	int ret = 0;
+
+	if (flags & MMSS_DSI_CLKS_FLAG_DSI0) {
+		/* Configure ESC clock */
+		ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
+		if (ret) {
+			dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n",
+				ret);
+			ASSERT(0);
+		}
+	}
+
+	if (flags & MMSS_DSI_CLKS_FLAG_DSI1) {
+		/* Configure ESC clock */
+		ret = clk_get_set_enable("mdss_esc1_clk", 0, 1);
+		if (ret) {
+			dprintf(CRITICAL, "failed to set esc1_clk ret = %d\n",
+				ret);
+			ASSERT(0);
+		}
+	}
+}
+
 /* Configure all the branch clocks needed by the DSI controller */
-void gcc_dsi_clocks_enable(uint32_t flags, bool use_dsi1_pll, uint8_t pclk0_m,
+void gcc_dsi_hs_clocks_enable(uint32_t flags, bool use_dsi1_pll, uint8_t pclk0_m,
 		uint8_t pclk0_n, uint8_t pclk0_d)
 {
-	int ret;
 	int dsi0_cfg_rcgr, dsi1_cfg_rcgr = 0;
 
 	dsi0_cfg_rcgr = BIT(8); /* DSI0 can only be sourced from PLL0 */
@@ -364,13 +388,6 @@
 		/* Enable the branch clock */
 		writel(0x1, DSI_PIXEL0_CBCR);
 		branch_clk_halt_check(DSI_PIXEL0_CBCR);
-
-		/* Configure ESC clock */
-		ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
-		if (ret) {
-			dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret);
-			ASSERT(0);
-		}
 	}
 
 	if (flags & MMSS_DSI_CLKS_FLAG_DSI1) {
@@ -398,13 +415,6 @@
 		/* Enable the branch clock */
 		writel(0x1, DSI_PIXEL1_CBCR);
 		branch_clk_halt_check(DSI_PIXEL1_CBCR);
-
-		/* Configure ESC clock */
-		ret = clk_get_set_enable("mdss_esc1_clk", 0, 1);
-		if (ret) {
-			dprintf(CRITICAL, "failed to set esc1_clk ret = %d\n", ret);
-			ASSERT(0);
-		}
 	}
 }
 
diff --git a/platform/msm8952/include/platform/clock.h b/platform/msm8952/include/platform/clock.h
index c9e8cc7..e6734cb 100644
--- a/platform/msm8952/include/platform/clock.h
+++ b/platform/msm8952/include/platform/clock.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -95,7 +95,8 @@
 void mdss_bus_clocks_disable(void);
 void mdp_clock_enable(void);
 void mdp_clock_disable(void);
-void gcc_dsi_clocks_enable(uint32_t flags,  bool use_dsi1_pll, uint8_t pclk0_m,
+void gcc_dsi_hs_clocks_enable(uint32_t flags,  bool use_dsi1_pll, uint8_t pclk0_m,
 		uint8_t pclk0_n, uint8_t pclk0_d);
+void gcc_dsi_lp_clock_enable(uint32_t flags);
 void gcc_dsi_clocks_disable(uint32_t flags);
 #endif
diff --git a/target/msm8952/target_display.c b/target/msm8952/target_display.c
index 68f15f9..e98b21d 100644
--- a/target/msm8952/target_display.c
+++ b/target/msm8952/target_display.c
@@ -367,6 +367,8 @@
 			return ret;
 		}
 
+		gcc_dsi_lp_clock_enable(flags);
+
 		ret = mdss_dsi_pll_config(pinfo->mipi.pll_base,
 			pinfo->mipi.ctl_base, pll_data);
 		if (!ret)
@@ -380,7 +382,7 @@
 				dprintf(CRITICAL, "Not able to enable second pll\n");
 		}
 
-		gcc_dsi_clocks_enable(flags, pinfo->mipi.use_dsi1_pll,
+		gcc_dsi_hs_clocks_enable(flags, pinfo->mipi.use_dsi1_pll,
 			pll_data->pclk_m, pll_data->pclk_n, pll_data->pclk_d);
 	} else if(!target_cont_splash_screen()) {
 		gcc_dsi_clocks_disable(flags);