[msm7630]: Support local clock control for MDDI display
Change-Id: Ic8ed24a016efb8de8a83bbe8e34f8491dc6b4e1e
CRs-Fixed: 271867
diff --git a/platform/msm7x30/acpuclock.c b/platform/msm7x30/acpuclock.c
index 42eb56b..e40d410 100644
--- a/platform/msm7x30/acpuclock.c
+++ b/platform/msm7x30/acpuclock.c
@@ -31,21 +31,11 @@
#include <platform/iomap.h>
#include <reg.h>
-#define REG_BASE(off) (MSM_CLK_CTL_BASE + (off))
-#define REG(off) (MSM_CLK_CTL_SH2_BASE + (off))
-
-#define PLL_ENA_REG REG(0x0264)
-#define PLL2_STATUS_BASE_REG REG_BASE(0x0350)
-
-#define PLL2_L_VAL_ADDR REG_BASE(0x033C)
#define ACPU_806MHZ 42
#define ACPU_1024MHZ 53
#define ACPU_1200MHZ 125
#define ACPU_1400MHZ 73
-#define SH2_OWN_ROW2_BASE_REG REG_BASE(0x0424)
-#define SH2_OWN_APPS2_BASE_REG REG_BASE(0x0414)
-
/* Macros to select PLL2 with divide by 1 */
#define ACPU_SRC_SEL 3
#define ACPU_SRC_DIV 0
@@ -277,3 +267,35 @@
lcdc_clock_init(27648000);
}
}
+
+void mddi_pmdh_clock_init(void)
+{
+ unsigned int val = 0;
+ unsigned sh2_own_row1;
+ unsigned sh2_own_row1_pmdh_mask = (1 << 19);
+
+ sh2_own_row1 = readl(SH2_OWN_ROW1_BASE_REG);
+ if(sh2_own_row1 & sh2_own_row1_pmdh_mask)
+ {
+ /* Select clock source and divider */
+ val = 1;
+ val |= (1 << 3);
+ val = val | readl(SH2_PMDH_NS_REG);
+ writel(val, SH2_PMDH_NS_REG);
+
+ /* Enable PMDH_SRC (root) signal */
+ val = 1 << 11;
+ val = val | readl(SH2_PMDH_NS_REG);
+ writel(val, SH2_PMDH_NS_REG);
+
+ /* Enable PMDH_P_CLK */
+ val = 1 << 4;
+ val = val | readl(SH2_GLBL_CLK_ENA_2_SC);
+ writel(val, SH2_GLBL_CLK_ENA_2_SC);
+ }
+ else
+ {
+ /* MDDI local clock control not enabled; use proc comm */
+ mddi_clock_init(0, 480000000);
+ }
+}
diff --git a/platform/msm7x30/include/platform/iomap.h b/platform/msm7x30/include/platform/iomap.h
index 853c4b3..2e7e1c2 100644
--- a/platform/msm7x30/include/platform/iomap.h
+++ b/platform/msm7x30/include/platform/iomap.h
@@ -52,20 +52,33 @@
#define MSM_CLK_CTL_BASE 0xAB800000
#define MSM_CLK_CTL_SH2_BASE 0xABA01000
+
+#define REG_BASE(off) (MSM_CLK_CTL_BASE + (off))
+#define REG_SH2_BASE(off) (MSM_CLK_CTL_SH2_BASE + (off))
+
#define SCSS_CLK_CTL 0xC0101004
#define SCSS_CLK_SEL 0xC0101008
#define MSM_USB_BASE 0xA3600000
-#define SH2_USBH_MD_REG 0xABA012BC
-#define SH2_USBH_NS_REG 0xABA012C0
+#define SH2_USBH_MD_REG REG_SH2_BASE(0x2BC)
+#define SH2_USBH_NS_REG REG_SH2_BASE(0x2C0)
-#define SH2_MDP_NS_REG 0xABA0114C
-#define SH2_MDP_LCDC_MD_REG 0xABA0138C
-#define SH2_MDP_LCDC_NS_REG 0xABA01390
-#define SH2_MDP_VSYNC_REG 0xABA01460
+#define SH2_MDP_NS_REG REG_SH2_BASE(0x14C)
+#define SH2_MDP_LCDC_MD_REG REG_SH2_BASE(0x38C)
+#define SH2_MDP_LCDC_NS_REG REG_SH2_BASE(0x390)
+#define SH2_MDP_VSYNC_REG REG_SH2_BASE(0x460)
+#define SH2_PMDH_NS_REG REG_SH2_BASE(0x8C)
-#define SH2_GLBL_CLK_ENA_SC 0xABA013BC
-#define SH2_GLBL_CLK_ENA_2_SC 0xABA013C0
+#define SH2_GLBL_CLK_ENA_SC REG_SH2_BASE(0x3BC)
+#define SH2_GLBL_CLK_ENA_2_SC REG_SH2_BASE(0x3C0)
+
+#define SH2_OWN_ROW1_BASE_REG REG_BASE(0x041C)
+#define SH2_OWN_ROW2_BASE_REG REG_BASE(0x0424)
+#define SH2_OWN_APPS2_BASE_REG REG_BASE(0x0414)
#define MSM_SAW_BASE 0xC0102000
+
+#define PLL_ENA_REG REG_SH2_BASE(0x0264)
+#define PLL2_STATUS_BASE_REG REG_BASE(0x0350)
+#define PLL2_L_VAL_ADDR REG_BASE(0x033C)
#endif
diff --git a/platform/msm7x30/platform.c b/platform/msm7x30/platform.c
index 2032e81..75e8e14 100644
--- a/platform/msm7x30/platform.c
+++ b/platform/msm7x30/platform.c
@@ -115,7 +115,7 @@
struct fbcon_config *fb_cfg;
#if DISPLAY_TYPE_MDDI
- mddi_clock_init(0, 480000000);
+ mddi_pmdh_clock_init();
mddi_panel_poweron();
/* We need to config GPIO 38 for Sleep clock with Spl Fun 2 */
toshiba_pmic_gpio_init(GPIO38_GPIO_CNTRL);