diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index e43f120..6a46a19 100644
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -2150,7 +2150,7 @@
 
 	// Initialize boot state before trying to verify boot.img
 #if VERIFIED_BOOT
-		boot_verifier_init();
+	boot_verifier_init();
 	/* Handle overflow if the input image size is greater than
 	 * boot image buffer can hold
 	 */
diff --git a/dev/gcdb/display/include/panel_byd_1200p_video.h b/dev/gcdb/display/include/panel_byd_1200p_video.h
new file mode 100644
index 0000000..20e0d75
--- /dev/null
+++ b/dev/gcdb/display/include/panel_byd_1200p_video.h
@@ -0,0 +1,1375 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  * Neither the name of The Linux Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _PANEL_BYD_1200P_VIDEO_H_
+
+#define _PANEL_BYD_1200P_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files                                                              */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration                                                       */
+/*---------------------------------------------------------------------------*/
+
+static struct panel_config byd_1200p_video_panel_data = {
+	"qcom,mdss_dsi_byd_1200p_video", "dsi:0:", "qcom,mdss-dsi-panel",
+	10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, NULL
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution                                                          */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution byd_1200p_video_panel_res = {
+	1200, 1920, 96, 64, 16, 0, 4, 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Color Information                                                   */
+/*---------------------------------------------------------------------------*/
+static struct color_info byd_1200p_video_color = {
+	24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel Command information                                                 */
+/*---------------------------------------------------------------------------*/
+static char byd_1200p_video_on_cmd0  [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0x8C, 0x8E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd1  [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0xC5, 0x23, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd2  [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0xC7, 0x23, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd3  [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0xFD, 0x5C, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd4  [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0xFA, 0x14, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd5  [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0X83, 0XAA, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd6  [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0X84, 0X11, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd7  [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC0, 0X0E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd8  [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC1, 0X12, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd9  [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC2, 0X25, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd10 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC3, 0X34, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd11 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC4, 0X3F, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd12 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC5, 0X49, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd13 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC6, 0X52, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd14 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC7, 0X59, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd15 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC8, 0X60, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd16 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC9, 0XC8, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd17 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XCA, 0XC7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd18 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XCB, 0XD6, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd19 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XCC, 0XD9, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd20 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XCD, 0XD7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd21 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XCE, 0XD1, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd22 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XCF, 0XD3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd23 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD0, 0XD4, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd24 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD1, 0XFF, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd25 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD2, 0X08, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd26 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD3, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd27 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD4, 0X3B, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd28 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD5, 0XAA, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd29 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD6, 0XB3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd30 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD7, 0XBC, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd31 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD8, 0XC5, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd32 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD9, 0XD0, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd33 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XDA, 0XDB, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd34 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XDB, 0XE7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd35 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XDC, 0XF7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd36 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XDD, 0XFE, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd37 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XDE, 0X00, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd38 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XDF, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd39 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE0, 0X0E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd40 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE1, 0X12, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd41 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE2, 0X25, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd42 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE3, 0X34, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd43 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE4, 0X3F, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd44 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE5, 0X49, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd45 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE6, 0X52, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd46 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE7, 0X59, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd47 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE8, 0X60, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd48 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE9, 0XC8, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd49 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XEA, 0XC7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd50 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XEB, 0XD6, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd51 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XEC, 0XD9, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd52 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XED, 0XD7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd53 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XEE, 0XD1, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd54 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XEF, 0XD3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd55 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF0, 0XD4, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd56 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF1, 0XFF, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd57 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF2, 0X08, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd58 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF3, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd59 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF4, 0X3B, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd60 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF5, 0XAA, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd61 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF6, 0XB3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd62 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF7, 0XBC, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd63 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF8, 0XC5, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd64 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF9, 0XD0, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd65 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XFA, 0XDB, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd66 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XFB, 0XE7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd67 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XFC, 0XF7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd68 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XFD, 0XFE, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd69 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XFE, 0X00, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd70 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XFF, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd71 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XA9, 0X4b, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd72 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0X83, 0XBB, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd73 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0X84, 0X22, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd74 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC0, 0X0E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd75 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC1, 0X12, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd76 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC2, 0X25, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd77 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC3, 0X34, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd78 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC4, 0X3F, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd79 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC5, 0X49, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd80 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC6, 0X52, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd81 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC7, 0X59, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd82 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC8, 0X60, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd83 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC9, 0XC8, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd84 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XCA, 0XC7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd85 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XCB, 0XD6, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd86 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XCC, 0XD9, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd87 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XCD, 0XD7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd88 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XCE, 0XD1, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd89 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XCF, 0XD3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd90 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD0, 0XD4, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd91 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD1, 0XFF, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd92 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD2, 0X08, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd93 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD3, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd94 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD4, 0X3B, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd95 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD5, 0XAA, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd96 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD6, 0XB3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd97 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD7, 0XBC, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd98 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD8, 0XC5, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd99 [] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD9, 0XD0, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd100[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XDA, 0XDB, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd101[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XDB, 0XE7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd102[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XDC, 0XF7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd103[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XDD, 0XFE, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd104[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XDE, 0X00, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd105[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XDF, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd106[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE0, 0X0E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd107[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE1, 0X12, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd108[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE2, 0X25, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd109[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE3, 0X34, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd110[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE4, 0X3F, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd111[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE5, 0X49, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd112[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE6, 0X52, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd113[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE7, 0X59, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd114[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE8, 0X60, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd115[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE9, 0XC8, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd116[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XEA, 0XC7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd117[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XEB, 0XD6, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd118[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XEC, 0XD9, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd119[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XED, 0XD7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd120[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XEE, 0XD1, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd121[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XEF, 0XD3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd122[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF0, 0XD4, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd123[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF1, 0XFF, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd124[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF2, 0X08, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd125[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF3, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd126[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF4, 0X3B, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd127[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF5, 0XAA, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd128[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF6, 0XB3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd129[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF7, 0XBC, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd130[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF8, 0XC5, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd131[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF9, 0XD0, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd132[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XFA, 0XDB, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd133[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XFB, 0XE7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd134[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XFC, 0XF7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd135[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XFD, 0XFE, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd136[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XFE, 0X00, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd137[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XFF, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd138[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0X83, 0XCC, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd139[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0X84, 0X33, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd140[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC0, 0X0E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd141[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC1, 0X12, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd142[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC2, 0X25, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd143[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC3, 0X34, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd144[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC4, 0X3F, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd145[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC5, 0X49, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd146[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC6, 0X52, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd147[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC7, 0X59, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd148[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC8, 0X60, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd149[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XC9, 0XC8, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd150[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XCA, 0XC7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd151[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XCB, 0XD6, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd152[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XCC, 0XD9, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd153[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XCD, 0XD7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd154[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XCE, 0XD1, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd155[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XCF, 0XD3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd156[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD0, 0XD4, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd157[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD1, 0XFF, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd158[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD2, 0X08, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd159[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD3, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd160[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD4, 0X3B, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd161[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD5, 0XAA, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd162[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD6, 0XB3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd163[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD7, 0XBC, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd164[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD8, 0XC5, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd165[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XD9, 0XD0, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd166[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XDA, 0XDB, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd167[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XDB, 0XE7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd168[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XDC, 0XF7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd169[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XDD, 0XFE, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd170[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XDE, 0X00, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd171[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XDF, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd172[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE0, 0X0E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd173[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE1, 0X12, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd174[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE2, 0X25, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd175[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE3, 0X34, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd176[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE4, 0X3F, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd177[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE5, 0X49, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd178[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE6, 0X52, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd179[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE7, 0X59, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd180[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE8, 0X60, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd181[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XE9, 0XC8, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd182[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XEA, 0XC7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd183[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XEB, 0XD6, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd184[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XEC, 0XD9, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd185[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XED, 0XD7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd186[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XEE, 0XD1, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd187[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XEF, 0XD3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd188[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF0, 0XD4, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd189[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF1, 0XFF, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd190[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF2, 0X08, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd191[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF3, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd192[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF4, 0X3B, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd193[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF5, 0XAA, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd194[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF6, 0XB3, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd195[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF7, 0XBC, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd196[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF8, 0XC5, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd197[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XF9, 0XD0, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd198[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XFA, 0XDB, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd199[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XFB, 0XE7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd200[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XFC, 0XF7, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd201[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XFD, 0XFE, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd202[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XFE, 0X00, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd203[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0XFF, 0X2E, 0xFF, 0xFF,
+};
+
+static char byd_1200p_video_on_cmd204[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0x11, 0x00, 0xFF, 0xFF,};
+
+static char byd_1200p_video_on_cmd205[] = {
+	0x02, 0x00, 0x29, 0xC0,
+	0x29, 0x00, 0xFF, 0xFF,
+};
+
+static struct mipi_dsi_cmd byd_1200p_video_on_command[] = {
+	{ 0x8 , byd_1200p_video_on_cmd0,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd1,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd2,  0x10},
+	{ 0x8 , byd_1200p_video_on_cmd3,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd4,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd5,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd6,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd7,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd8,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd9,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd10,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd11,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd12,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd13,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd14,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd15,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd16,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd17,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd18,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd19,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd20,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd21,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd22,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd23,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd24,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd25,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd26,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd27,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd28,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd29,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd30,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd31,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd32,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd33,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd34,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd35,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd36,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd37,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd38,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd39,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd40,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd41,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd42,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd43,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd44,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd45,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd46,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd47,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd48,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd49,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd50,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd51,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd52,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd53,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd54,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd55,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd56,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd57,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd58,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd59,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd60,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd61,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd62,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd63,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd64,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd65,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd66,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd67,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd68,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd69,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd70,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd71,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd72,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd73,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd74,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd75,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd76,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd77,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd78,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd79,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd80,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd81,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd82,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd83,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd84,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd85,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd86,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd87,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd88,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd89,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd90,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd91,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd92,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd93,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd94,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd95,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd96,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd97,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd98,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd99,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd100,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd101,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd102,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd103,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd104,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd105,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd106,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd107,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd108,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd109,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd110,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd111,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd112,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd113,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd114,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd115,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd116,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd117,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd118,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd119,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd120,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd121,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd122,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd123,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd124,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd125,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd126,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd127,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd128,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd129,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd130,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd131,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd132,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd133,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd134,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd135,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd136,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd137,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd138,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd139,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd140,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd141,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd142,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd143,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd144,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd145,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd146,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd147,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd148,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd149,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd150,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd151,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd152,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd153,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd154,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd155,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd156,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd157,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd158,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd159,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd160,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd161,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd162,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd163,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd164,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd165,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd166,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd167,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd168,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd169,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd170,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd171,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd172,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd173,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd174,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd175,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd176,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd177,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd178,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd179,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd180,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd181,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd182,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd183,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd184,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd185,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd186,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd187,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd188,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd189,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd190,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd191,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd192,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd193,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd194,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd195,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd196,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd197,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd198,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd199,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd200,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd201,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd202,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd203,  0x00},
+	{ 0x8 , byd_1200p_video_on_cmd204,  0xca},
+	{ 0x8 , byd_1200p_video_on_cmd205,  0x1f},
+};
+
+#define BYD_1200P_VIDEO_ON_COMMAND 206
+
+
+static char byd_1200p_video_off_cmd0[] = {
+	0x28, 0x00, 0x05, 0x80
+};
+
+static char byd_1200p_video_off_cmd1[] = {
+	0x10, 0x00, 0x05, 0x80
+};
+
+
+static struct mipi_dsi_cmd byd_1200p_video_off_command[] = {
+	{ 0x4 , byd_1200p_video_off_cmd0, 0x0},
+	{ 0x4 , byd_1200p_video_off_cmd1, 0x0}
+};
+
+#define BYD_1200P_VIDEO_OFF_COMMAND 2
+
+static struct command_state byd_1200p_video_state = {
+	0, 1
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information                                            */
+/*---------------------------------------------------------------------------*/
+
+static struct commandpanel_info byd_1200p_video_command_panel = {
+	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information                                              */
+/*---------------------------------------------------------------------------*/
+
+static struct videopanel_info byd_1200p_video_video_panel = {
+	0, 0, 0, 0, 1, 1, 1, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane Configuration                                                        */
+/*---------------------------------------------------------------------------*/
+
+static struct lane_configuration byd_1200p_video_lane_config = {
+	4, 0, 1, 1, 1, 1, 1
+};
+
+
+/*---------------------------------------------------------------------------*/
+/* Panel Timing                                                              */
+/*---------------------------------------------------------------------------*/
+const uint32_t byd_1200p_video_timings[] = {
+	0xE6, 0x38, 0x26, 0x00, 0x68, 0x6e, 0x2A, 0x3c, 0x44, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing byd_1200p_video_timing_info = {
+	0, 4, 0x02, 0x2d
+};
+
+static struct panel_reset_sequence byd_1200p_video_panel_reset_seq = {
+	{ 0, 1, 0, }, { 200, 200, 200, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight Settings                                                        */
+/*---------------------------------------------------------------------------*/
+
+static struct backlight byd_1200p_video_backlight = {
+	1, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+#define BYD_1200P_VIDEO_SIGNATURE 0xFFFF
+
+#endif /*_BYD_1200P_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_hx8399a_1080p_video.h b/dev/gcdb/display/include/panel_hx8399a_1080p_video.h
index f2d828e..a7c4df0 100644
--- a/dev/gcdb/display/include/panel_hx8399a_1080p_video.h
+++ b/dev/gcdb/display/include/panel_hx8399a_1080p_video.h
@@ -66,6 +66,11 @@
 };
 
 static char hx8399a_1080p_video_on_cmd1[] = {
+	0x03, 0x00, 0x29, 0xC0,
+	0xBA, 0x63, 0x82, 0xFF,
+};
+
+static char hx8399a_1080p_video_on_cmd2[] = {
 	0x0D, 0x00, 0x29, 0xC0,
 	0xB1, 0x00, 0x74, 0x31,
 	0x31, 0x44, 0x09, 0x22,
@@ -73,14 +78,14 @@
 	0x6D, 0xFF, 0xFF, 0xFF,
 };
 
-static char hx8399a_1080p_video_on_cmd2[] = {
+static char hx8399a_1080p_video_on_cmd3[] = {
 	0x0B, 0x00, 0x29, 0xC0,
 	0xB2, 0x00, 0x80, 0x00,
 	0x7F, 0x05, 0x07, 0x23,
 	0x4D, 0x02, 0x02, 0xFF,
 };
 
-static char hx8399a_1080p_video_on_cmd3[] = {
+static char hx8399a_1080p_video_on_cmd4[] = {
 	0x29, 0x00, 0x29, 0xC0,
 	0xB4, 0x00, 0xFF, 0x00,
 	0x40, 0x00, 0x3E, 0x00,
@@ -95,12 +100,12 @@
 	0x44, 0xFF, 0xFF, 0xFF,
 };
 
-static char hx8399a_1080p_video_on_cmd4[] = {
+static char hx8399a_1080p_video_on_cmd5[] = {
 	0x02, 0x00, 0x29, 0xC0,
 	0xD2, 0x00, 0xFF, 0xFF,
 };
 
-static char hx8399a_1080p_video_on_cmd5[] = {
+static char hx8399a_1080p_video_on_cmd6[] = {
 	0x20, 0x00, 0x29, 0xC0,
 	0xD3, 0x00, 0x01, 0x00,
 	0x00, 0x00, 0x30, 0x00,
@@ -112,7 +117,7 @@
 	0x00, 0x00, 0x05, 0x08,
 };
 
-static char hx8399a_1080p_video_on_cmd6[] = {
+static char hx8399a_1080p_video_on_cmd7[] = {
 	0x21, 0x00, 0x29, 0xC0,
 	0xD5, 0x18, 0x18, 0x00,
 	0x00, 0x00, 0x00, 0x00,
@@ -125,7 +130,7 @@
 	0x32, 0xFF, 0xFF, 0xFF,
 };
 
-static char hx8399a_1080p_video_on_cmd7[] = {
+static char hx8399a_1080p_video_on_cmd8[] = {
 	0x21, 0x00, 0x29, 0xC0,
 	0xD6, 0x18, 0x18, 0x40,
 	0x40, 0x40, 0x40, 0x40,
@@ -138,7 +143,7 @@
 	0x32, 0xFF, 0xFF, 0xFF,
 };
 
-static char hx8399a_1080p_video_on_cmd8[] = {
+static char hx8399a_1080p_video_on_cmd9[] = {
 	0x31, 0x00, 0x29, 0xC0,
 	0xD8, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00,
@@ -155,17 +160,17 @@
 	0xBF, 0xFF, 0xFF, 0xFF,
 };
 
-static char hx8399a_1080p_video_on_cmd9[] = {
+static char hx8399a_1080p_video_on_cmd10[] = {
 	0x03, 0x00, 0x29, 0xC0,
 	0xB6, 0x34, 0x34, 0xFF,
 };
 
-static char hx8399a_1080p_video_on_cmd10[] = {
+static char hx8399a_1080p_video_on_cmd11[] = {
 	0x02, 0x00, 0x29, 0xC0,
 	0xCC, 0x08, 0xFF, 0xFF,
 };
 
-static char hx8399a_1080p_video_on_cmd11[] = {
+static char hx8399a_1080p_video_on_cmd12[] = {
 	0x2B, 0x00, 0x29, 0xC0,
 	0xE0, 0x01, 0x10, 0x15,
 	0x2B, 0x32, 0x3E, 0x22,
@@ -180,46 +185,47 @@
 	0x17, 0x06, 0x12, 0xFF,
 };
 
-static char hx8399a_1080p_video_on_cmd12[] = {
+static char hx8399a_1080p_video_on_cmd13[] = {
 	0x04, 0x00, 0x29, 0xC0,
 	0xBF, 0xCF, 0x00, 0x46,
 };
 
-static char hx8399a_1080p_video_on_cmd13[] = {
+static char hx8399a_1080p_video_on_cmd14[] = {
 	0x02, 0x00, 0x29, 0xC0,
 	0x36, 0xc0, 0xFF, 0xFF,
 };
 
-static char hx8399a_1080p_video_on_cmd14[] = {
+static char hx8399a_1080p_video_on_cmd15[] = {
 	0x02, 0x00, 0x29, 0xC0,
 	0x11, 0x00, 0xFF, 0xFF,
 };
 
-static char hx8399a_1080p_video_on_cmd15[] = {
+static char hx8399a_1080p_video_on_cmd16[] = {
 	0x02, 0x00, 0x29, 0xC0,
 	0x29, 0x00, 0xFF, 0xFF,
 };
 
 static struct mipi_dsi_cmd hx8399a_1080p_video_on_command[] = {
 	{0x8, hx8399a_1080p_video_on_cmd0, 0x00},
-	{0x14, hx8399a_1080p_video_on_cmd1, 0x00},
-	{0x10, hx8399a_1080p_video_on_cmd2, 0x00},
-	{0x30, hx8399a_1080p_video_on_cmd3, 0x00},
-	{0x8, hx8399a_1080p_video_on_cmd4, 0x00},
-	{0x24, hx8399a_1080p_video_on_cmd5, 0x00},
-	{0x28, hx8399a_1080p_video_on_cmd6, 0x00},
+	{0x8, hx8399a_1080p_video_on_cmd1, 0x00},
+	{0x14, hx8399a_1080p_video_on_cmd2, 0x00},
+	{0x10, hx8399a_1080p_video_on_cmd3, 0x00},
+	{0x30, hx8399a_1080p_video_on_cmd4, 0x00},
+	{0x8, hx8399a_1080p_video_on_cmd5, 0x00},
+	{0x24, hx8399a_1080p_video_on_cmd6, 0x00},
 	{0x28, hx8399a_1080p_video_on_cmd7, 0x00},
-	{0x38, hx8399a_1080p_video_on_cmd8, 0x00},
-	{0x8, hx8399a_1080p_video_on_cmd9, 0x00},
+	{0x28, hx8399a_1080p_video_on_cmd8, 0x00},
+	{0x38, hx8399a_1080p_video_on_cmd9, 0x00},
 	{0x8, hx8399a_1080p_video_on_cmd10, 0x00},
-	{0x30, hx8399a_1080p_video_on_cmd11, 0x00},
-	{0x8, hx8399a_1080p_video_on_cmd12, 0x00},
+	{0x8, hx8399a_1080p_video_on_cmd11, 0x00},
+	{0x30, hx8399a_1080p_video_on_cmd12, 0x00},
 	{0x8, hx8399a_1080p_video_on_cmd13, 0x00},
-	{0x8, hx8399a_1080p_video_on_cmd14, 0x78},
-	{0x8, hx8399a_1080p_video_on_cmd15, 0x0A}
+	{0x8, hx8399a_1080p_video_on_cmd14, 0x00},
+	{0x8, hx8399a_1080p_video_on_cmd15, 0x78},
+	{0x8, hx8399a_1080p_video_on_cmd16, 0x0A}
 };
 
-#define HX8399A_1080P_VIDEO_ON_COMMAND 16
+#define HX8399A_1080P_VIDEO_ON_COMMAND 17
 
 
 static char hx8399a_1080p_videooff_cmd0[] = {
diff --git a/dev/pmic/fgsram/include/pm_fg_sram.h b/dev/pmic/fgsram/include/pm_fg_sram.h
new file mode 100644
index 0000000..a117e0d
--- /dev/null
+++ b/dev/pmic/fgsram/include/pm_fg_sram.h
@@ -0,0 +1,61 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+ *   * Neither the name of The Linux Foundation, nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _PM_FG_SRAM_H_
+#define _PM_FG_SRAM_H_
+
+#include <sys/types.h>
+
+#define FG_MEMIF_INT_RT_STS             0x4410
+#define FG_MEMIF_MEM_INTF_CFG           0x4450
+#define FG_MEMIF_MEM_INTF_CTL           0x4451
+#define FG_MEMIF_IMA_CFG                0x4452
+#define FG_MEMIF_IMA_OPERATION_STS      0x4454
+#define FG_MEMIF_IMA_EXCEPTION_STS      0x4455
+#define FG_MEMIF_MEM_INTF_ADDR_LSB      0x4461
+#define FG_MEMIF_MEM_INTF_ADDR_MSB      0x4462
+#define FG_MEMIF_MEM_INTF_WR_DATA0      0x4463
+#define FG_MEMIF_MEM_INTF_WR_DATA1      0x4464
+#define FG_MEMIF_MEM_INTF_WR_DATA2      0x4465
+#define FG_MEMIF_MEM_INTF_WR_DATA3      0x4466
+#define FG_MEMIF_MEM_INTF_RD_DATA0      0x4467
+#define FG_MEMIF_MEM_INTF_RD_DATA1      0x4468
+#define FG_MEMIF_MEM_INTF_RD_DATA2      0x4469
+#define FG_MEMIF_MEM_INTF_RD_DATA3      0x446A
+#define FG_MEMIF_FG_BEAT_COUNT          0x4457
+#define IACS_SLCT                       BIT(5)
+#define RIF_MEM_ACCESS_REQ              BIT(7)
+#define IACS_RDY                        BIT(1)
+#define IACS_CLR                        BIT(2)
+#define BEAT_COUNT_MASK                 0x0F
+#define FG_MAX_TRY                      10
+#define FG_DATA_MASK                    0xffffffff
+#define FG_DATA_MAX_LEN                 4
+
+int pmi_fg_sram_read(uint32_t addr, uint32_t *data,int sid, uint8_t offset, uint8_t len);
+
+#endif
diff --git a/dev/pmic/fgsram/pm_fg_sram.c b/dev/pmic/fgsram/pm_fg_sram.c
new file mode 100644
index 0000000..fd4cf14
--- /dev/null
+++ b/dev/pmic/fgsram/pm_fg_sram.c
@@ -0,0 +1,157 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+ *   * Neither the name of The Linux Foundation, nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <pm_fg_sram.h>
+#include <pm8x41.h>
+#include <pm8x41_hw.h>
+#include <debug.h>
+#include <bits.h>
+#include <platform/timer.h>
+#include <pm_comm.h>
+
+static int fg_check_addr_mask(int sid,uint32_t addr,uint8_t mask,uint8_t set)
+{
+	uint8_t value;
+	int ret = 1;
+	int try = FG_MAX_TRY;
+
+	udelay(30);
+	while(try)
+	{
+		ret = pm_comm_read_byte_mask(sid, addr, mask, &value, 0);
+		if( !ret && (value == set) )
+			goto err;
+
+		udelay(1000);
+		try--;
+	}
+err:
+	return ret;
+}
+
+int pmi_fg_sram_read(uint32_t addr, uint32_t *data,int sid, uint8_t offset, uint8_t len)
+{
+	uint8_t value;
+	int err = 0;
+	uint8_t start_beat_count, end_beat_count;
+
+	if(offset > 3)
+	{
+		dprintf(INFO,"offset beyond the 4 byte boundary\n");
+		goto err;
+	}
+	/* poll to check if fg memif is available */
+	err = fg_check_addr_mask(sid,FG_MEMIF_MEM_INTF_CFG, RIF_MEM_ACCESS_REQ, 0);
+	if(err)
+	{
+		dprintf(INFO,"Failed to get fg sram access\n");
+		goto err;
+	}
+
+	/* enter into ima mode write 8'hA0 */
+	pm_comm_write_byte(sid, FG_MEMIF_MEM_INTF_CFG, 0xA0, 0);
+	/* ensure single read access 8'h00 */
+	pm_comm_write_byte(sid, FG_MEMIF_MEM_INTF_CTL, 0x00, 0);
+
+	/* poll ima is ready */
+	err = fg_check_addr_mask(sid, FG_MEMIF_IMA_OPERATION_STS, IACS_RDY, 1);
+	if(err)
+	{
+		dprintf(INFO,"IACS is not ready cannot enter ima mode\n");
+		goto err;
+	}
+
+	/* write lsb address of the requested data */
+	value = addr & 0xff;
+	pm_comm_write_byte(sid, FG_MEMIF_MEM_INTF_ADDR_LSB, value, 0);
+
+	/* write msb address of the requested data */
+	value = (addr >> 8) & 0xff;
+	pm_comm_write_byte(sid, FG_MEMIF_MEM_INTF_ADDR_MSB, value, 0);
+
+	/* poll until transaction is completed */
+	/* poll ima is ready */
+	err = fg_check_addr_mask(sid, FG_MEMIF_IMA_OPERATION_STS, IACS_RDY, 1);
+	if(err)
+	{
+		dprintf(INFO,"IACS is not ready cannot set address\n");
+		goto err;
+	}
+
+	/* read start beat count */
+	pm_comm_read_byte_mask(sid, FG_MEMIF_FG_BEAT_COUNT, BEAT_COUNT_MASK, &start_beat_count, 0);
+	/* read the data */
+	pm_comm_read_byte(sid, FG_MEMIF_MEM_INTF_RD_DATA0, &value, 0);
+	*data = value;
+	pm_comm_read_byte(sid, FG_MEMIF_MEM_INTF_RD_DATA1, &value, 0);
+	*data |= value << 8;
+	pm_comm_read_byte(sid, FG_MEMIF_MEM_INTF_RD_DATA2, &value, 0);
+	*data |= value << 16;
+	pm_comm_read_byte(sid, FG_MEMIF_MEM_INTF_RD_DATA3, &value, 0);
+	*data = value << 24;
+
+	/* poll to check there was no error */
+	err = fg_check_addr_mask(sid, FG_MEMIF_IMA_OPERATION_STS, IACS_RDY, 1);
+	if(err)
+	{
+		dprintf(INFO,"IACS is not ready cannot read\n");
+		goto err;
+	}
+
+	pm_comm_read_byte(sid, FG_MEMIF_IMA_EXCEPTION_STS, &value, 0);
+	err = value;
+	if(!err)
+	{
+		*data = ((*data) >> (offset*8)) & (FG_DATA_MASK >> ((FG_DATA_MAX_LEN - len)*8) );
+		pm_comm_read_byte_mask(sid, FG_MEMIF_FG_BEAT_COUNT, BEAT_COUNT_MASK, &end_beat_count, 0);
+		if(start_beat_count != end_beat_count)
+			err = 1;
+	}
+	else
+	{
+		/* error occured */
+		/*perform iacs clear sequence 1'b1 */
+		pm_comm_read_byte(sid, FG_MEMIF_IMA_CFG, &value, 0);
+		value |= IACS_CLR;
+		pm_comm_write_byte(sid, FG_MEMIF_IMA_CFG, value, 0);
+		/* 8'h04 */
+		pm_comm_write_byte(sid, FG_MEMIF_MEM_INTF_ADDR_MSB, 0x04, 0);
+		/* 8'h00 */
+		pm_comm_write_byte(sid, FG_MEMIF_MEM_INTF_WR_DATA3, 0x00, 0);
+		pm_comm_read_byte(sid, FG_MEMIF_MEM_INTF_RD_DATA3, &value, 0);
+		/*perform iacs clear sequence 1'b0 */
+		pm_comm_read_byte(sid, FG_MEMIF_IMA_CFG, &value, 0);
+		value &= ~(IACS_CLR);
+		pm_comm_write_byte(sid, FG_MEMIF_IMA_CFG, value, 0);
+	}
+
+err:
+	pm_comm_write_byte(sid, FG_MEMIF_MEM_INTF_CFG, 0x00, 0);
+
+	return err;
+
+}
diff --git a/dev/pmic/fgsram/rules.mk b/dev/pmic/fgsram/rules.mk
new file mode 100644
index 0000000..261c99a
--- /dev/null
+++ b/dev/pmic/fgsram/rules.mk
@@ -0,0 +1,6 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+INCLUDES += -I$(LOCAL_DIR)/include
+
+OBJS += \
+$(LOCAL_DIR)/pm_fg_sram.o
diff --git a/dev/qpnp_haptic/qpnp_haptic.c b/dev/qpnp_haptic/qpnp_haptic.c
index e1200a1..e472dff 100644
--- a/dev/qpnp_haptic/qpnp_haptic.c
+++ b/dev/qpnp_haptic/qpnp_haptic.c
@@ -32,7 +32,7 @@
 #include <target.h>
 #include <vibrator.h>
 
-#define HAPTIC_BASE (PMI_ADDR_BASE+ 0xC000)
+#define HAPTIC_BASE (PMI_SECOND_SLAVE_ADDR_BASE+ 0xC000)
 #define QPNP_HAP_EN_CTL_REG (HAPTIC_BASE + 0x46)
 #define QPNP_HAP_EN_CTL2_REG (HAPTIC_BASE + 0x48)
 #define QPNP_HAP_ACT_TYPE_REG (HAPTIC_BASE + 0x4C)
diff --git a/include/platform.h b/include/platform.h
index 790b132..b23f125 100644
--- a/include/platform.h
+++ b/include/platform.h
@@ -66,6 +66,7 @@
 int platform_is_msm8909();
 int platform_is_msm8992();
 int platform_is_msm8956();
+uint32_t platform_is_msm8976_v_1_1();
 int boot_device_mask(int);
 uint32_t platform_detect_panel();
 uint32_t platform_get_max_periph();
@@ -76,4 +77,5 @@
 void get_bootloader_version(unsigned char *buf);
 void get_baseband_version(unsigned char *buf);
 bool is_device_locked();
+bool platform_is_mdmcalifornium();
 #endif
diff --git a/include/target.h b/include/target.h
index 6f83b6f..6784206 100644
--- a/include/target.h
+++ b/include/target.h
@@ -24,6 +24,7 @@
  */
 #ifndef __TARGET_H
 #define __TARGET_H
+#include <qmp_phy.h>
 
 /* Target helper functions exposed to USB driver */
 typedef struct {
@@ -88,6 +89,9 @@
 bool target_build_variant_user();
 void pmic_reset_configure(uint8_t reset_type);
 
+struct qmp_reg *target_get_qmp_settings();
+int target_get_qmp_regsize();
+
 #if PON_VIB_SUPPORT
 uint32_t get_vibration_type();
 #endif
diff --git a/platform/mdm9640/acpuclock.c b/platform/mdm9640/acpuclock.c
index 40827eb..99fd7d0 100644
--- a/platform/mdm9640/acpuclock.c
+++ b/platform/mdm9640/acpuclock.c
@@ -35,6 +35,7 @@
 #include <platform/clock.h>
 #include <platform/iomap.h>
 #include <platform/timer.h>
+#include <platform.h>
 
 void clock_config_uart_dm(uint8_t id)
 {
@@ -92,7 +93,11 @@
 		ASSERT(0);
 	}
 
-	ret = clk_get_set_enable("usb30_pipe_clk", 19200000, 1);
+	if (platform_is_mdmcalifornium())
+		ret = clk_get_set_enable("usb30_pipe_clk_mdmcalifornium", 0, 1);
+	else
+		ret = clk_get_set_enable("usb30_pipe_clk", 19200000, 1);
+
 	if(ret)
 	{
 		dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret);
@@ -106,6 +111,20 @@
 		ASSERT(0);
 	}
 
+	ret = clk_get_set_enable("usb30_mock_utmi_clk", 60000000, true);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set usb30_mock_utmi_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	ret = clk_get_set_enable("usb30_sleep_clk", 0, true);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set usb30_sleep_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
 	ret = clk_get_set_enable("usb_phy_cfg_ahb_clk", 0, 1);
 	if(ret)
 	{
@@ -169,12 +188,85 @@
 
 void clock_bumpup_pipe3_clk()
 {
-	int ret = 0;
+	int ret =0;
 
-	ret = clk_get_set_enable("usb30_pipe_clk", 125000000, 0);
+	if (platform_is_mdmcalifornium())
+		ret = clk_get_set_enable("usb30_pipe_clk", 0, true);
+	else
+		ret = clk_get_set_enable("usb30_pipe_clk", 125000000, true);
+
 	if(ret)
 	{
 		dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret);
 		ASSERT(0);
 	}
 }
+
+void clock_reset_usb_phy()
+{
+	int ret;
+
+	struct clk *phy_reset_clk = NULL;
+	struct clk *pipe_reset_clk = NULL;
+	struct clk *master_clk = NULL;
+
+	master_clk = clk_get("usb30_master_clk");
+	ASSERT(master_clk);
+
+	/* Look if phy com clock is present */
+	phy_reset_clk = clk_get("usb30_phy_reset");
+	ASSERT(phy_reset_clk);
+
+	pipe_reset_clk = clk_get("usb30_pipe_clk");
+	ASSERT(pipe_reset_clk);
+
+	/* ASSERT */
+	ret = clk_reset(master_clk, CLK_RESET_ASSERT);
+	if (ret)
+	{
+		dprintf(CRITICAL, "Failed to assert usb30_master_reset clk\n");
+		return;
+	}
+	ret = clk_reset(phy_reset_clk, CLK_RESET_ASSERT);
+
+	if (ret)
+	{
+		dprintf(CRITICAL, "Failed to assert usb30_phy_reset clk\n");
+		goto deassert_master_clk;
+	}
+
+	ret = clk_reset(pipe_reset_clk, CLK_RESET_ASSERT);
+	if (ret)
+	{
+		dprintf(CRITICAL, "Failed to assert usb30_pipe_clk\n");
+		goto deassert_phy_clk;
+	}
+
+	udelay(100);
+
+	/* DEASSERT */
+	ret = clk_reset(pipe_reset_clk, CLK_RESET_DEASSERT);
+	if (ret)
+	{
+		dprintf(CRITICAL, "Failed to deassert usb_pipe_clk\n");
+		return;
+	}
+
+deassert_phy_clk:
+
+	ret = clk_reset(phy_reset_clk, CLK_RESET_DEASSERT);
+	if (ret)
+	{
+		dprintf(CRITICAL, "Failed to deassert usb30_phy_com_reset clk\n");
+		return;
+	}
+deassert_master_clk:
+
+	ret = clk_reset(master_clk, CLK_RESET_DEASSERT);
+	if (ret)
+	{
+		dprintf(CRITICAL, "Failed to deassert usb30_master clk\n");
+		return;
+	}
+
+}
diff --git a/platform/mdm9640/include/platform/clock.h b/platform/mdm9640/include/platform/clock.h
index e450661..7fdf8a7 100644
--- a/platform/mdm9640/include/platform/clock.h
+++ b/platform/mdm9640/include/platform/clock.h
@@ -35,5 +35,6 @@
 void platform_clock_init(void);
 void clock_config_uart_dm(uint8_t id);
 void clock_usb30_init(void);
+void clock_reset_usb_phy();
 
 #endif
diff --git a/platform/mdm9640/include/platform/iomap.h b/platform/mdm9640/include/platform/iomap.h
index f92f556..2a21206 100644
--- a/platform/mdm9640/include/platform/iomap.h
+++ b/platform/mdm9640/include/platform/iomap.h
@@ -170,9 +170,16 @@
 #define USB3_AUX_D                  (CLK_CTL_BASE + 0x5E06C)
 #define USB3_AUX_CBCR               (CLK_CTL_BASE + 0x5E044)
 
+#define USB30_MOCK_UTMI_CBCR        (CLK_CTL_BASE + 0x5E008)
+#define USB30_SLEEP_CBCR            (CLK_CTL_BASE + 0x5E004)
+#define USB30_MOCK_UTMI_CMD_RCGR    (CLK_CTL_BASE + 0x5E020)
+#define USB30_MOCK_UTMI_CFG_RCGR    (CLK_CTL_BASE + 0x5E024)
+
 /* USB 3.0 phy */
 #define USB3_PHY_BCR                (CLK_CTL_BASE + 0x0005E034)
 
+#define USB_30_BCR                  (CLK_CTL_BASE + 0x0005E070)
+
 /* QUSB2 PHY */
 #define QUSB2_PHY_BASE              0x00079000
 #define GCC_QUSB2_PHY_BCR           (CLK_CTL_BASE + 0x00041028)
@@ -197,5 +204,17 @@
 #define APCS_ALIAS0_IPC_INTERRUPT   0xB011008
 /* eMMC Display */
 #define TLMM_EBI2_EMMC_GPIO_CFG     0x01111000
+
+/* QMP rev registers */
+#define USB3_PHY_REVISION_ID0       (QMP_PHY_BASE + 0x988)
+#define USB3_PHY_REVISION_ID1       (QMP_PHY_BASE + 0x98C)
+#define USB3_PHY_REVISION_ID2       (QMP_PHY_BASE + 0x990)
+#define USB3_PHY_REVISION_ID3       (QMP_PHY_BASE + 0x994)
+
 #define EBI2_BOOT_SELECT            0x2
+#define GCC_RX2_USB2_CLKREF_EN      0x01841030
+#define USB3_PHY_STATUS             0x78974
+/* Register for finding out if single ended or differential clock enablement */
+#define TCSR_PHY_CLK_SCHEME_SEL     0x01956044
+
 #endif
diff --git a/platform/mdm9640/mdm9640-clock.c b/platform/mdm9640/mdm9640-clock.c
index f6b85fb..0d4c26f 100644
--- a/platform/mdm9640/mdm9640-clock.c
+++ b/platform/mdm9640/mdm9640-clock.c
@@ -276,10 +276,10 @@
 	},
 };
 
-
 static struct branch_clk gcc_usb30_master_clk =
 {
 	.cbcr_reg     = (uint32_t *) GCC_USB30_MASTER_CBCR,
+	.bcr_reg      = (uint32_t *) USB_30_BCR,
 	.parent       = &usb30_master_clk_src.c,
 
 	.c = {
@@ -319,6 +319,19 @@
 	},
 };
 
+
+static struct branch_clk gcc_usb30_pipe_clk_mdmcalifornium = {
+	.bcr_reg      = (uint32_t *) USB3_PIPE_BCR,
+	.cbcr_reg     = (uint32_t *) USB3_PIPE_CBCR,
+	.has_sibling  = 1,
+	.halt_check   = 0,
+
+	.c = {
+		.dbg_name = "usb30_pipe_clk_mdmcalifornium",
+		.ops      = &clk_ops_branch,
+	},
+};
+
 static struct clk_freq_tbl ftbl_gcc_usb30_aux_clk[] = {
 	F(   1000000,         cxo,    1,    5,    96),
 	F_END
@@ -369,6 +382,47 @@
 	},
 };
 
+static struct clk_freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = {
+	F(  60000000, gpll0,   10,    0,     0),
+	F_END
+};
+
+static struct rcg_clk usb30_mock_utmi_clk_src = {
+	.cmd_reg      = (uint32_t *) USB30_MOCK_UTMI_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) USB30_MOCK_UTMI_CFG_RCGR,
+	.set_rate     = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl     = ftbl_gcc_usb30_mock_utmi_clk_src,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "usb30_mock_utmi_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct branch_clk gcc_usb30_mock_utmi_clk = {
+	.cbcr_reg    = (uint32_t *) USB30_MOCK_UTMI_CBCR,
+	.has_sibling = 0,
+	.parent      = &usb30_mock_utmi_clk_src.c,
+
+	.c = {
+		.dbg_name = "usb30_mock_utmi_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk gcc_usb30_sleep_clk = {
+	.cbcr_reg    = (uint32_t *) USB30_SLEEP_CBCR,
+	.has_sibling = 1,
+
+	.c = {
+		.dbg_name = "usb30_sleep_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+
+
 static struct clk_lookup msm_clocks_9640[] =
 {
 	CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
@@ -380,12 +434,15 @@
 	CLK_LOOKUP("usb30_iface_clk",  gcc_sys_noc_usb30_axi_clk.c),
 	CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
 	CLK_LOOKUP("usb30_pipe_clk",   gcc_usb30_pipe_clk.c),
+	CLK_LOOKUP("usb30_pipe_clk_mdmcalifornium",   gcc_usb30_pipe_clk_mdmcalifornium.c),
 	CLK_LOOKUP("usb30_aux_clk",    gcc_usb30_aux_clk.c),
 
 	CLK_LOOKUP("usb2b_phy_sleep_clk", gcc_usb2a_phy_sleep_clk.c),
 	CLK_LOOKUP("usb30_phy_reset",     gcc_usb30_phy_reset.c),
 
+	CLK_LOOKUP("usb30_mock_utmi_clk", gcc_usb30_mock_utmi_clk.c),
 	CLK_LOOKUP("usb_phy_cfg_ahb_clk", gcc_usb_phy_cfg_ahb_clk.c),
+	CLK_LOOKUP("usb30_sleep_clk",     gcc_usb30_sleep_clk.c),
 };
 
 void platform_clock_init(void)
diff --git a/platform/mdm9640/platform.c b/platform/mdm9640/platform.c
index 6ccbe19..f69053c 100644
--- a/platform/mdm9640/platform.c
+++ b/platform/mdm9640/platform.c
@@ -156,14 +156,45 @@
 	return phys_addr;
 }
 
+
+bool platform_is_mdmcalifornium()
+{
+	uint32_t platform_id = board_platform_id();
+	bool ret;
+
+	switch(platform_id)
+	{
+		case MDMCALIFORNIUM1:
+		case MDMCALIFORNIUM2:
+		case MDMCALIFORNIUM3:
+		case MDMCALIFORNIUM4:
+				ret = true;
+				break;
+		default:
+				ret = false;
+	};
+
+	return ret;
+}
+
 uint32_t platform_boot_config()
 {
 	uint32_t boot_config;
 
-	if (board_soc_version() >= 0x20000)
+	if (platform_is_mdmcalifornium())
+		boot_config = BOOT_CONFIG_REG_V2;
+	/* Else the platform is 9x45 */
+	else if (board_soc_version() >= 0x20000)
 		boot_config = BOOT_CONFIG_REG_V2;
 	else
 		boot_config = BOOT_CONFIG_REG_V1;
 
 	return boot_config;
 }
+
+uint32_t platform_get_qmp_rev()
+{
+	return readl(USB3_PHY_REVISION_ID3) << 24 | readl(USB3_PHY_REVISION_ID2) << 16 |
+		   readl(USB3_PHY_REVISION_ID1) << 8 | readl(USB3_PHY_REVISION_ID0);
+}
+
diff --git a/platform/mdmfermium/acpuclock.c b/platform/mdmfermium/acpuclock.c
index 7463222..bd068ad 100644
--- a/platform/mdmfermium/acpuclock.c
+++ b/platform/mdmfermium/acpuclock.c
@@ -37,11 +37,81 @@
 
 void hsusb_clock_init(void)
 {
+	int ret;
+	struct clk *iclk, *cclk;
 
+	ret = clk_get_set_enable("usb_iface_clk", 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	ret = clk_get_set_enable("usb_core_clk", 133330000, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	mdelay(20);
+
+	iclk = clk_get("usb_iface_clk");
+	cclk = clk_get("usb_core_clk");
+
+	clk_disable(iclk);
+	clk_disable(cclk);
+
+	mdelay(20);
+
+	/* Start the block reset for usb */
+	writel(1, USB_HS_BCR);
+
+	mdelay(20);
+
+	/* Take usb block out of reset */
+	writel(0, USB_HS_BCR);
+
+	mdelay(20);
+
+	ret = clk_enable(iclk);
+
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	ret = clk_enable(cclk);
+
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+		ASSERT(0);
+	}
 }
 
 /* Configure UART clock based on the UART block id*/
 void clock_config_uart_dm(uint8_t id)
 {
+	int ret;
+	char iclk[64];
+	char cclk[64];
 
+	snprintf(iclk, sizeof(iclk), "uart%u_iface_clk", id);
+	snprintf(cclk, sizeof(cclk), "uart%u_core_clk", id);
+
+	ret = clk_get_set_enable(iclk, 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set %s ret = %d\n", iclk, ret);
+		ASSERT(0);
+	}
+
+	ret = clk_get_set_enable(cclk, 7372800, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set %s ret = %d\n", cclk, ret);
+		ASSERT(0);
+	}
 }
diff --git a/platform/mdmfermium/gpio.c b/platform/mdmfermium/gpio.c
index fba2c76..6f9bc3c 100644
--- a/platform/mdmfermium/gpio.c
+++ b/platform/mdmfermium/gpio.c
@@ -68,10 +68,10 @@
 void gpio_config_uart_dm(uint8_t id)
 {
 	/* configure rx gpio */
-	gpio_tlmm_config(5, 2, GPIO_INPUT, GPIO_NO_PULL,
+	gpio_tlmm_config(9, 2, GPIO_INPUT, GPIO_NO_PULL,
 				GPIO_8MA, GPIO_DISABLE);
 
 	/* configure tx gpio */
-	gpio_tlmm_config(4, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+	gpio_tlmm_config(8, 2, GPIO_OUTPUT, GPIO_NO_PULL,
 				GPIO_8MA, GPIO_DISABLE);
 }
diff --git a/platform/mdmfermium/include/platform/iomap.h b/platform/mdmfermium/include/platform/iomap.h
index 852e5a9..205cd19 100644
--- a/platform/mdmfermium/include/platform/iomap.h
+++ b/platform/mdmfermium/include/platform/iomap.h
@@ -64,6 +64,7 @@
 
 #define BLSP1_UART0_BASE                   (PERIPH_SS_BASE + 0x000AF000)
 #define BLSP1_UART1_BASE                   (PERIPH_SS_BASE + 0x000B0000)
+#define BLSP1_UART5_BASE                   (PERIPH_SS_BASE + 0x000B3000)
 #define MSM_USB_BASE                       (PERIPH_SS_BASE + 0x000D9000)
 
 #define CLK_CTL_BASE                       0x1800000
@@ -87,18 +88,18 @@
 
 
 /* GPLL */
-#define GPLL0_STATUS                       (CLK_CTL_BASE + 0x21024)
+#define GPLL0_MODE                         (CLK_CTL_BASE + 0x21000)
 #define APCS_GPLL_ENA_VOTE                 (CLK_CTL_BASE + 0x45000)
 #define APCS_CLOCK_BRANCH_ENA_VOTE         (CLK_CTL_BASE + 0x45004)
 
 /* UART */
 #define BLSP1_AHB_CBCR                     (CLK_CTL_BASE + 0x1008)
-#define BLSP1_UART2_APPS_CBCR              (CLK_CTL_BASE + 0x302C)
-#define BLSP1_UART2_APPS_CMD_RCGR          (CLK_CTL_BASE + 0x3034)
-#define BLSP1_UART2_APPS_CFG_RCGR          (CLK_CTL_BASE + 0x3038)
-#define BLSP1_UART2_APPS_M                 (CLK_CTL_BASE + 0x303C)
-#define BLSP1_UART2_APPS_N                 (CLK_CTL_BASE + 0x3040)
-#define BLSP1_UART2_APPS_D                 (CLK_CTL_BASE + 0x3044)
+#define BLSP1_UART5_APPS_CBCR              (CLK_CTL_BASE + 0x603c)
+#define BLSP1_UART5_APPS_CMD_RCGR          (CLK_CTL_BASE + 0x6044)
+#define BLSP1_UART5_APPS_CFG_RCGR          (CLK_CTL_BASE + 0x6048)
+#define BLSP1_UART5_APPS_M                 (CLK_CTL_BASE + 0x604C)
+#define BLSP1_UART5_APPS_N                 (CLK_CTL_BASE + 0x6050)
+#define BLSP1_UART5_APPS_D                 (CLK_CTL_BASE + 0x6054)
 
 /* USB */
 #define USB_HS_BCR                         (CLK_CTL_BASE + 0x41000)
diff --git a/platform/mdmfermium/mdmfermium-clock.c b/platform/mdmfermium/mdmfermium-clock.c
index 235d40f..35fbd27 100644
--- a/platform/mdmfermium/mdmfermium-clock.c
+++ b/platform/mdmfermium/mdmfermium-clock.c
@@ -100,8 +100,8 @@
 {
 	.en_reg       = (void *) APCS_GPLL_ENA_VOTE,
 	.en_mask      = BIT(0),
-	.status_reg   = (void *) GPLL0_STATUS,
-	.status_mask  = BIT(17),
+	.status_reg   = (void *) GPLL0_MODE,
+	.status_mask  = BIT(30),
 	.parent       = &cxo_clk_src.c,
 
 	.c = {
@@ -112,7 +112,7 @@
 };
 
 /* UART Clocks */
-static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_2_apps_clk[] =
+static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart5_apps_clk[] =
 {
 	F( 3686400,  gpll0,    1,  72,  15625),
 	F( 7372800,  gpll0,    1, 144,  15625),
@@ -132,16 +132,16 @@
 	F_END
 };
 
-static struct rcg_clk blsp1_uart2_apps_clk_src =
+static struct rcg_clk blsp1_uart5_apps_clk_src =
 {
-	.cmd_reg      = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
-	.cfg_reg      = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR,
-	.m_reg        = (uint32_t *) BLSP1_UART2_APPS_M,
-	.n_reg        = (uint32_t *) BLSP1_UART2_APPS_N,
-	.d_reg        = (uint32_t *) BLSP1_UART2_APPS_D,
+	.cmd_reg      = (uint32_t *) BLSP1_UART5_APPS_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) BLSP1_UART5_APPS_CFG_RCGR,
+	.m_reg        = (uint32_t *) BLSP1_UART5_APPS_M,
+	.n_reg        = (uint32_t *) BLSP1_UART5_APPS_N,
+	.d_reg        = (uint32_t *) BLSP1_UART5_APPS_D,
 
 	.set_rate     = clock_lib2_rcg_set_rate_mnd,
-	.freq_tbl     = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
+	.freq_tbl     = ftbl_gcc_blsp1_2_uart5_apps_clk,
 	.current_freq = &rcg_dummy_freq,
 
 	.c = {
@@ -150,13 +150,13 @@
 	},
 };
 
-static struct branch_clk gcc_blsp1_uart2_apps_clk =
+static struct branch_clk gcc_blsp1_uart5_apps_clk =
 {
-	.cbcr_reg     = (uint32_t *) BLSP1_UART2_APPS_CBCR,
-	.parent       = &blsp1_uart2_apps_clk_src.c,
+	.cbcr_reg     = (uint32_t *) BLSP1_UART5_APPS_CBCR,
+	.parent       = &blsp1_uart5_apps_clk_src.c,
 
 	.c = {
-		.dbg_name = "gcc_blsp1_uart2_apps_clk",
+		.dbg_name = "gcc_blsp1_uart5_apps_clk",
 		.ops      = &clk_ops_branch,
 	},
 };
@@ -219,8 +219,8 @@
 /* Clock lookup table */
 static struct clk_lookup mdm_clocks_fermium[] =
 {
-	CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
-	CLK_LOOKUP("uart2_core_clk",  gcc_blsp1_uart2_apps_clk.c),
+	CLK_LOOKUP("uart5_iface_clk", gcc_blsp1_ahb_clk.c),
+	CLK_LOOKUP("uart5_core_clk",  gcc_blsp1_uart5_apps_clk.c),
 
 	CLK_LOOKUP("usb_iface_clk",  gcc_usb_hs_ahb_clk.c),
 	CLK_LOOKUP("usb_core_clk",   gcc_usb_hs_system_clk.c),
diff --git a/platform/msm8952/acpuclock.c b/platform/msm8952/acpuclock.c
index e3aaec3..ec37789 100644
--- a/platform/msm8952/acpuclock.c
+++ b/platform/msm8952/acpuclock.c
@@ -132,7 +132,12 @@
 	}
 	else if(freq == MMC_CLK_192MHZ)
 	{
-		ret = clk_get_set_enable(clk_name, 192000000, 1);
+		if (platform_is_msm8956() && platform_is_msm8976_v_1_1())
+
+			ret = clk_get_set_enable(clk_name, 186400000, 1);
+		else
+
+			ret = clk_get_set_enable(clk_name, 192000000, 1);
 	}
 	else if(freq == MMC_CLK_200MHZ)
 	{
@@ -140,7 +145,12 @@
 	}
 	else if(freq == MMC_CLK_400MHZ)
 	{
-		ret = clk_get_set_enable(clk_name, 384000000, 1);
+		if (platform_is_msm8956() && platform_is_msm8976_v_1_1())
+
+			ret = clk_get_set_enable(clk_name, 372800000, 1);
+		else
+
+			ret = clk_get_set_enable(clk_name, 384000000, 1);
 	}
 	else
 	{
@@ -312,16 +322,28 @@
 }
 
 /* Configure all the branch clocks needed by the DSI controller */
-void gcc_dsi_clocks_enable(uint32_t flags, uint8_t pclk0_m,
+void gcc_dsi_clocks_enable(uint32_t flags, bool use_dsi1_pll, uint8_t pclk0_m,
 		uint8_t pclk0_n, uint8_t pclk0_d)
 {
 	int ret;
+	int dsi0_cfg_rcgr, dsi1_cfg_rcgr = 0;
+
+	dsi0_cfg_rcgr = BIT(8); /* DSI0 can only be sourced from PLL0 */
+
+	/*
+	 * DSI1<->PLL1 for 1.) 8956 v1.0 always 2.) Single DSI cases on DSI1
+	 * DSI1<->PLL0 for 8956 v1.1 split DSI cases
+	 */
+	if (!platform_is_msm8976_v_1_1() || use_dsi1_pll)
+		dsi1_cfg_rcgr = BIT(8);
+	else if (flags == (MMSS_DSI_CLKS_FLAG_DSI0 | MMSS_DSI_CLKS_FLAG_DSI1))
+		dsi1_cfg_rcgr = BIT(8) | BIT(9);
 
 	if (flags & MMSS_DSI_CLKS_FLAG_DSI0) {
 		/* Enable DSI0 branch clocks */
 
 		/* Set the source for DSI0 byte RCG */
-		writel(0x100, DSI_BYTE0_CFG_RCGR);
+		writel(dsi0_cfg_rcgr, DSI_BYTE0_CFG_RCGR);
 		/* Set the update RCG bit */
 		writel(0x1, DSI_BYTE0_CMD_RCGR);
 		rcg_update_config(DSI_BYTE0_CMD_RCGR);
@@ -331,7 +353,7 @@
 
 		/* Configure Pixel clock */
 		/* Set the source for DSI0 pixel RCG */
-		writel(0x100, DSI_PIXEL0_CFG_RCGR);
+		writel(dsi0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
 		/* Set the MND for DSI0 pixel clock */
 		writel(pclk0_m, DSI_PIXEL0_M);
 		writel(pclk0_n, DSI_PIXEL0_N);
@@ -355,7 +377,7 @@
 		/* Enable DSI1 branch clocks */
 
 		/* Set the source for DSI1 byte RCG */
-		writel(0x100, DSI_BYTE1_CFG_RCGR);
+		writel(dsi1_cfg_rcgr, DSI_BYTE1_CFG_RCGR);
 		/* Set the update RCG bit */
 		writel(0x1, DSI_BYTE1_CMD_RCGR);
 		rcg_update_config(DSI_BYTE1_CMD_RCGR);
@@ -365,7 +387,7 @@
 
 		/* Configure Pixel clock */
 		/* Set the source for DSI1 pixel RCG */
-		writel(0x100, DSI_PIXEL1_CFG_RCGR);
+		writel(dsi1_cfg_rcgr, DSI_PIXEL1_CFG_RCGR);
 		/* Set the MND for DSI1 pixel clock */
 		writel(pclk0_m, DSI_PIXEL1_M);
 		writel(pclk0_n, DSI_PIXEL1_N);
diff --git a/platform/msm8952/include/platform/clock.h b/platform/msm8952/include/platform/clock.h
index f6e962a..c9e8cc7 100644
--- a/platform/msm8952/include/platform/clock.h
+++ b/platform/msm8952/include/platform/clock.h
@@ -95,7 +95,7 @@
 void mdss_bus_clocks_disable(void);
 void mdp_clock_enable(void);
 void mdp_clock_disable(void);
-void gcc_dsi_clocks_enable(uint32_t flags, uint8_t pclk0_m,
+void gcc_dsi_clocks_enable(uint32_t flags,  bool use_dsi1_pll, uint8_t pclk0_m,
 		uint8_t pclk0_n, uint8_t pclk0_d);
 void gcc_dsi_clocks_disable(uint32_t flags);
 #endif
diff --git a/platform/msm8952/include/platform/iomap.h b/platform/msm8952/include/platform/iomap.h
index ce98076..41f0f83 100644
--- a/platform/msm8952/include/platform/iomap.h
+++ b/platform/msm8952/include/platform/iomap.h
@@ -70,8 +70,12 @@
 
 #define CLK_CTL_BASE                       0x1800000
 
-#define PMI_SLAVE_ID 3
-#define PMI_ADDR_BASE (PMI_SLAVE_ID << 16)
+#define PMI_SLAVE_BASE           2
+#define PMI_FIRST_SLAVE_OFFSET   0
+#define PMI_SECOND_SLAVE_OFFSET  1
+
+#define PMI_FIRST_SLAVE_ADDR_BASE   (( PMI_SLAVE_BASE + PMI_FIRST_SLAVE_OFFSET ) << 16)
+#define PMI_SECOND_SLAVE_ADDR_BASE  (( PMI_SLAVE_BASE + PMI_SECOND_SLAVE_OFFSET) << 16)
 
 #define SPMI_BASE                          0x02000000
 #define SPMI_GENI_BASE                     (SPMI_BASE + 0xA000)
@@ -98,6 +102,7 @@
 
 /* GPLL */
 #define GPLL0_STATUS                       (CLK_CTL_BASE + 0x2101C)
+#define GPLL2_STATUS                       (CLK_CTL_BASE + 0x4A01C)
 #define APCS_GPLL_ENA_VOTE                 (CLK_CTL_BASE + 0x45000)
 #define APCS_CLOCK_BRANCH_ENA_VOTE         (CLK_CTL_BASE + 0x45004)
 #define GPLL4_MODE                         (CLK_CTL_BASE + 0x24000)
diff --git a/platform/msm8952/msm8952-clock.c b/platform/msm8952/msm8952-clock.c
index b87406d..3214895 100644
--- a/platform/msm8952/msm8952-clock.c
+++ b/platform/msm8952/msm8952-clock.c
@@ -39,6 +39,7 @@
 /* Mux source select values */
 #define cxo_source_val    0
 #define gpll0_source_val  1
+#define gpll2_source_val  4
 #define gpll4_source_val  2
 #define cxo_mm_source_val 0
 #define gpll0_mm_source_val 6
@@ -112,6 +113,21 @@
 	},
 };
 
+static struct pll_vote_clk gpll2_clk_src =
+{
+	.en_reg       = (void *) APCS_GPLL_ENA_VOTE,
+	.en_mask      = BIT(2),
+	.status_reg   = (void *) GPLL2_STATUS,
+	.status_mask  = BIT(17),
+	.parent       = &cxo_clk_src.c,
+
+	.c = {
+		.rate     = 932000000,
+		.dbg_name = "gpll2_clk_src",
+		.ops      = &clk_ops_pll_vote,
+	},
+};
+
 static struct pll_vote_clk gpll4_clk_src =
 {
 	.en_reg       = (void *) APCS_GPLL_ENA_VOTE,
@@ -157,6 +173,21 @@
 	F_END
 };
 
+/* SDCC Clocks for version 8976 v 1.1*/
+static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk_8976_v_1_1[] =
+{
+	F(   144000,    cxo,  16,   3,  25),
+	F(   400000,    cxo,  12,   1,   4),
+	F( 20000000,  gpll0,  10,   1,   4),
+	F( 25000000,  gpll0,  16,   1,   2),
+	F( 50000000,  gpll0,  16,   0,   0),
+	F(100000000,  gpll0,   8,   0,   0),
+	F(177770000,  gpll0, 4.5,   0,   0),
+	F(186400000,  gpll2,   5,   0,   0),
+	F(372800000,  gpll2, 2.5,   0,   0),
+	F_END
+};
+
 static struct rcg_clk sdcc1_apps_clk_src =
 {
 	.cmd_reg      = (uint32_t *) SDCC1_CMD_RCGR,
@@ -594,9 +625,18 @@
 	mdss_mdp_clk_src.freq_tbl = ftbl_mdp_clk_8956;
 }
 
+void msm8976_v_1_1_sdcc_clock_modify()
+{
+	sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_8976_v_1_1;
+}
+
 void platform_clock_init(void)
 {
-	if (platform_is_msm8956())
+	if (platform_is_msm8956()) {
 		msm8956_clock_override();
+		if (platform_is_msm8976_v_1_1())
+			/*freq and GPLL change for 8976 v1.1 */
+			msm8976_v_1_1_sdcc_clock_modify();
+	}
 	clk_init(msm_clocks_8952, ARRAY_SIZE(msm_clocks_8952));
 }
diff --git a/platform/msm8952/platform.c b/platform/msm8952/platform.c
index 2da8ced..5a8e716 100644
--- a/platform/msm8952/platform.c
+++ b/platform/msm8952/platform.c
@@ -41,6 +41,7 @@
 #include <platform.h>
 #include <target/display.h>
 
+#define MSM8976_SOC_V11 0x10001
 #define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
 #define APPS_SS_SIZE   ((APPS_SS_END - APPS_SS_BASE)/MB)
 
@@ -195,3 +196,14 @@
 
 	return ret;
 }
+
+uint32_t platform_is_msm8976_v_1_1()
+{
+	uint32_t soc_ver = board_soc_version();
+	uint32_t ret = 0;
+
+	if(soc_ver == MSM8976_SOC_V11)
+		ret = 1;
+
+	return ret;
+}
diff --git a/platform/msm8996/include/platform/iomap.h b/platform/msm8996/include/platform/iomap.h
index 3fc75dd..50d2542 100644
--- a/platform/msm8996/include/platform/iomap.h
+++ b/platform/msm8996/include/platform/iomap.h
@@ -85,6 +85,13 @@
 /* Clocks */
 #define CLK_CTL_BASE                0x300000
 
+#define PMI_SLAVE_BASE           2
+#define PMI_FIRST_SLAVE_OFFSET   0
+#define PMI_SECOND_SLAVE_OFFSET  1
+
+#define PMI_FIRST_SLAVE_ADDR_BASE   (( PMI_SLAVE_BASE + PMI_FIRST_SLAVE_OFFSET ) << 16)
+#define PMI_SECOND_SLAVE_ADDR_BASE  (( PMI_SLAVE_BASE + PMI_SECOND_SLAVE_OFFSET) << 16)
+
 /* GPLL */
 #define GPLL0_MODE                  (CLK_CTL_BASE + 0x0000)
 #define GPLL4_MODE                  (CLK_CTL_BASE + 0x77000)
diff --git a/platform/msm_shared/boot_verifier.c b/platform/msm_shared/boot_verifier.c
index 6a5f5f3..953e892 100644
--- a/platform/msm_shared/boot_verifier.c
+++ b/platform/msm_shared/boot_verifier.c
@@ -533,6 +533,12 @@
 		goto verify_image_error;
 	}
 
+	if (sig_len > ASN1_SIGNATURE_BUFFER_SZ)
+	{
+		dprintf(CRITICAL, "boot_verifier: Signature length exceeds size signature buffer\n");
+		goto verify_image_error;
+	}
+
 	if((sig = d2i_VERIFIED_BOOT_SIG(NULL, (const unsigned char **) &sig_addr, sig_len)) == NULL)
 	{
 		dprintf(CRITICAL,
diff --git a/platform/msm_shared/clock_lib2.c b/platform/msm_shared/clock_lib2.c
index ad088cb..50042f2 100644
--- a/platform/msm_shared/clock_lib2.c
+++ b/platform/msm_shared/clock_lib2.c
@@ -32,7 +32,7 @@
 #include <clock.h>
 #include <clock_pll.h>
 #include <clock_lib2.h>
-
+#include <platform/timer.h>
 
 /*=============== CXO clock ops =============*/
 int cxo_clk_enable(struct clk *clk)
@@ -55,14 +55,32 @@
 {
 	int rc = 0;
 	uint32_t cbcr_val;
+	int retry = 100;
 	struct branch_clk *bclk = to_branch_clk(clk);
 
 	cbcr_val  = readl(bclk->cbcr_reg);
 	cbcr_val |= CBCR_BRANCH_ENABLE_BIT;
 	writel(cbcr_val, bclk->cbcr_reg);
 
+	/* Some clocks do not need to check the enable status, return
+	 * if the halt_check is not set
+	 */
+	if (!bclk->halt_check)
+		return rc;
+
 	/* wait until status shows it is enabled */
-	while(readl(bclk->cbcr_reg) & CBCR_BRANCH_OFF_BIT);
+	while(readl(bclk->cbcr_reg) & CBCR_BRANCH_OFF_BIT)
+	{
+		/* Add 100 ms of time out, bail out if the clock is not enable
+		 * within 100 ms */
+		if (!retry)
+		{
+			rc = 1;
+			break;
+		}
+		retry--;
+		mdelay(1);
+	}
 
 	return rc;
 }
diff --git a/platform/msm_shared/include/mmc_sdhci.h b/platform/msm_shared/include/mmc_sdhci.h
index 54f09ee..5461b49 100644
--- a/platform/msm_shared/include/mmc_sdhci.h
+++ b/platform/msm_shared/include/mmc_sdhci.h
@@ -215,7 +215,7 @@
     ({                                                    \
      uint32_t indx = (start) / (size_of);                 \
      uint32_t offset = (start) % (size_of);               \
-     uint32_t mask = (((len)<(size_of))? 1ULL<<(len):0) - 1; \
+     unsigned long long mask = (((len)<(size_of))? 1ULL<<(len):0) - 1; \
      uint32_t unpck = array[indx] >> offset;              \
      uint32_t indx2 = ((start) + (len) - 1) / (size_of);  \
      if(indx2 > indx)                                     \
diff --git a/platform/msm_shared/mmc_sdhci.c b/platform/msm_shared/mmc_sdhci.c
index 7b4ed5f..12fb661 100644
--- a/platform/msm_shared/mmc_sdhci.c
+++ b/platform/msm_shared/mmc_sdhci.c
@@ -1379,7 +1379,9 @@
 	/* Card AU size in sectors */
 	card->ssr.au_size = 1 << (au_size + 4);
 	card->ssr.num_aus = UNPACK_BITS(status, MMC_SD_ERASE_SIZE_BIT, MMC_SD_ERASE_SIZE_LEN, 32);
-
+	/*if num_aus is 0 then host should assign number of AU erased at a time*/
+	if (!card->ssr.num_aus)
+		card->ssr.num_aus = 0x10;
 	return 0;
 }
 
@@ -2384,15 +2386,17 @@
 		dprintf(CRITICAL, "card deselect error: %s\n", __func__);
 		return;
 	}
+	if(MMC_CARD_MMC(card)){
+		/*CMD5 is reserved in SD card */
+		cmd.cmd_index = CMD5_SLEEP_AWAKE;
+		cmd.argument = (card->rca << MMC_CARD_RCA_BIT) | MMC_CARD_SLEEP;
+		cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
+		cmd.resp_type = SDHCI_CMD_RESP_R1B;
 
-	cmd.cmd_index = CMD5_SLEEP_AWAKE;
-	cmd.argument = (card->rca << MMC_CARD_RCA_BIT) | MMC_CARD_SLEEP;
-	cmd.cmd_type = SDHCI_CMD_TYPE_NORMAL;
-	cmd.resp_type = SDHCI_CMD_RESP_R1B;
-
-	/* send command */
-	if(sdhci_send_command(&dev->host, &cmd))
-		dprintf(CRITICAL, "card sleep error: %s\n", __func__);
+		/* send command */
+		if(sdhci_send_command(&dev->host, &cmd))
+			dprintf(CRITICAL, "card sleep error: %s\n", __func__);
+	}
 }
 
 /*
diff --git a/platform/msm_shared/qmp_usb30_phy.c b/platform/msm_shared/qmp_usb30_phy.c
index 56b009a..a558cea 100644
--- a/platform/msm_shared/qmp_usb30_phy.c
+++ b/platform/msm_shared/qmp_usb30_phy.c
@@ -37,6 +37,7 @@
 #include <debug.h>
 #include <qtimer.h>
 #include <platform.h>
+#include <target.h>
 
 #define HS_PHY_COMMON_CTRL             0xEC
 #define USE_CORECLK                    BIT(14)
@@ -256,12 +257,30 @@
 void usb30_qmp_phy_init()
 {
 	int timeout = QMP_PHY_MAX_TIMEOUT;
-	uint32_t rev_id = 0;
 	uint32_t phy_status = 0;
 	uint32_t qmp_reg_size;
 	uint32_t i;
 
-	rev_id = platform_get_qmp_rev();
+
+#if USE_TARGET_QMP_SETTINGS
+	struct qmp_reg *target_qmp_settings = NULL;
+	qmp_reg_size = target_get_qmp_regsize();
+	target_qmp_settings = target_get_qmp_settings();
+	if (qmp_reg_size && target_qmp_settings)
+	{
+		for (i = 0 ; i < qmp_reg_size; i++)
+		{
+			/* As per the hw document we need to add a delay of 1 ms after setting
+			 * QSERDES_COM_RESETSM_CNTRL2 and before setting QSERDES_COM_CMN_CONFIG */
+			if (i == 7)
+				mdelay(1);
+			writel(target_qmp_settings[i].val, QMP_PHY_BASE + target_qmp_settings[i].off);
+		}
+	goto phy_status;
+	}
+#endif
+
+	uint32_t rev_id = platform_get_qmp_rev();
 
 	/* Sequence as per HPG */
 	writel(0x01, QMP_PHY_BASE + PCIE_USB3_PHY_POWER_DOWN_CONTROL);
@@ -342,12 +361,25 @@
 		writel(0x03, QMP_PHY_BASE + PCIE_USB3_PHY_START);
 	}
 
-	if (rev_id >= 0x20000000)
-		phy_status = 0x77c;
-	else
-		phy_status = 0x728;
+#if USE_TARGET_QMP_SETTINGS
+phy_status:
+#endif
 
-	while ((readl(QMP_PHY_BASE + phy_status) & PHYSTATUS))
+	/* For future targets defined USB3_PHY_STATUS in the iomap.h
+	 * Initial version of driver was written thinking phy_status register
+	 * address would not change, but the address keeps changing for every chip
+	 * so better get the address from iomap amd keep the backward compatibility
+	 */
+#if USB3_PHY_STATUS
+	phy_status = USB3_PHY_STATUS;
+#else
+	if (rev_id >= 0x20000000)
+		phy_status = QMP_PHY_BASE + 0x77c;
+	else
+		phy_status = QMP_PHY_BASE + 0x728;
+#endif
+
+	while ((readl(phy_status) & PHYSTATUS))
 	{
 		udelay(1);
 		timeout--;
diff --git a/platform/msm_shared/qpic_nand.c b/platform/msm_shared/qpic_nand.c
index c39d584..d2b6044 100644
--- a/platform/msm_shared/qpic_nand.c
+++ b/platform/msm_shared/qpic_nand.c
@@ -77,6 +77,7 @@
 	{0x9590DC2C, 0x56,     0xFFFFFFFF, 0x0,      0x10000000,    0,  2048,   0x00020000,        0x40,   0},
 	{0x1590aa98, 0x76,     0xFFFFFFFF, 0x0,      0x10000000,    0,  2048,   0x00020000,        0x80,   1},
 	{0x2690A32C, 0x64,     0xFFFFFFFF, 0x0,      0x20000000,    0,  4096,   0x00040000,        0xE0,   1},
+	{0x2690AC98, 0x81676,  0xFFFFFFFF, 0x0,      0x20000000,    0,  4096,   0x00040000,        0xE0,   1},
 	/* Note: Width flag is 0 for 8 bit Flash and 1 for 16 bit flash   */
 };
 
diff --git a/platform/msm_shared/qusb2_phy.c b/platform/msm_shared/qusb2_phy.c
index edc0ecc..c682727 100644
--- a/platform/msm_shared/qusb2_phy.c
+++ b/platform/msm_shared/qusb2_phy.c
@@ -32,6 +32,7 @@
 #include <bits.h>
 #include <debug.h>
 #include <qtimer.h>
+#include <platform.h>
 
 __WEAK int platform_is_msm8994()
 {
@@ -43,11 +44,18 @@
 	return 0;
 }
 
+__WEAK int platform_is_mdmcalifornium()
+{
+	return 0;
+}
+
 void qusb2_phy_reset(void)
 {
 	uint32_t val;
 	/* Default tune value */
 	uint8_t tune2 = 0xB3;
+	int retry = 100;
+	int se_clock = 1;
 
 	/* Disable the ref clock before phy reset */
 #if GCC_RX2_USB2_CLKREF_EN
@@ -67,7 +75,7 @@
 	/* set CLAMP_N_EN and stay with disabled USB PHY */
 	writel(0x23, QUSB2PHY_PORT_POWERDOWN);
 
-	if (platform_is_msm8996())
+	if (platform_is_msm8996() || platform_is_mdmcalifornium())
 	{
 		writel(0xF8, QUSB2PHY_PORT_TUNE1);
 		/* Upper nibble of tune2 register should be updated based on the fuse value.
@@ -88,7 +96,6 @@
 		writel(0x79, QUSB2PHY_PLL_USER_CTL1);
 		writel(0x21, QUSB2PHY_PLL_USER_CTL2);
 		writel(0x14, QUSB2PHY_PORT_TEST2);
-		writel(0x80, QUSB2PHY_PLL_TEST);
 		writel(0x9F, QUSB2PHY_PLL_AUTOPGM_CTL1);
 		writel(0x00, QUSB2PHY_PLL_PWR_CTL);
 	}
@@ -107,27 +114,47 @@
 		writel(0x85, QUSB2PHY_PORT_TUNE4);
 	}
 
-	/* Wait for tuning params to take effect right before re-enabling power*/
-	udelay(10);
-
-	/* Disable the PHY */
-	writel(0x23, QUSB2PHY_PORT_POWERDOWN);
 	/* Enable ULPI mode */
 	if (platform_is_msm8994())
 		writel(0x0,  QUSB2PHY_PORT_UTMI_CTRL2);
-	/* Enable PHY */
 	/* set CLAMP_N_EN and USB PHY is enabled*/
 	writel(0x22, QUSB2PHY_PORT_POWERDOWN);
 	udelay(150);
 
-	/* Check PLL status */
-	if (!(readl(QUSB2PHY_PLL_STATUS) & QUSB2PHY_PLL_LOCK))
-	{
-		dprintf(CRITICAL, "QUSB2PHY failed to lock: %d", readl(QUSB2PHY_PLL_STATUS));
-	}
-
-#if GCC_RX2_USB2_CLKREF_EN
-	writel((readl(GCC_RX2_USB2_CLKREF_EN) | 0x1), GCC_RX2_USB2_CLKREF_EN);
-	dmb();
+	/* TCSR register bit 0 indicates whether single ended clock
+	 * or differential clock configuration is enabled. Based on the
+	 * configuration set the PLL_TEST register.
+	 */
+#if TCSR_PHY_CLK_SCHEME_SEL
+	se_clock = readl(TCSR_PHY_CLK_SCHEME_SEL) & 0x1;
 #endif
+	/* By default consider differential clock configuration and if TCSR
+	 * register bit 0 is not set then use single ended setting
+	 */
+	if (se_clock)
+	{
+		writel(0x80, QUSB2PHY_PLL_TEST);
+	}
+	else
+	{
+	/* turn the ref clock on for differential clocks */
+#if GCC_RX2_USB2_CLKREF_EN
+		writel((readl(GCC_RX2_USB2_CLKREF_EN) | 0x1), GCC_RX2_USB2_CLKREF_EN);
+		dmb();
+#endif
+	}
+	udelay(100);
+
+	/* Check PLL status */
+	while (!(readl(QUSB2PHY_PLL_STATUS) & QUSB2PHY_PLL_LOCK))
+	{
+		retry--;
+		if (!retry)
+		{
+			dprintf(CRITICAL, "QUSB2PHY failed to lock: %d", readl(QUSB2PHY_PLL_STATUS));
+			break;
+		}
+		/* As per recommendation form hw team wait for 5 us before reading the status */
+		udelay(5);
+	}
 }
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index d391b8d..385bc66 100644
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -569,7 +569,8 @@
 			$(LOCAL_DIR)/mipi_dsi.o \
 			$(LOCAL_DIR)/mipi_dsc.o \
 			$(LOCAL_DIR)/mipi_dsi_phy.o \
-			$(LOCAL_DIR)/mipi_dsi_autopll_thulium.o
+			$(LOCAL_DIR)/mipi_dsi_autopll_thulium.o \
+			$(LOCAL_DIR)/shutdown_detect.o
 endif
 
 ifeq ($(ENABLE_UFS_SUPPORT), 1)
diff --git a/platform/msm_shared/shutdown_detect.c b/platform/msm_shared/shutdown_detect.c
index b7410eb..9bde63d 100644
--- a/platform/msm_shared/shutdown_detect.c
+++ b/platform/msm_shared/shutdown_detect.c
@@ -32,6 +32,7 @@
 #include <pm8x41.h>
 #include <pm8x41_hw.h>
 #include <kernel/timer.h>
+#include <kernel/thread.h>
 #include <platform/timer.h>
 #include <shutdown_detect.h>
 #include <platform.h>
@@ -130,6 +131,7 @@
 			timer_cancel(&pon_timer);
 			break;
 		}
+		thread_sleep(1);
 	}
 }
 
@@ -150,7 +152,10 @@
 	 * Initialize pon_timer and call long_press_pwrkey_timer_func
 	 * function to check if the power key is last press long enough.
 	 */
-	if (is_pwrkey_pon_reason() && is_pwrkey_time_expired()) {
+	if (is_pwrkey_pon_reason()) {
+		if(!pm8x41_get_pwrkey_is_pressed()){
+			shutdown_device();
+		}
 		timer_initialize(&pon_timer);
 		timer_set_oneshot(&pon_timer, 0,(timer_callback)long_press_pwrkey_timer_func, NULL);
 
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index 30af435..fe89eea 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -438,7 +438,11 @@
 	MDMCALIFORNIUM4  = 285,
 	MDMCALIFORNIUM5  = 286,
 	APQ8052  = 289,
-	MDMFERMIUM  = 290,
+	MDMFERMIUM1 = 290,
+	MDMFERMIUM2  = 296,
+	MDMFERMIUM3  = 297,
+	MDMFERMIUM4  = 298,
+	MDMFERMIUM5  = 299,
 	APQ8096  = 291,
 	MSMTITANIUM  = 293,
 	MSM8937 = 294,
diff --git a/project/mdm9640.mk b/project/mdm9640.mk
index 24addd8..2aa002a 100644
--- a/project/mdm9640.mk
+++ b/project/mdm9640.mk
@@ -45,5 +45,9 @@
 DEFINES += SMD_SUPPORT=1
 endif
 
+# Reset USB clock from target code
+DEFINES += USB_RESET_FROM_CLK=1
+
 # Turn on Werror
 CFLAGS += -Werror
+DEFINES += USE_TARGET_QMP_SETTINGS=1
diff --git a/project/mdmfermium.mk b/project/mdmfermium.mk
index 8a7b5f5..96de0cb 100644
--- a/project/mdmfermium.mk
+++ b/project/mdmfermium.mk
@@ -17,6 +17,7 @@
 DEFINES += DEVICE_TREE=1
 DEFINES += CONTIGUOUS_MEMORY=1
 
+DEFINES += SPMI_CORE_V2=1
 DEFINES += BAM_V170=1
 #Disable thumb mode
 ENABLE_THUMB := false
diff --git a/project/msm8996.mk b/project/msm8996.mk
index 4d2953f..0d674c7 100644
--- a/project/msm8996.mk
+++ b/project/msm8996.mk
@@ -49,6 +49,11 @@
 #Enable below flag to compile cmnlib64
 #DEFINES += ENABLE_CMNLIB64_LOADING=1
 
+ENABLE_HAP_VIB_SUPPORT := true
+
+#Enable the feature of long press power on
+DEFINES += LONG_PRESS_POWER_ON=1
+
 #Disable thumb mode
 ENABLE_THUMB := false
 
@@ -59,6 +64,9 @@
 DEFINES += FBCON_DISPLAY_MSG=1
 endif
 
+ifeq ($(ENABLE_HAP_VIB_SUPPORT),true)
+DEFINES += PON_VIB_SUPPORT=1
+endif
 
 ifeq ($(ENABLE_GLINK_SUPPORT),1)
 DEFINES += GLINK_SUPPORT=1
diff --git a/target/mdm9640/init.c b/target/mdm9640/init.c
index 565b0b2..0b8cb1e 100644
--- a/target/mdm9640/init.c
+++ b/target/mdm9640/init.c
@@ -54,6 +54,7 @@
 #include <sdhci_msm.h>
 #include <uart_dm.h>
 #include <boot_device.h>
+#include <qmp_phy.h>
 
 extern void smem_ptable_init(void);
 extern void smem_add_modem_partitions(struct ptable *flash_ptable);
@@ -239,6 +240,7 @@
 	struct ptable *ptable;
 	int system_ptn_index = -1;
 	uint32_t buflen;
+	int ret = -1;
 
 	if (!cmdline || !part ) {
 		dprintf(CRITICAL, "WARN: Invalid input param\n");
@@ -274,9 +276,10 @@
 			/* Adding command line parameters according to target boot type */
 			snprintf(*buf, buflen, UBI_CMDLINE);
 			snprintf(*buf+strlen(*buf), buflen, " root=ubi0:rootfs ubi.mtd=%d", system_ptn_index);
+			ret = 0;
 		}
 		else {
-			buflen = strlen("EXT4_CMDLINE") + sizeof(int) +1;
+			buflen = strlen(EXT4_CMDLINE) + sizeof(int) +1;
 			*buf = (char *)malloc(buflen);
 			if(!(*buf)) {
 				dprintf(CRITICAL,"Unable to allocate memory for boot params\n");
@@ -291,10 +294,11 @@
 				return -1;
 			}
 			snprintf(*buf, buflen, EXT4_CMDLINE"%d", system_ptn_index);
+			ret = 0;
 		}
 	}
 	/*in success case buf will be freed in the calling function of this*/
-	return 0;
+	return ret;
 }
 
 const char * target_usb_controller()
@@ -372,7 +376,14 @@
 
 void target_usb_phy_reset(void)
 {
-	usb30_qmp_phy_reset();
+	/* Reset sequence for californium is different from 9x40, use the reset sequence
+	 * from clock driver
+	 */
+	if (platform_is_mdmcalifornium())
+		clock_reset_usb_phy();
+	else
+		usb30_qmp_phy_reset();
+
 	qusb2_phy_reset();
 }
 
@@ -394,10 +405,123 @@
 
 uint32_t target_override_pll()
 {
-	return 1;
+	if (platform_is_mdmcalifornium())
+		return 0;
+	else
+		return 1;
 }
 
 uint32_t target_get_hlos_subtype()
 {
 	return board_hlos_subtype();
 }
+
+/* QMP settings are different from californium when compared to v2.0/v1.0 hardware.
+ * Use the QMP settings from target code to keep the common driver clean
+ */
+struct qmp_reg qmp_settings[] =
+{
+	{0x804, 0x01}, /*USB3PHY_PCIE_USB3_PCS_POWER_DOWN_CONTROL */
+	{0xAC, 0x14}, /* QSERDES_COM_SYSCLK_EN_SEL */
+	{0x34, 0x08}, /* QSERDES_COM_BIAS_EN_CLKBUFLR_EN */
+	{0x174, 0x30}, /* QSERDES_COM_CLK_SELECT */
+	{0x3C, 0x06}, /* QSERDES_COM_SYS_CLK_CTRL */
+	{0xB4, 0x00}, /* QSERDES_COM_RESETSM_CNTRL */
+	{0xB8, 0x08}, /* QSERDES_COM_RESETSM_CNTRL2 */
+	{0x194, 0x06}, /* QSERDES_COM_CMN_CONFIG */
+	{0x19c, 0x01}, /* QSERDES_COM_SVS_MODE_CLK_SEL */
+	{0x178, 0x00}, /* QSERDES_COM_HSCLK_SEL */
+	{0xd0, 0x82}, /* QSERDES_COM_DEC_START_MODE0 */
+	{0xdc, 0x55}, /* QSERDES_COM_DIV_FRAC_START1_MODE0 */
+	{0xe0, 0x55}, /* QSERDES_COM_DIV_FRAC_START2_MODE0 */
+	{0xe4, 0x03}, /* QSERDES_COM_DIV_FRAC_START3_MODE0 */
+	{0x78, 0x0b}, /* QSERDES_COM_CP_CTRL_MODE0 */
+	{0x84, 0x16}, /* QSERDES_COM_PLL_RCTRL_MODE0 */
+	{0x90, 0x28}, /* QSERDES_COM_PLL_CCTRL_MODE0 */
+	{0x108, 0x80}, /* QSERDES_COM_INTEGLOOP_GAIN0_MODE0 */
+	{0x10C, 0x00}, /* QSERDES_COM_INTEGLOOP_GAIN1_MODE0 */
+	{0x184, 0x0A}, /* QSERDES_COM_CORECLK_DIV */
+	{0x4c, 0x15}, /* QSERDES_COM_LOCK_CMP1_MODE0 */
+	{0x50, 0x34}, /* QSERDES_COM_LOCK_CMP2_MODE0 */
+	{0x54, 0x00}, /* QSERDES_COM_LOCK_CMP3_MODE0 */
+	{0xC8, 0x00}, /* QSERDES_COM_LOCK_CMP_EN */
+	{0x18c, 0x00}, /* QSERDES_COM_CORE_CLK_EN */
+	{0xcc, 0x00}, /* QSERDES_COM_LOCK_CMP_CFG */
+	{0x128, 0x00}, /* QSERDES_COM_VCO_TUNE_MAP */
+	{0x0C, 0x0A}, /* QSERDES_COM_BG_TIMER */
+	{0x10, 0x01}, /* QSERDES_COM_SSC_EN_CENTER */
+	{0x1c, 0x31}, /* QSERDES_COM_SSC_PER1 */
+	{0x20, 0x01}, /* QSERDES_COM_SSC_PER2 */
+	{0x14, 0x00}, /* QSERDES_COM_SSC_ADJ_PER1 */
+	{0x18, 0x00}, /* QSERDES_COM_SSC_ADJ_PER2 */
+	{0x24, 0xde}, /* QSERDES_COM_SSC_STEP_SIZE1 */
+	{0x28, 0x07}, /* QSERDES_COM_SSC_STEP_SIZE2 */
+	{0x48, 0x0F}, /* USB3PHY_QSERDES_COM_PLL_IVCO */
+	{0x70, 0x0F}, /* USB3PHY_QSERDES_COM_BG_TRIM */
+	{0x100, 0x80}, /* QSERDES_COM_INTEGLOOP_INITVAL */
+
+	/* Rx Settings */
+	{0x440, 0x0b}, /* QSERDES_RX_UCDR_FASTLOCK_FO_GAIN */
+	{0x4d8, 0x02}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 */
+	{0x4dc, 0x6c}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 */
+	{0x4e0, 0xbb}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 */
+	{0x508, 0x77}, /* QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */
+	{0x50c, 0x80}, /* QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 */
+	{0x514, 0x03}, /* QSERDES_RX_SIGDET_CNTRL */
+	{0x51c, 0x16}, /* QSERDES_RX_SIGDET_DEGLITCH_CNTRL */
+	{0x448, 0x75}, /* QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE */
+	{0x450, 0x00}, /* QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW */
+	{0x454, 0x00}, /* QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH */
+	{0x40C, 0x0a}, /* QSERDES_RX_UCDR_FO_GAIN */
+	{0x41C, 0x06}, /* QSERDES_RX_UCDR_SO_GAIN */
+	{0x510, 0x00}, /*QSERDES_RX_SIGDET_ENABLES */
+
+	/* Tx settings */
+	{0x268, 0x45}, /* QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN */
+	{0x2ac, 0x12}, /* QSERDES_TX_RCV_DETECT_LVL_2 */
+	{0x294, 0x06}, /* QSERDES_TX_LANE_MODE */
+	{0x254, 0x00}, /* QSERDES_TX_RES_CODE_LANE_OFFSET */
+
+	/* FLL settings */
+	{0x8c8, 0x83}, /* PCIE_USB3_PCS_FLL_CNTRL2 */
+	{0x8c4, 0x02}, /* PCIE_USB3_PCS_FLL_CNTRL1 */
+	{0x8cc, 0x09}, /* PCIE_USB3_PCS_FLL_CNT_VAL_L */
+	{0x8D0, 0xA2}, /* PCIE_USB3_PCS_FLL_CNT_VAL_H_TOL */
+	{0x8D4, 0x85}, /* PCIE_USB3_PCS_FLL_MAN_CODE */
+
+	/* PCS Settings */
+	{0x880, 0xD1}, /* PCIE_USB3_PCS_LOCK_DETECT_CONFIG1 */
+	{0x884, 0x1F}, /* PCIE_USB3_PCS_LOCK_DETECT_CONFIG2 */
+	{0x888, 0x47}, /* PCIE_USB3_PCS_LOCK_DETECT_CONFIG3 */
+	{0x80C, 0x9F}, /* PCIE_USB3_PCS_TXMGN_V0 */
+	{0x824, 0x17}, /* PCIE_USB3_PCS_TXDEEMPH_M6DB_V0 */
+	{0x828, 0x0F}, /* PCIE_USB3_PCS_TXDEEMPH_M3P5DB_V0 */
+	{0x8B8, 0x75}, /* PCIE_USB3_PCS_RXEQTRAINING_WAIT_TIME */
+	{0x8BC, 0x13}, /* PCIE_USB3_PCS_RXEQTRAINING_RUN_TIME */
+	{0x8B0, 0x86}, /* PCIE_USB3_PCS_LFPS_TX_ECSTART_EQTLOCK */
+	{0x8A0, 0x04}, /* PCIE_USB3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK */
+	{0x88C, 0x44}, /* PCIE_USB3_PCS_TSYNC_RSYNC_TIME */
+	{0x870, 0xE7}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_P1U2_L */
+	{0x874, 0x03}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_P1U2_H */
+	{0x878, 0x40}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_U3_L */
+	{0x87c, 0x00}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_U3_H */
+	{0x9D8, 0x88}, /* PCIE_USB3_PCS_RX_SIGDET_LVL */
+	{0x808, 0x03}, /* PCIE_USB3_PCS_START_CONTROL */
+	{0x800, 0x00}, /* PCIE_USB3_PCS_SW_RESET */
+};
+
+struct qmp_reg *target_get_qmp_settings()
+{
+	if (platform_is_mdmcalifornium())
+		return qmp_settings;
+	else
+		return NULL;
+}
+
+int target_get_qmp_regsize()
+{
+	if (platform_is_mdmcalifornium())
+		return ARRAY_SIZE(qmp_settings);
+	else
+		return 0;
+}
diff --git a/target/mdm9640/keypad.c b/target/mdm9640/keypad.c
index 11ba6e8..2f637f1 100644
--- a/target/mdm9640/keypad.c
+++ b/target/mdm9640/keypad.c
@@ -29,6 +29,8 @@
 #include <reg.h>
 #include <platform/gpio.h>
 #include <platform/iomap.h>
+#include <pm8x41.h>
+#include <platform.h>
 
 /* GPIO that controls the button
  * for FASTBOOT.
@@ -43,9 +45,14 @@
 {
 	int ret;
 
-	gpio_tlmm_config(FASTBOOT_KEY_GPIO_ID, 0, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA, GPIO_ENABLE);
+	if (platform_is_mdmcalifornium())
+		ret = pm8x41_resin_status();
+	else
+	{
+		gpio_tlmm_config(FASTBOOT_KEY_GPIO_ID, 0, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA, GPIO_ENABLE);
 
-	ret = gpio_get_state(FASTBOOT_KEY_GPIO_ID);
+		ret = gpio_get_state(FASTBOOT_KEY_GPIO_ID);
+	}
 
 	return ret;
 }
diff --git a/target/mdmfermium/init.c b/target/mdmfermium/init.c
index 1ccc227..5a91d7f 100644
--- a/target/mdmfermium/init.c
+++ b/target/mdmfermium/init.c
@@ -115,10 +115,26 @@
 	}
 }
 
+/* Return Non zero (i.e 0x2) if vol_down pressed */
+uint32_t target_volume_down()
+{
+	/* Volume down button tied in with PMIC RESIN. */
+	return pm8x41_resin_status();
+}
+
+static void target_keystatus()
+{
+	keys_init();
+
+	if(target_volume_down())
+		keys_post_event(KEY_VOLUMEDOWN, 1);
+}
+
 void target_early_init(void)
 {
 #if WITH_DEBUG_UART
-	uart_dm_init(1, 0, BLSP1_UART1_BASE);
+	/*BLSP1 and UART5*/
+	uart_dm_init(5, 0, BLSP1_UART5_BASE);
 #endif
 }
 
@@ -150,6 +166,7 @@
 
 	spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
 
+	target_keystatus();
 	config.pipes.read_pipe = DATA_PRODUCER_PIPE;
 	config.pipes.write_pipe = DATA_CONSUMER_PIPE;
 	config.pipes.cmd_pipe = CMD_PIPE;
@@ -190,7 +207,11 @@
 
 	switch(platform)
 	{
-	case MDMFERMIUM:
+	case MDMFERMIUM1:
+	case MDMFERMIUM2:
+	case MDMFERMIUM3:
+	case MDMFERMIUM4:
+	case MDMFERMIUM5:
 		board->baseband = BASEBAND_MDM;
         break;
 	default:
@@ -199,6 +220,13 @@
 	};
 }
 
+void target_serialno(unsigned char *buf)
+{
+	uint32_t serialno;
+	serialno = board_chip_serial();
+	snprintf((char *)buf, sizeof(uint32_t)+1, "%x", serialno);
+}
+
 unsigned check_reboot_mode(void)
 {
 	uint32_t restart_reason = 0;
@@ -273,6 +301,7 @@
 
 void reboot_device(unsigned reboot_reason)
 {
+	uint8_t reset_type = 0;
 	 /* Write the reboot reason */
 	writel(reboot_reason, RESTART_REASON_ADDR);
 
@@ -281,7 +310,12 @@
 	* This call should be based on the pmic version
 	* when PM8019 v2 is available.
 	*/
-	pm8x41_v2_reset_configure(PON_PSHOLD_WARM_RESET);
+	if(reboot_reason)
+		reset_type = PON_PSHOLD_WARM_RESET;
+	else
+		reset_type = PON_PSHOLD_HARD_RESET;
+
+	pm8x41_v2_reset_configure(reset_type);
 
 	/* Drop PS_HOLD for MSM */
 	writel(0x00, MPM2_MPM_PS_HOLD);
diff --git a/target/mdmfermium/rules.mk b/target/mdmfermium/rules.mk
index 59f53ff..b614ea5 100644
--- a/target/mdmfermium/rules.mk
+++ b/target/mdmfermium/rules.mk
@@ -18,7 +18,6 @@
 
 BASE_ADDR                           := 0x80000000
 
-DEFINES += NO_KEYPAD_DRIVER=1
 
 MODULES += \
 	dev/keys \
diff --git a/target/msm8952/init.c b/target/msm8952/init.c
index e25b615..88889d1 100644
--- a/target/msm8952/init.c
+++ b/target/msm8952/init.c
@@ -430,7 +430,7 @@
 	else
 		reset_type = PON_PSHOLD_HARD_RESET;
 
-	pm8x41_reset_configure(reset_type);
+	pm8994_reset_configure(reset_type);
 
 	ret = scm_halt_pmic_arbiter();
 	if (ret)
diff --git a/target/msm8952/oem_panel.c b/target/msm8952/oem_panel.c
index 114fa41..bbb3a1f 100644
--- a/target/msm8952/oem_panel.c
+++ b/target/msm8952/oem_panel.c
@@ -55,6 +55,7 @@
 #include "include/panel_nt35597_wqxga_dsc_video.h"
 #include "include/panel_nt35597_wqxga_dsc_cmd.h"
 #include "include/panel_hx8394d_720p_video.h"
+#include "include/panel_byd_1200p_video.h"
 
 /*---------------------------------------------------------------------------*/
 /* static panel selection variable                                           */
@@ -70,6 +71,7 @@
 	NT35597_WQXGA_DSC_VIDEO_PANEL,
 	NT35597_WQXGA_DSC_CMD_PANEL,
 	HX8394D_720P_VIDEO_PANEL,
+	BYD_1200P_VIDEO_PANEL,
 	UNKNOWN_PANEL
 };
 
@@ -92,6 +94,7 @@
 	{"nt35597_wqxga_dsc_video", NT35597_WQXGA_DSC_VIDEO_PANEL},
 	{"nt35597_wqxga_dsc_cmd", NT35597_WQXGA_DSC_CMD_PANEL},
 	{"hx8394d_720p_video", HX8394D_720P_VIDEO_PANEL},
+	{"byd_1200p_video", BYD_1200P_VIDEO_PANEL},
 };
 
 static uint32_t panel_id;
@@ -469,6 +472,33 @@
 				hx8394d_720p_video_timings, TIMING_SIZE);
 		pinfo->mipi.signature = HX8394D_720P_VIDEO_SIGNATURE;
 		break;
+	case BYD_1200P_VIDEO_PANEL:
+		panelstruct->paneldata    = &byd_1200p_video_panel_data;
+		panelstruct->paneldata->panel_with_enable_gpio = 1;
+		panelstruct->panelres     = &byd_1200p_video_panel_res;
+		panelstruct->color        = &byd_1200p_video_color;
+		panelstruct->videopanel   = &byd_1200p_video_video_panel;
+		panelstruct->commandpanel = &byd_1200p_video_command_panel;
+		panelstruct->state        = &byd_1200p_video_state;
+		panelstruct->laneconfig   = &byd_1200p_video_lane_config;
+		panelstruct->paneltiminginfo
+			= &byd_1200p_video_timing_info;
+		panelstruct->panelresetseq
+					 = &byd_1200p_video_panel_reset_seq;
+		panelstruct->backlightinfo = &byd_1200p_video_backlight;
+		pinfo->mipi.panel_on_cmds
+			= byd_1200p_video_on_command;
+		pinfo->mipi.num_of_panel_on_cmds
+			= BYD_1200P_VIDEO_ON_COMMAND;
+		pinfo->mipi.panel_off_cmds
+			= byd_1200p_video_off_command;
+		pinfo->mipi.num_of_panel_off_cmds
+			= BYD_1200P_VIDEO_OFF_COMMAND;
+		memcpy(phy_db->timing,
+			byd_1200p_video_timings, TIMING_SIZE);
+		pinfo->mipi.signature 	= BYD_1200P_VIDEO_SIGNATURE;
+		phy_db->regulator_mode = DSI_PHY_REGULATOR_LDO_MODE;
+		break;
 	case UNKNOWN_PANEL:
 	default:
 		memset(panelstruct, 0, sizeof(struct panel_struct));
@@ -504,6 +534,7 @@
 			struct mdss_dsi_phy_ctrl *phy_db)
 {
 	uint32_t hw_id = board_hardware_id();
+	uint32_t hw_subtype = board_hardware_subtype();
 	int32_t panel_override_id;
 	uint32_t target_id, plat_hw_ver_major;
 
@@ -539,6 +570,11 @@
 			panel_id = TRULY_1080P_VIDEO_PANEL;
 		break;
 	case HW_PLATFORM_QRD:
+		if (hw_subtype == HW_PLATFORM_SUBTYPE_POLARIS) {
+			panel_id = BYD_1200P_VIDEO_PANEL;
+			break;
+		}
+
 		target_id = board_target_id();
 		plat_hw_ver_major = ((target_id >> 16) & 0xFF);
 
diff --git a/target/msm8952/rules.mk b/target/msm8952/rules.mk
index cedc119..c199e56 100644
--- a/target/msm8952/rules.mk
+++ b/target/msm8952/rules.mk
@@ -29,6 +29,7 @@
 	lib/libfdt \
 	dev/qpnp_wled \
 	dev/pmic/pmi8994 \
+	dev/pmic/fgsram \
 	dev/gcdb/display
 
 DEFINES += \
diff --git a/target/msm8952/target_display.c b/target/msm8952/target_display.c
index b2585fc..f3c3c32 100644
--- a/target/msm8952/target_display.c
+++ b/target/msm8952/target_display.c
@@ -330,15 +330,16 @@
 		if (!ret)
 			dprintf(CRITICAL, "Not able to enable master pll\n");
 
-		if (platform_is_msm8956() && pinfo->mipi.dual_dsi) {
+		if (platform_is_msm8956() && pinfo->mipi.dual_dsi &&
+			!platform_is_msm8976_v_1_1()) {
 				ret = mdss_dsi_pll_config(pinfo->mipi.spll_base,
 					pinfo->mipi.sctl_base, pll_data);
 			if (!ret)
 				dprintf(CRITICAL, "Not able to enable second pll\n");
 		}
 
-		gcc_dsi_clocks_enable(flags, pll_data->pclk_m, pll_data->pclk_n,
-				pll_data->pclk_d);
+		gcc_dsi_clocks_enable(flags, pinfo->mipi.use_dsi1_pll,
+			pll_data->pclk_m, pll_data->pclk_n, pll_data->pclk_d);
 	} else if(!target_cont_splash_screen()) {
 		gcc_dsi_clocks_disable(flags);
 		mdp_clock_disable();
@@ -353,10 +354,15 @@
 						struct msm_panel_info *pinfo)
 {
 	int ret = NO_ERROR;
+	uint32_t hw_id = board_hardware_id();
+	uint32_t hw_subtype = board_hardware_subtype();
 
 	if (platform_is_msm8956()) {
 		reset_gpio.pin_id = 25;
 		bkl_gpio.pin_id = 66;
+	} else if ((hw_id == HW_PLATFORM_QRD) &&
+		   (hw_subtype == HW_PLATFORM_SUBTYPE_POLARIS)) {
+		enable_gpio.pin_id = 19;
 	}
 
 	if (enable) {
diff --git a/target/msm8996/init.c b/target/msm8996/init.c
index ff7fe0c..750f7b1 100644
--- a/target/msm8996/init.c
+++ b/target/msm8996/init.c
@@ -64,6 +64,15 @@
 #include <pm_app_smbchg.h>
 #endif
 
+#if LONG_PRESS_POWER_ON
+#include <shutdown_detect.h>
+#endif
+
+#if PON_VIB_SUPPORT
+#include <vibrator.h>
+#define VIBRATE_TIME 250
+#endif
+
 #define CE_INSTANCE             1
 #define CE_EE                   0
 #define CE_FIFO_SIZE            64
@@ -209,6 +218,16 @@
 	tlmm_set_pull_ctrl(sdc1_rclk_cfg, ARRAY_SIZE(sdc1_rclk_cfg));
 }
 
+uint32_t target_is_pwrkey_pon_reason()
+{
+	uint8_t pon_reason = pm8950_get_pon_reason();
+	if (pm8x41_get_is_cold_boot() && ((pon_reason == KPDPWR_N) || (pon_reason == (KPDPWR_N|PON1))))
+		return 1;
+	else
+		return 0;
+}
+
+
 void target_sdc_init()
 {
 	struct mmc_config_data config = {0};
@@ -265,6 +284,20 @@
 
 	target_keystatus();
 
+#if defined(LONG_PRESS_POWER_ON) || defined(PON_VIB_SUPPORT)
+	switch(board_hardware_id())
+	{
+		case HW_PLATFORM_QRD:
+#if LONG_PRESS_POWER_ON
+			shutdown_detect();
+#endif
+#if PON_VIB_SUPPORT
+			vib_timed_turn_on(VIBRATE_TIME);
+#endif
+			break;
+	}
+#endif
+
 	if (target_use_signed_kernel())
 		target_crypto_init_params();
 
diff --git a/target/msm8996/rules.mk b/target/msm8996/rules.mk
index cf294bf..e59bfc2 100644
--- a/target/msm8996/rules.mk
+++ b/target/msm8996/rules.mk
@@ -22,6 +22,8 @@
 L1_PT_SZ     := 4
 L2_PT_SZ     := 3
 
+DEFINES += PMI_CONFIGURED=1
+
 DEFINES += DISPLAY_SPLASH_SCREEN=1
 DEFINES += DISPLAY_TYPE_MIPI=1
 DEFINES += DISPLAY_TYPE_DSI6G=1
@@ -29,6 +31,8 @@
 MODULES += \
 	dev/keys \
 	dev/pmic/pm8x41 \
+	dev/qpnp_haptic \
+	dev/vib \
 	dev/qpnp_wled \
 	dev/qpnp_led \
 	dev/gcdb/display \