platform: msm_shared: Fix the display interface setup
- Ensure that the compression ratio is set to 1 if the panel does
not support FBC.
- Program fetch start parameters and the CDM hardware block for HDMI
primary use cases.
- Update programming of underflow control as per HPG.
Change-Id: I679d29ab69fb8e8deece050368e71be8f86cb38f
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index 1bcb69f..461cb9e 100755
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -547,9 +547,8 @@
writel(BIT(16) | (0x3 << 20), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CONFIG */
}
- if (pinfo->compression_mode == COMPRESSION_FBC)
- if (!pinfo->fbc.enabled || !pinfo->fbc.comp_ratio)
- pinfo->fbc.comp_ratio = 1;
+ if (!pinfo->fbc.enabled || !pinfo->fbc.comp_ratio)
+ pinfo->fbc.comp_ratio = 1;
itp.xres = (adjust_xres / pinfo->fbc.comp_ratio);
itp.yres = pinfo->yres;
@@ -1090,10 +1089,10 @@
int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
{
- uint32_t left_pipe, right_pipe;
- dprintf(SPEW, "ENTER: %s\n", __func__);
+ uint32_t left_pipe, right_pipe, out_size;
mdss_intf_tg_setup(pinfo, MDP_INTF_3_BASE + mdss_mdp_intf_offset());
+ mdss_intf_fetch_start_config(pinfo, MDP_INTF_3_BASE + mdss_mdp_intf_offset());
pinfo->pipe_type = MDSS_MDP_PIPE_TYPE_RGB;
mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe);
@@ -1116,10 +1115,23 @@
writel(0x40, MDP_CTL_0_BASE + CTL_TOP);
writel(BIT(24) | BIT(25), MDP_DISP_INTF_SEL);
- writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL);
+ writel(0x11111, MDP_VIDEO_INTF_UNDERFLOW_CTL);
writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START);
writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START);
+ /**
+ * Program the CDM hardware block in HDMI bypass mode, and enable
+ * the HDMI packer.
+ */
+ writel(0x01, CDM_HDMI_PACK_OP_MODE);
+ writel(0x00, MDP_OUT_CTL_0);
+ writel(0x00, MDP_INTF_3_INTF_CONFIG);
+ out_size = (pinfo->xres & 0xFFFF) | ((pinfo->yres & 0xFFFF) << 16);
+ writel(out_size, CDM_CDWN2_OUT_SIZE);
+ writel(0x80, CDM_CDWN2_OP_MODE);
+ writel(0x3FF0000, CDM_CDWN2_CLAMP_OUT);
+ writel(0x0, CDM_CSC_10_OP_MODE);
+
return 0;
}