diff --git a/platform/msm8226/acpuclock.c b/platform/msm8226/acpuclock.c
index f1b3d41..df4c7f6 100644
--- a/platform/msm8226/acpuclock.c
+++ b/platform/msm8226/acpuclock.c
@@ -175,3 +175,7 @@
 	}
 }
 
+void clock_config_ce(uint8_t instance)
+{
+}
+
diff --git a/platform/msm8226/include/platform/clock.h b/platform/msm8226/include/platform/clock.h
index b549dd1..118428a 100644
--- a/platform/msm8226/include/platform/clock.h
+++ b/platform/msm8226/include/platform/clock.h
@@ -40,5 +40,6 @@
 void clock_config_mmc(uint32_t interface, uint32_t freq);
 void clock_config_uart_dm(uint8_t id);
 void hsusb_clock_init(void);
+void clock_config_ce(uint8_t instance);
 
 #endif
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index e0cbb50..1045240 100644
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -100,6 +100,11 @@
 			$(LOCAL_DIR)/spmi.o \
 			$(LOCAL_DIR)/bam.o \
 			$(LOCAL_DIR)/qpic_nand.o \
+            $(LOCAL_DIR)/certificate.o \
+            $(LOCAL_DIR)/image_verify.o \
+            $(LOCAL_DIR)/crypto_hash.o \
+            $(LOCAL_DIR)/crypto5_eng.o \
+            $(LOCAL_DIR)/crypto5_wrapper.o \
 			$(LOCAL_DIR)/dev_tree.o
 endif
 
diff --git a/project/msm8226.mk b/project/msm8226.mk
index 0ba5aaa..a9d45b2 100644
--- a/project/msm8226.mk
+++ b/project/msm8226.mk
@@ -13,4 +13,4 @@
 #DEFINES += WITH_DEBUG_FBCON=1
 DEFINES += DEVICE_TREE=1
 #DEFINES += MMC_BOOT_BAM=1
-#DEFINES += CRYPTO_BAM=1
+DEFINES += CRYPTO_BAM=1
diff --git a/target/msm8226/init.c b/target/msm8226/init.c
index 279d063..a3b0fff 100644
--- a/target/msm8226/init.c
+++ b/target/msm8226/init.c
@@ -40,9 +40,19 @@
 #include <baseband.h>
 #include <dev/keys.h>
 #include <pm8x41.h>
+#include <crypto5_wrapper.h>
 
-#define PMIC_ARB_CHANNEL_NUM    0
-#define PMIC_ARB_OWNER_ID       0
+extern  bool target_use_signed_kernel(void);
+
+#define PMIC_ARB_CHANNEL_NUM               0
+#define PMIC_ARB_OWNER_ID                  0
+
+#define CRYPTO_ENGINE_INSTANCE             1
+#define CRYPTO_ENGINE_EE                   1
+#define CRYPTO_ENGINE_FIFO_SIZE            64
+#define CRYPTO_ENGINE_READ_PIPE            3
+#define CRYPTO_ENGINE_WRITE_PIPE           2
+#define CRYPTO_ENGINE_CMD_ARRAY_SIZE       20
 
 #define TLMM_VOL_UP_BTN_GPIO    106
 
@@ -88,6 +98,29 @@
 		keys_post_event(KEY_VOLUMEUP, 1);
 }
 
+/* Set up params for h/w CRYPTO_ENGINE. */
+void target_crypto_init_params()
+{
+	struct crypto_init_params ce_params;
+
+	/* Set up base addresses and instance. */
+	ce_params.crypto_instance  = CRYPTO_ENGINE_INSTANCE;
+	ce_params.crypto_base      = MSM_CE1_BASE;
+	ce_params.bam_base         = MSM_CE1_BAM_BASE;
+
+	/* Set up BAM config. */
+	ce_params.bam_ee           = CRYPTO_ENGINE_EE;
+	ce_params.pipes.read_pipe  = CRYPTO_ENGINE_READ_PIPE;
+	ce_params.pipes.write_pipe = CRYPTO_ENGINE_WRITE_PIPE;
+
+	/* Assign buffer sizes. */
+	ce_params.num_ce           = CRYPTO_ENGINE_CMD_ARRAY_SIZE;
+	ce_params.read_fifo_size   = CRYPTO_ENGINE_FIFO_SIZE;
+	ce_params.write_fifo_size  = CRYPTO_ENGINE_FIFO_SIZE;
+
+	crypto_init_params(&ce_params);
+}
+
 void target_init(void)
 {
 	uint32_t base_addr;
@@ -113,6 +146,9 @@
 			ASSERT(0);
 		}
 	}
+
+	if (target_use_signed_kernel())
+		target_crypto_init_params();
 }
 
 /* Do any target specific intialization needed before entering fastboot mode */
@@ -199,6 +235,11 @@
 	dprintf(CRITICAL, "Rebooting failed\n");
 }
 
+crypto_engine_type board_ce_type(void)
+{
+	return CRYPTO_ENGINE_TYPE_HW;
+}
+
 unsigned board_machtype(void)
 {
 }