platform: update the DSI PLL APIs to use DSI_PLL base
The PLL register offsets from the DSI controller base
is not same for all targets. Update the auto PLL and
DSI PLL lock APIs to use the DSI_PLL base to handle
these cases.
Change-Id: Ie8aebc1bcc2b63f6825964c3476ce5cb6d0e7732
diff --git a/target/msm8226/target_display.c b/target/msm8226/target_display.c
index 1b5703d..b26d3e6 100755
--- a/target/msm8226/target_display.c
+++ b/target/msm8226/target_display.c
@@ -55,145 +55,145 @@
.fdbck = 0x1
};
-static uint32_t dsi_pll_enable_seq_m(uint32_t ctl_base)
+static uint32_t dsi_pll_enable_seq_m(uint32_t pll_base)
{
uint32_t i = 0;
uint32_t pll_locked = 0;
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+ mdss_dsi_uniphy_pll_sw_reset(pll_base);
/*
* Add hardware recommended delays between register writes for
* the updates to take effect. These delays are necessary for the
* PLL to successfully lock
*/
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
udelay(1000);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
- pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+ mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
+ pll_locked = readl(pll_base + 0x00c0) & 0x01;
for (i = 0; (i < 4) && !pll_locked; i++) {
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x07, pll_base + 0x0020); /* GLB CFG */
if (i != 0)
- writel(0x34, ctl_base + 0x00270); /* CAL CFG1*/
+ writel(0x34, pll_base + 0x00070); /* CAL CFG1*/
udelay(1);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
udelay(1000);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
- pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+ mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
+ pll_locked = readl(pll_base + 0x00c0) & 0x01;
}
return pll_locked;
}
-static uint32_t dsi_pll_enable_seq_d(uint32_t ctl_base)
+static uint32_t dsi_pll_enable_seq_d(uint32_t pll_base)
{
uint32_t pll_locked = 0;
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+ mdss_dsi_uniphy_pll_sw_reset(pll_base);
/*
* Add hardware recommended delays between register writes for
* the updates to take effect. These delays are necessary for the
* PLL to successfully lock
*/
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x07, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x07, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x07, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
udelay(1000);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
- pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+ mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
+ pll_locked = readl(pll_base + 0x00c0) & 0x01;
return pll_locked;
}
-static uint32_t dsi_pll_enable_seq_f1(uint32_t ctl_base)
+static uint32_t dsi_pll_enable_seq_f1(uint32_t pll_base)
{
uint32_t pll_locked = 0;
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+ mdss_dsi_uniphy_pll_sw_reset(pll_base);
/*
* Add hardware recommended delays between register writes for
* the updates to take effect. These delays are necessary for the
* PLL to successfully lock
*/
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x0d, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x0d, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
udelay(1000);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
- pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+ mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
+ pll_locked = readl(pll_base + 0x00c0) & 0x01;
return pll_locked;
}
-static uint32_t dsi_pll_enable_seq_c(uint32_t ctl_base)
+static uint32_t dsi_pll_enable_seq_c(uint32_t pll_base)
{
uint32_t pll_locked = 0;
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+ mdss_dsi_uniphy_pll_sw_reset(pll_base);
/*
* Add hardware recommended delays between register writes for
* the updates to take effect. These delays are necessary for the
* PLL to successfully lock
*/
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
udelay(1000);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
- pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+ mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
+ pll_locked = readl(pll_base + 0x00c0) & 0x01;
return pll_locked;
}
-static uint32_t dsi_pll_enable_seq_e(uint32_t ctl_base)
+static uint32_t dsi_pll_enable_seq_e(uint32_t pll_base)
{
uint32_t pll_locked = 0;
- mdss_dsi_uniphy_pll_sw_reset(ctl_base);
+ mdss_dsi_uniphy_pll_sw_reset(pll_base);
/*
* Add hardware recommended delays between register writes for
* the updates to take effect. These delays are necessary for the
* PLL to successfully lock
*/
- writel(0x01, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x01, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x05, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x05, pll_base + 0x0020); /* GLB CFG */
udelay(200);
- writel(0x0d, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x0d, pll_base + 0x0020); /* GLB CFG */
udelay(1);
- writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
+ writel(0x0f, pll_base + 0x0020); /* GLB CFG */
udelay(1000);
- mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
- pll_locked = readl(ctl_base + 0x02c0) & 0x01;
+ mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
+ pll_locked = readl(pll_base + 0x00c0) & 0x01;
return pll_locked;
}
@@ -225,14 +225,14 @@
return 0;
}
-static void dsi_pll_enable_seq(uint32_t ctl_base)
+static void dsi_pll_enable_seq(uint32_t pll_base)
{
- if (dsi_pll_enable_seq_m(ctl_base)) {
- } else if (dsi_pll_enable_seq_d(ctl_base)) {
- } else if (dsi_pll_enable_seq_d(ctl_base)) {
- } else if (dsi_pll_enable_seq_f1(ctl_base)) {
- } else if (dsi_pll_enable_seq_c(ctl_base)) {
- } else if (dsi_pll_enable_seq_e(ctl_base)) {
+ if (dsi_pll_enable_seq_m(pll_base)) {
+ } else if (dsi_pll_enable_seq_d(pll_base)) {
+ } else if (dsi_pll_enable_seq_d(pll_base)) {
+ } else if (dsi_pll_enable_seq_f1(pll_base)) {
+ } else if (dsi_pll_enable_seq_c(pll_base)) {
+ } else if (dsi_pll_enable_seq_e(pll_base)) {
} else {
dprintf(CRITICAL, "Not able to enable the pll\n");
}
@@ -260,8 +260,9 @@
mdp_gdsc_ctrl(0);
return ret;
}
- mdss_dsi_auto_pll_config(MIPI_DSI0_BASE, pll_data);
- dsi_pll_enable_seq(MIPI_DSI0_BASE);
+ mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
+ MIPI_DSI0_BASE, pll_data);
+ dsi_pll_enable_seq(DSI0_PLL_BASE);
mmss_dsi_clocks_enable(pll_data->pclk_m,
pll_data->pclk_n,
pll_data->pclk_d);