| commit | 79d0d405d324ee6fee1afa5139b86b87ad1b5086 | [log] [tgz] |
|---|---|---|
| author | Ajay Dudani <adudani@quicinc.com> | Wed Apr 21 12:38:45 2010 -0700 |
| committer | Ajay Dudani <adudani@quicinc.com> | Wed Apr 21 17:38:14 2010 -0700 |
| tree | 35d5e8b05998caf1f131563e0e53a96108fca565 | |
| parent | c51bf63c3e1e895ab75ac1ca376c9851e5f5a4a9 [diff] |
[7x30] Update write to PVR2F0 when initializing cache settings Original code intended to write to PVR2F0 as commented, but was incorrectly writing to PVR2F2 instead which affects L1 D cache read timing. Fixing to write to PVR2F0 as was originally intended. Also adding data and instruction synchronization after zeroing bss to force context ordering before jumping to kmain. Change-Id: Ibdfffd5bad33fa7bfe068fb743fec0cbec97ece8