[7x30] Update write to PVR2F0 when initializing cache settings
Original code intended to write to PVR2F0 as commented, but was
incorrectly writing to PVR2F2 instead which affects L1 D cache
read timing. Fixing to write to PVR2F0 as was originally intended.
Also adding data and instruction synchronization after zeroing
bss to force context ordering before jumping to kmain.
Change-Id: Ibdfffd5bad33fa7bfe068fb743fec0cbec97ece8
diff --git a/arch/arm/crt0.S b/arch/arm/crt0.S
index d5b4a32..3a3d776 100644
--- a/arch/arm/crt0.S
+++ b/arch/arm/crt0.S
@@ -20,6 +20,10 @@
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
+
+#define DSB .byte 0x4f, 0xf0, 0x7f, 0xf5
+#define ISB .byte 0x6f, 0xf0, 0x7f, 0xf5
+
.text
.globl _start
_start:
@@ -144,6 +148,11 @@
strlt r2, [r0], #4
blt .L__bss_loop
+#ifdef ARM_CPU_CORTEX_A8
+ DSB
+ ISB
+#endif
+
bl kmain
b .