target: Remove pll configuration for DSI1 PHY
Remove pll configuration for dsi1_phy because
pclk0 and pclk1 are sourced from dsi0 PHY in all
dual dsi cases.
CRs-fixed: 642087
Change-Id: I180320e4378b6c094cbe952a7dcfeffedd27074f
diff --git a/target/msm8974/target_display.c b/target/msm8974/target_display.c
index b8dc850..c89c483 100755
--- a/target/msm8974/target_display.c
+++ b/target/msm8974/target_display.c
@@ -221,11 +221,6 @@
mdp_clock_init();
mdss_dsi_auto_pll_config(MIPI_DSI0_BASE, pll_data);
dsi_pll_enable_seq(MIPI_DSI0_BASE);
- if (panel.panel_info.mipi.dual_dsi &&
- !(panel.panel_info.mipi.broadcast)) {
- mdss_dsi_auto_pll_config(MIPI_DSI1_BASE, pll_data);
- dsi_pll_enable_seq(MIPI_DSI1_BASE);
- }
mmss_clock_auto_pll_init(DSI0_PHY_PLL_OUT, dual_dsi,
pll_data->pclk_m,
pll_data->pclk_n,