| commit | 83b08bc12151de9b39a0bcfa3794e2aaeeb92c6a | [log] [tgz] |
|---|---|---|
| author | Dhaval Patel <pdhaval@codeaurora.org> | Fri Oct 25 10:40:58 2013 -0700 |
| committer | Dhaval Patel <pdhaval@codeaurora.org> | Thu Dec 05 11:25:58 2013 -0800 |
| tree | cb9370d04d6e0e8d6a8285abea8fd84362da2e4e | |
| parent | 430f8ecd8fe0d03c0ba897ed693423cb8a8b4f52 [diff] |
target: apq8084: Configure VBIF & CLK_CTL for APQ8084 Configure VBIF & CLK_CTL registers for APQ8084 with target specific values before timing generator enable. This configuration matches with VBIF & CLK_CTL setting in kernel. Change-Id: I014be2b805f39da0edeec8ec6f8d772211b94c57