target: apq8084: Configure VBIF & CLK_CTL for APQ8084
Configure VBIF & CLK_CTL registers for APQ8084
with target specific values before timing
generator enable. This configuration matches
with VBIF & CLK_CTL setting in kernel.
Change-Id: I014be2b805f39da0edeec8ec6f8d772211b94c57
diff --git a/target/apq8084/target_display.c b/target/apq8084/target_display.c
index 02e4737..4c6453e 100644
--- a/target/apq8084/target_display.c
+++ b/target/apq8084/target_display.c
@@ -211,6 +211,36 @@
return NO_ERROR;
}
+int target_display_pre_on()
+{
+ writel(0x000000FA, MDP_QOS_REMAPPER_CLASS_0);
+ writel(0x00000055, MDP_QOS_REMAPPER_CLASS_1);
+ writel(0xC0000CCD, MDP_CLK_CTRL0);
+ writel(0xD0000CCC, MDP_CLK_CTRL1);
+ writel(0x00CCCCCC, MDP_CLK_CTRL2);
+ writel(0x000000CC, MDP_CLK_CTRL6);
+ writel(0x0CCCC0C0, MDP_CLK_CTRL3);
+ writel(0xCCCCC0C0, MDP_CLK_CTRL4);
+ writel(0xCCCCC0C0, MDP_CLK_CTRL5);
+ writel(0x00CCC000, MDP_CLK_CTRL7);
+
+ writel(0x00000001, VBIF_VBIF_DDR_FORCE_CLK_ON);
+ writel(0x00080808, VBIF_VBIF_IN_RD_LIM_CONF0);
+ writel(0x08000808, VBIF_VBIF_IN_RD_LIM_CONF1);
+ writel(0x00080808, VBIF_VBIF_IN_RD_LIM_CONF2);
+ writel(0x00000808, VBIF_VBIF_IN_RD_LIM_CONF3);
+ writel(0x10000000, VBIF_VBIF_IN_WR_LIM_CONF0);
+ writel(0x00100000, VBIF_VBIF_IN_WR_LIM_CONF1);
+ writel(0x10000000, VBIF_VBIF_IN_WR_LIM_CONF2);
+ writel(0x00000000, VBIF_VBIF_IN_WR_LIM_CONF3);
+ writel(0x00013fff, VBIF_VBIF_ABIT_SHORT);
+ writel(0x000000A4, VBIF_VBIF_ABIT_SHORT_CONF);
+ writel(0x00003FFF, VBIF_VBIF_GATE_OFF_WRREQ_EN);
+ writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB);
+
+ return NO_ERROR;
+}
+
void display_init(void)
{
uint32_t ret = 0;