dev: gcdb: extend platform specific offsets check to DSI PHY/PLL
In the current implementation, the platform specific offset
adjustment is done only for DSI controller base. Derived
platforms may have different base addresses than the base
platform for DSI PHY/PLL/regulator as well. Add support for this.
Change-Id: Icf2f0e0e0edb7c78c4148c275e80e08022294125
diff --git a/dev/gcdb/display/panel_display.c b/dev/gcdb/display/panel_display.c
index d258db2..2555274 100755
--- a/dev/gcdb/display/panel_display.c
+++ b/dev/gcdb/display/panel_display.c
@@ -55,7 +55,9 @@
static int dsi_panel_ctl_base_setup(struct msm_panel_info *pinfo,
char *panel_destination)
{
- int base_offset = 0, base1_offset = 0;
+ int base_offset = 0, base1_offset = 0, base_phy_offset = 0,
+ base1_phy_offset = 0, base_phy_pll_offset = 0,
+ base1_phy_pll_offset = 0, base_phy_reg_offset = 0;
/*
* Base offsets may vary for few platforms. Add the difference to get
@@ -63,33 +65,38 @@
*/
base_offset = dsi_platform_base_offset_adjust(MIPI_DSI0_BASE);
base1_offset = dsi_platform_base_offset_adjust(MIPI_DSI1_BASE);
+ base_phy_offset = dsi_platform_base_offset_adjust(DSI0_PHY_BASE);
+ base1_phy_offset = dsi_platform_base_offset_adjust(DSI1_PHY_BASE);
+ base_phy_pll_offset = dsi_platform_base_offset_adjust(DSI0_PLL_BASE);
+ base1_phy_pll_offset = dsi_platform_base_offset_adjust(DSI1_PLL_BASE);
+ base_phy_reg_offset = dsi_platform_base_offset_adjust(DSI0_REGULATOR_BASE);
dprintf(SPEW, "base offset = %d, %x\n", base_offset, base_offset);
if (!strcmp(panel_destination, "DISPLAY_1")) {
pinfo->dest = DISPLAY_1;
pinfo->mipi.ctl_base = MIPI_DSI0_BASE + base_offset;
- pinfo->mipi.phy_base = DSI0_PHY_BASE + base_offset;
+ pinfo->mipi.phy_base = DSI0_PHY_BASE + base_phy_offset;
pinfo->mipi.sctl_base = MIPI_DSI1_BASE + base1_offset;
- pinfo->mipi.sphy_base = DSI1_PHY_BASE + base1_offset;
+ pinfo->mipi.sphy_base = DSI1_PHY_BASE + base1_phy_offset;
if (pinfo->mipi.use_dsi1_pll) {
dprintf(CRITICAL, "%s: Invalid combination: DSI0 controller + DSI1 PLL, using DSI0 PLL\n",
__func__);
pinfo->mipi.use_dsi1_pll = 0;
}
- pinfo->mipi.pll_base = DSI0_PLL_BASE + base_offset;
- pinfo->mipi.spll_base = DSI1_PLL_BASE + base1_offset;
+ pinfo->mipi.pll_base = DSI0_PLL_BASE + base_phy_pll_offset;
+ pinfo->mipi.spll_base = DSI1_PLL_BASE + base1_phy_pll_offset;
} else if (!strcmp(panel_destination, "DISPLAY_2")) {
pinfo->dest = DISPLAY_2;
pinfo->mipi.ctl_base = MIPI_DSI1_BASE + base1_offset;
- pinfo->mipi.phy_base = DSI1_PHY_BASE + base1_offset;
+ pinfo->mipi.phy_base = DSI1_PHY_BASE + base1_phy_offset;
pinfo->mipi.sctl_base = MIPI_DSI0_BASE + base_offset;
- pinfo->mipi.sphy_base = DSI0_PHY_BASE + base_offset;
+ pinfo->mipi.sphy_base = DSI0_PHY_BASE + base_phy_offset;
if (pinfo->mipi.use_dsi1_pll) {
- pinfo->mipi.pll_base = DSI1_PLL_BASE + base1_offset;
- pinfo->mipi.spll_base = DSI0_PLL_BASE + base_offset;
+ pinfo->mipi.pll_base = DSI1_PLL_BASE + base1_phy_pll_offset;
+ pinfo->mipi.spll_base = DSI0_PLL_BASE + base_phy_pll_offset;
} else {
- pinfo->mipi.pll_base = DSI0_PLL_BASE + base_offset;
- pinfo->mipi.spll_base = DSI1_PLL_BASE + base1_offset;
+ pinfo->mipi.pll_base = DSI0_PLL_BASE + base_phy_pll_offset;
+ pinfo->mipi.spll_base = DSI1_PLL_BASE + base1_phy_pll_offset;
}
} else {
pinfo->dest = DISPLAY_UNKNOWN;
@@ -99,8 +106,8 @@
}
/* Both DSI0 and DSI1 use the same regulator */
- pinfo->mipi.reg_base = DSI0_REGULATOR_BASE + base_offset;
- pinfo->mipi.sreg_base = DSI0_REGULATOR_BASE + base_offset;
+ pinfo->mipi.reg_base = DSI0_REGULATOR_BASE + base_phy_reg_offset;
+ pinfo->mipi.sreg_base = DSI0_REGULATOR_BASE + base_phy_reg_offset;
dprintf(SPEW, "%s: panel dest=%s, ctl_base=0x%08x, phy_base=0x%08x\n",
__func__, panel_destination, pinfo->mipi.ctl_base,