commit 8d6150c7d332e11bc9bf0a8141eb7ac75ec6a1c9
author Wentao Xu <wentaox@codeaurora.org> Wed Jun 22 11:03:18 2011 -0400
committer Linux Build Service Account <lnxbuild@localhost> Tue Aug 02 00:18:03 2011 -0600
tree ec38a988649ce886556abac4f7c28154bd2e334a
parent 32a9d4ff25b4014afb44cfce806784c533b5bf5f

[msm8660/LCD]: add AUO wvga panel support

Platform check added to decide which panel to turn on for splash
screen. Also changed to enable fbcon before power up the panel to
avoid a flicker.

Change-Id: I71851862f960294220df3f030b679c5694381d7d

platform/msm8x60/include/platform/clock.h

diff --git a/platform/msm8x60/include/platform/clock.h b/platform/msm8x60/include/platform/clock.h
index 0783efc..b676b16 100644
--- a/platform/msm8x60/include/platform/clock.h
+++ b/platform/msm8x60/include/platform/clock.h
@@ -87,6 +87,15 @@
 #define PIXEL_MD_VAL            0x00A9FDA6
 #define PIXEL_CC_VAL            0x00000080
 
+/* Configured at 25 MHz (AUO Panel) */
+#define PIXEL_NS_VAL_25M        0xFFF10002
+#define PIXEL_MD_VAL_25M        0x0001FFF0
+#define PIXEL_CC_VAL_25M        0x00000080
+
+/* PIXEL clock index */
+#define PIXEL_CLK_INDEX_54M	0 /* 53.99MHz */
+#define PIXEL_CLK_INDEX_25M	1 /* 25MHz */
+
 #define MSM_CLK_CTL_BASE        0x00900000
 #define BB_PLL8_L_VAL_REG       (MSM_CLK_CTL_BASE + 0x3144)
 #define BB_PLL8_M_VAL_REG       (MSM_CLK_CTL_BASE + 0x3148)
@@ -132,6 +141,6 @@
 void clock_config_uart_dm(uint8_t id);
 void clock_config_i2c(uint8_t id, uint32_t freq);
 void mdp_clock_init(void);
-void mmss_pixel_clock_configure(void);
+void mmss_pixel_clock_configure(uint32_t pclk_index);
 
 #endif