platform: msm_shared: add support to keep clock lane in HS
Some targets require to force DSI clock lanes in HS mode,
because in some corner cases clock lanes might be stuck due
to frequent transition between HS and LP modes.
Change-Id: I7001faaa041f5e67bf2c3405082e6d721c72014e
CRs-fixed: 783723
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 4814894..4dcc9d9 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -380,6 +380,14 @@
lane_swap_dsi1 = lane_swap;
writel(lane_swap_dsi1, mipi->sctl_base + LANE_SWAP_CTL);
writel(timing_ctl, mipi->sctl_base + TIMING_CTL);
+
+ if (mipi->force_clk_lane_hs) {
+ uint32_t tmp;
+
+ tmp = readl(mipi->sctl_base + LANE_CTL);
+ tmp |= BIT(28);
+ writel(tmp, mipi->sctl_base + LANE_CTL);
+ }
}
writel(0x0001, mipi->ctl_base + SOFT_RESET);
@@ -396,6 +404,14 @@
writel(lane_swap, mipi->ctl_base + LANE_SWAP_CTL);
writel(timing_ctl, mipi->ctl_base + TIMING_CTL);
+
+ if (mipi->force_clk_lane_hs) {
+ uint32_t tmp;
+
+ tmp = readl(mipi->ctl_base + LANE_CTL);
+ tmp |= BIT(28);
+ writel(tmp, mipi->ctl_base + LANE_CTL);
+ }
#endif
return 0;