platform: apq8084: Add clock support for hs400
Change-Id: I60590a187c7f466ae1313cae7d3dd79f9de4de1a
diff --git a/platform/apq8084/acpuclock.c b/platform/apq8084/acpuclock.c
index 386b558..4608432 100644
--- a/platform/apq8084/acpuclock.c
+++ b/platform/apq8084/acpuclock.c
@@ -124,6 +124,10 @@
{
ret = clk_get_set_enable(clk_name, 400000, 1);
}
+ else if(freq == MMC_CLK_25MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 25000000, 1);
+ }
else if(freq == MMC_CLK_50MHZ)
{
ret = clk_get_set_enable(clk_name, 50000000, 1);
@@ -134,7 +138,11 @@
}
else if(freq == MMC_CLK_200MHZ)
{
- ret = clk_get_set_enable(clk_name, 200000000, 1);
+ ret = clk_get_set_enable(clk_name, 192000000, 1);
+ }
+ else if(freq == MMC_CLK_400MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 384000000, 1);
}
else
{
@@ -151,6 +159,30 @@
}
+/* Configure clocks for SDCC Calibration circuit */
+void clock_config_cdc(uint32_t interface)
+{
+ int ret = 0;
+ char clk_name[64];
+
+ snprintf(clk_name, sizeof(clk_name), "gcc_sdcc%u_cdccal_sleep_clk", interface);
+
+ ret = clk_get_set_enable(clk_name, 0 , 1);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to enable clock: %s\n", clk_name);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "gcc_sdcc%u_cdccal_ff_clk", interface);
+ ret = clk_get_set_enable(clk_name, 0 , 1);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to enable clock: %s\n", clk_name);
+ ASSERT(0);
+ }
+}
+
/* Configure UART clock based on the UART block id*/
void clock_config_uart_dm(uint8_t id)
{