| commit | 90991f162b6ae1e1a4a046de0ef9b3053de84a28 | [log] [tgz] |
|---|---|---|
| author | Huaibin Yang <huaibiny@codeaurora.org> | Mon Dec 29 13:24:43 2014 -0800 |
| committer | Huaibin Yang <huaibiny@codeaurora.org> | Fri Jan 16 09:55:59 2015 -0800 |
| tree | b2f2cbbb93d59fff77759b3a99b897bef959ec27 | |
| parent | c81ea3eabd4dd760cdb1ea650f78a116027be03e [diff] |
platform: msm_shared: add pll common block settings for pll 1 One subset of DSI pll common block setting registers need to be programmed for both pll 0 and pll 1 to prevent current leakage. Change-Id: I1ba621f21b49e0e55c3840b281ca9323130465a2