platform: msm_shared: add pll common block settings for pll 1
One subset of DSI pll common block setting registers need to be
programmed for both pll 0 and pll 1 to prevent current leakage.
Change-Id: I1ba621f21b49e0e55c3840b281ca9323130465a2
diff --git a/platform/msm_shared/mipi_dsi_autopll_20nm.c b/platform/msm_shared/mipi_dsi_autopll_20nm.c
index 6a323be..736e0d7 100644
--- a/platform/msm_shared/mipi_dsi_autopll_20nm.c
+++ b/platform/msm_shared/mipi_dsi_autopll_20nm.c
@@ -156,12 +156,16 @@
return status;
}
-static void mdss_dsi_pll_20nm_config_common_block(uint32_t pll_base)
+static void mdss_dsi_pll_20nm_config_common_block_1(uint32_t pll_base)
{
writel(0x82, pll_base + MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN);
writel(0x2a, pll_base + MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN);
writel(0x2b, pll_base + MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN);
writel(0x02, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
+}
+
+static void mdss_dsi_pll_20nm_config_common_block_2(uint32_t pll_base)
+{
writel(0x40, pll_base + MMSS_DSI_PHY_PLL_SYS_CLK_CTRL);
writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_IE_TRIM);
writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_IP_TRIM);
@@ -191,12 +195,6 @@
writel(0x77, pll_base + MMSS_DSI_PHY_PLL_PLL_CRCTRL);
}
-static void mdss_dsi_pll_20nm_phy_config(uint32_t pll_base)
-{
- mdss_dsi_pll_20nm_config_common_block(pll_base);
- mdss_dsi_pll_20nm_config_loop_bw(pll_base);
-}
-
static void mdss_dsi_pll_20nm_config_vco_rate(uint32_t pll_base, struct mdss_dsi_pll_config *pd)
{
@@ -278,24 +276,23 @@
dmb();
}
-void mdss_dsi_auto_pll_20nm_config(uint32_t pll_base,uint32_t pll_1_base,
- uint32_t ctl_base, struct mdss_dsi_pll_config *pd)
+
+void mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t pll_1_base,
+ struct mdss_dsi_pll_config *pd)
{
-
- mdss_dsi_pll_20nm_phy_config(pll_base);
-
/*
* For 20nm PHY, DSI PLL 1 drains some current in its reset state.
* Need to turn off the DSI1 PLL explicitly.
*/
- if (ctl_base == MIPI_DSI0_BASE) {
- dprintf(SPEW, "Calling disable function for PHY PLL 1 \n");
- mdss_dsi_pll_20nm_disable(pll_1_base);
- }
+ mdss_dsi_pll_20nm_disable(pll_1_base);
+ mdss_dsi_pll_20nm_config_common_block_1(pll_1_base);
+ mdss_dsi_pll_20nm_config_common_block_1(pll_base);
+ mdss_dsi_pll_20nm_config_common_block_2(pll_base);
+ mdss_dsi_pll_20nm_config_loop_bw(pll_base);
mdss_dsi_pll_20nm_config_vco_rate(pll_base, pd);
-
mdss_dsi_pll_20nm_config_resetsm(pll_base);
mdss_dsi_pll_20nm_config_vco_start(pll_base);
+
udelay(1000);
}