platform: msmtitanium: Add clock config for Peripherals.
Adding Clock configuration needed to enable UART, USB, SDCC and Cypto.
Change-Id: I845d4cc7f06cb8d3f0954f5133f808acbc1be79e
diff --git a/platform/msmtitanium/acpuclock.c b/platform/msmtitanium/acpuclock.c
index 25c1eff..58fc686 100755
--- a/platform/msmtitanium/acpuclock.c
+++ b/platform/msmtitanium/acpuclock.c
@@ -38,25 +38,171 @@
#define MAX_LOOPS 500
-void hsusb_clock_init(void)
+/*
+ * Disable power collapse using GDSCR:
+ * Globally Distributed Switch Controller Register
+ */
+void clock_usb30_gdsc_enable(void)
{
+ uint32_t reg = readl(GCC_USB30_GDSCR);
+
+ reg &= ~(0x1);
+
+ writel(reg, GCC_USB30_GDSCR);
+}
+
+/* enables usb30 clocks */
+void clock_usb30_init(void)
+{
+ int ret;
+
+ ret = clk_get_set_enable("usb30_iface_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ clock_usb30_gdsc_enable();
+
+ ret = clk_get_set_enable("usb30_master_clk", 133330000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+ ret = clk_get_set_enable("usb30_pipe_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_aux_clk", 19200000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_aux_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_mock_utmi_clk", 60000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_mock_utmi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_sleep_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_sleep_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb_phy_cfg_ahb_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb_phy_cfg_ahb_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
}
void clock_init_mmc(uint32_t interface)
{
+ char clk_name[64];
+ int ret;
+
+ snprintf(clk_name, sizeof(clk_name), "sdc%u_iface_clk", interface);
+
+ /* enable interface clock */
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set sdc1_iface_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
}
/* Configure MMC clock */
void clock_config_mmc(uint32_t interface, uint32_t freq)
{
+ int ret = 1;
char clk_name[64];
snprintf(clk_name, sizeof(clk_name), "sdc%u_core_clk", interface);
+
+ if(freq == MMC_CLK_400KHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 400000, 1);
+ }
+ else if(freq == MMC_CLK_50MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 50000000, 1);
+ }
+ else if(freq == MMC_CLK_177MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 177770000, 1);
+ }
+ else if(freq == MMC_CLK_192MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 192000000, 1);
+ }
+ else if(freq == MMC_CLK_200MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 200000000, 1);
+ }
+ else if(freq == MMC_CLK_400MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 384000000, 1);
+ }
+ else
+ {
+ dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
+ ASSERT(0);
+ }
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set %s ret = %d\n", clk_name, ret);
+ ASSERT(0);
+ }
+}
+
+void clock_bumpup_pipe3_clk()
+{
+ int ret =0;
+ ret = clk_get_set_enable("usb30_pipe_clk", 0, true);
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
}
/* Configure UART clock based on the UART block id*/
void clock_config_uart_dm(uint8_t id)
{
+ int ret;
+ char iclk[64];
+ char cclk[64];
+
+ snprintf(iclk, sizeof(iclk), "uart%u_iface_clk", id);
+ snprintf(cclk, sizeof(cclk), "uart%u_core_clk", id);
+
+ ret = clk_get_set_enable(iclk, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set %s ret = %d\n", iclk, ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable(cclk, 7372800, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set %s ret = %d\n", cclk, ret);
+ ASSERT(0);
+ }
}
/* Function to asynchronously reset CE.
@@ -64,14 +210,90 @@
*/
static void ce_async_reset(uint8_t instance)
{
+ /* Start the block reset for CE */
+ writel(1, GCC_CRYPTO_BCR);
+
+ udelay(2);
+
+ /* Take CE block out of reset */
+ writel(0, GCC_CRYPTO_BCR);
+
+ udelay(2);
}
void clock_ce_enable(uint8_t instance)
{
+ int ret;
+ char clk_name[64];
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_src_clk", instance);
+ ret = clk_get_set_enable(clk_name, 160000000, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce%u_src_clk ret = %d\n", instance, ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_core_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce%u_core_clk ret = %d\n", instance, ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_ahb_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce%u_ahb_clk ret = %d\n", instance, ret);
+ ASSERT(0);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_axi_clk", instance);
+ ret = clk_get_set_enable(clk_name, 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set ce%u_axi_clk ret = %d\n", instance, ret);
+ ASSERT(0);
+ }
+
+ /* Wait for 48 * #pipes cycles.
+ * This is necessary as immediately after an access control reset (boot up)
+ * or a debug re-enable, the Crypto core sequentially clears its internal
+ * pipe key storage memory. If pipe key initialization writes are attempted
+ * during this time, they may be overwritten by the internal clearing logic.
+ */
+ udelay(1);
}
void clock_ce_disable(uint8_t instance)
{
+ struct clk *ahb_clk;
+ struct clk *cclk;
+ struct clk *axi_clk;
+ struct clk *src_clk;
+ char clk_name[64];
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_src_clk", instance);
+ src_clk = clk_get(clk_name);
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_ahb_clk", instance);
+ ahb_clk = clk_get(clk_name);
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_axi_clk", instance);
+ axi_clk = clk_get(clk_name);
+
+ snprintf(clk_name, sizeof(clk_name), "ce%u_core_clk", instance);
+ cclk = clk_get(clk_name);
+
+ clk_disable(ahb_clk);
+ clk_disable(axi_clk);
+ clk_disable(cclk);
+ clk_disable(src_clk);
+
+ /* Some delay for the clocks to stabalize. */
+ udelay(1);
}
void clock_config_ce(uint8_t instance)
@@ -88,3 +310,73 @@
clock_ce_enable(instance);
}
+
+
+void clock_reset_usb_phy()
+{
+ int ret;
+
+ struct clk *phy_reset_clk = NULL;
+ struct clk *pipe_reset_clk = NULL;
+ struct clk *master_clk = NULL;
+
+ master_clk = clk_get("usb30_master_clk");
+ ASSERT(master_clk);
+
+ /* Look if phy com clock is present */
+ phy_reset_clk = clk_get("usb30_phy_reset");
+ ASSERT(phy_reset_clk);
+
+ pipe_reset_clk = clk_get("usb30_pipe_clk");
+ ASSERT(pipe_reset_clk);
+
+ /* ASSERT */
+ ret = clk_reset(master_clk, CLK_RESET_ASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert usb30_master_reset clk\n");
+ return;
+ }
+ ret = clk_reset(phy_reset_clk, CLK_RESET_ASSERT);
+
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert usb30_phy_reset clk\n");
+ goto deassert_master_clk;
+ }
+
+ ret = clk_reset(pipe_reset_clk, CLK_RESET_ASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert usb30_pipe_clk\n");
+ goto deassert_phy_clk;
+ }
+
+ udelay(100);
+
+ /* DEASSERT */
+ ret = clk_reset(pipe_reset_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to deassert usb_pipe_clk\n");
+ return;
+ }
+
+deassert_phy_clk:
+
+ ret = clk_reset(phy_reset_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to deassert usb30_phy_com_reset clk\n");
+ return;
+ }
+
+deassert_master_clk:
+
+ ret = clk_reset(master_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to deassert usb30_master clk\n");
+ return;
+ }
+}
diff --git a/platform/msmtitanium/include/platform/clock.h b/platform/msmtitanium/include/platform/clock.h
old mode 100644
new mode 100755
index 4174744..86d1f9b
--- a/platform/msmtitanium/include/platform/clock.h
+++ b/platform/msmtitanium/include/platform/clock.h
@@ -41,4 +41,8 @@
void clock_config_uart_dm(uint8_t id);
void hsusb_clock_init(void);
void clock_config_ce(uint8_t instance);
+void clock_ce_enable(uint8_t instance);
+void clock_ce_disable(uint8_t instance);
+void clock_usb30_init(void);
+void clock_reset_usb_phy();
#endif
diff --git a/platform/msmtitanium/include/platform/iomap.h b/platform/msmtitanium/include/platform/iomap.h
index a57769b..64779cb 100755
--- a/platform/msmtitanium/include/platform/iomap.h
+++ b/platform/msmtitanium/include/platform/iomap.h
@@ -93,7 +93,7 @@
#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004)
#define GPLL4_MODE (CLK_CTL_BASE + 0x24000)
#define GPLL4_STATUS (CLK_CTL_BASE + 0x24024)
-#define GPLL6_STATUS (CLK_CTL_BASE + 0x3701C)
+#define GPLL6_STATUS (CLK_CTL_BASE + 0x37024)
/* SDCC */
#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x10A000)
@@ -127,6 +127,12 @@
/* UART */
#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x1008)
+#define BLSP1_UART1_APPS_CBCR (CLK_CTL_BASE + 0x203C)
+#define BLSP1_UART1_APPS_CMD_RCGR (CLK_CTL_BASE + 0x2044)
+#define BLSP1_UART1_APPS_CFG_RCGR (CLK_CTL_BASE + 0x2048)
+#define BLSP1_UART1_APPS_M (CLK_CTL_BASE + 0x204C)
+#define BLSP1_UART1_APPS_N (CLK_CTL_BASE + 0x2050)
+#define BLSP1_UART1_APPS_D (CLK_CTL_BASE + 0x2054)
#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x302C)
#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x3034)
#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x3038)
@@ -140,9 +146,56 @@
#define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x41008)
#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x41010)
#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x41014)
-#define MSM_USB30_QSCRATCH_BASE 0x070F8800
-#define MSM_USB30_BASE 0x7000000
-#define USB2_PHY_SEL 0x01937000
+#define GCC_QUSB2_PHY_BCR (CLK_CTL_BASE + 0x4103C)
+#define MSM_USB30_QSCRATCH_BASE 0x070F8800
+#define MSM_USB30_BASE 0x7000000
+#define USB2_PHY_SEL 0x01937000
+#define QUSB2_PHY_BASE 0X79000
+
+/* SS QMP (Qulacomm Multi Protocol) */
+#define QMP_PHY_BASE 0x78000
+
+#define AHB2_PHY_BASE 0x0007e000
+#define PERIPH_SS_AHB2PHY_TOP_CFG (AHB2_PHY_BASE + 0x10)
+
+ /* USB3 clocks */
+#define USB_30_BCR (CLK_CTL_BASE + 0x3F070)
+#define GCC_USB30_GDSCR (CLK_CTL_BASE + 0x3F078)
+#define USB30_MASTER_CBCR (CLK_CTL_BASE + 0x3F000)
+#define USB30_SLEEP_CBCR (CLK_CTL_BASE + 0x3F004)
+#define USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0x3F008)
+#define USB30_MASTER_CMD_RCGR (CLK_CTL_BASE + 0x3F00C)
+#define USB30_MASTER_CFG_RCGR (CLK_CTL_BASE + 0x3F010)
+#define USB30_MASTER_M (CLK_CTL_BASE + 0x3F014)
+#define USB30_MASTER_N (CLK_CTL_BASE + 0x3F018)
+#define USB30_MASTER_D (CLK_CTL_BASE + 0x3F01C)
+#define USB30_MOCK_UTMI_CMD_RCGR (CLK_CTL_BASE + 0x3F020)
+#define USB30_MOCK_UTMI_CFG_RCGR (CLK_CTL_BASE + 0x3F024)
+#define PC_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0x3F038)
+
+#define USB3_AUX_CMD_RCGR (CLK_CTL_BASE + 0x3F05C)
+#define USB3_AUX_CFG_RCGR (CLK_CTL_BASE + 0x3F060)
+#define USB3_AUX_CBCR (CLK_CTL_BASE + 0x3F044)
+#define USB3_AUX_M (CLK_CTL_BASE + 0x3F064)
+#define USB3_AUX_N (CLK_CTL_BASE + 0x3F068)
+#define USB3_AUX_D (CLK_CTL_BASE + 0x3F06C)
+#define USB3_PIPE_CBCR (CLK_CTL_BASE + 0x3F040)
+#define USB3_PHY_BCR (CLK_CTL_BASE + 0x3F034)
+#define USB3PHY_PHY_BCR (CLK_CTL_BASE + 0x3F03C)
+#define USB_PHY_CFG_AHB_CBCR (CLK_CTL_BASE + 0x3F080)
+
+/* QMP rev registers */
+#define USB3_PHY_REVISION_ID0 (QMP_PHY_BASE + 0x988)
+#define USB3_PHY_REVISION_ID1 (QMP_PHY_BASE + 0x98C)
+#define USB3_PHY_REVISION_ID2 (QMP_PHY_BASE + 0x990)
+#define USB3_PHY_REVISION_ID3 (QMP_PHY_BASE + 0x994)
+
+/* Dummy macro needed for compilation only */
+#define PLATFORM_QMP_OFFSET 0x0
+
+#define USB3_PHY_STATUS 0x78974
+/* Register for finding out if single ended or differential clock enablement */
+#define TCSR_PHY_CLK_SCHEME_SEL 0x0193F044
/* RPMB send receive buffer needs to be mapped
* as device memory, define the start address
diff --git a/platform/msmtitanium/include/platform/irqs.h b/platform/msmtitanium/include/platform/irqs.h
index db33501..120ea3d 100755
--- a/platform/msmtitanium/include/platform/irqs.h
+++ b/platform/msmtitanium/include/platform/irqs.h
@@ -51,7 +51,7 @@
#define SDCC2_PWRCTL_IRQ (GIC_SPI_START + 221)
/* Retrofit universal macro names */
-#define INT_USB_HS USB1_HS_IRQ
+#define INT_USB_HS USB30_EE1_IRQ
#define EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ (GIC_SPI_START + 190)
diff --git a/platform/msmtitanium/msmtitanium-clock.c b/platform/msmtitanium/msmtitanium-clock.c
old mode 100644
new mode 100755
index ee831b2..ff1e313
--- a/platform/msmtitanium/msmtitanium-clock.c
+++ b/platform/msmtitanium/msmtitanium-clock.c
@@ -40,6 +40,8 @@
#define cxo_source_val 0
#define gpll0_source_val 1
#define gpll4_source_val 2
+#define gpll6_source_val 1
+#define gpll0_out_main_div2_source_val 4
#define cxo_mm_source_val 0
#define gpll0_mm_source_val 6
#define gpll6_mm_source_val 3
@@ -48,6 +50,12 @@
/* Clock Operations */
+
+static struct clk_ops clk_ops_reset =
+{
+ .reset = clock_lib2_reset_clk_reset,
+};
+
static struct clk_ops clk_ops_branch =
{
.enable = clock_lib2_branch_clk_enable,
@@ -112,6 +120,21 @@
},
};
+static struct pll_vote_clk gpll0_out_main_div2_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(0),
+ .status_reg = (void *) GPLL0_MODE,
+ .status_mask = BIT(30),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 400000000,
+ .dbg_name = "gpll0_out_main_div2_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
static struct pll_vote_clk gpll4_clk_src =
{
.en_reg = (void *) APCS_GPLL_ENA_VOTE,
@@ -127,17 +150,32 @@
},
};
+static struct pll_vote_clk gpll6_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(7),
+ .status_reg = (void *) GPLL6_STATUS,
+ .status_mask = BIT(17),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 1080000000,
+ .dbg_name = "gpll6_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
/* SDCC Clocks */
static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk[] =
{
F( 144000, cxo, 16, 3, 25),
F( 400000, cxo, 12, 1, 4),
- F( 20000000, gpll0, 10, 1, 4),
- F( 25000000, gpll0, 16, 1, 2),
+ F( 20000000, gpll0_out_main_div2, 5, 1, 2),
+ F( 25000000, gpll0_out_main_div2, 16, 0, 0),
F( 50000000, gpll0, 16, 0, 0),
F(100000000, gpll0, 8, 0, 0),
F(177770000, gpll0, 4.5, 0, 0),
- F(200000000, gpll0, 4, 0, 0),
+ F(192000000, gpll4, 6, 0, 0),
F(384000000, gpll4, 3, 0, 0),
F_END
};
@@ -186,12 +224,12 @@
{
F( 144000, cxo, 16, 3, 25),
F( 400000, cxo, 12, 1, 4),
- F( 20000000, gpll0, 10, 1, 4),
- F( 25000000, gpll0, 16, 1, 2),
+ F( 20000000, gpll0_out_main_div2, 5, 1, 2),
+ F( 25000000, gpll0_out_main_div2, 16, 0, 0),
F( 50000000, gpll0, 16, 0, 0),
F(100000000, gpll0, 8, 0, 0),
F(177770000, gpll0, 4.5, 0, 0),
- F(200000000, gpll0, 4, 0, 0),
+ F(192000000, gpll4, 6, 0, 0),
F_END
};
@@ -238,10 +276,10 @@
/* UART Clocks */
static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_2_apps_clk[] =
{
- F( 3686400, gpll0, 1, 72, 15625),
- F( 7372800, gpll0, 1, 144, 15625),
- F(14745600, gpll0, 1, 288, 15625),
- F(16000000, gpll0, 10, 1, 5),
+ F( 3686400, gpll0_out_main_div2, 1, 144, 15625),
+ F( 7372800, gpll0_out_main_div2, 1, 288, 15625),
+ F(14745600, gpll0_out_main_div2, 1, 576, 15625),
+ F(16000000, gpll0_out_main_div2, 5, 1, 5),
F(19200000, cxo, 1, 0, 0),
F(24000000, gpll0, 1, 3, 100),
F(25000000, gpll0, 16, 1, 2),
@@ -253,9 +291,39 @@
F(56000000, gpll0, 1, 7, 100),
F(58982400, gpll0, 1,1152, 15625),
F(60000000, gpll0, 1, 3, 40),
+ F(64000000, gpll0, 12, 1, 2),
F_END
};
+static struct rcg_clk blsp1_uart1_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP1_UART1_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART1_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART1_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART1_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART1_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp1_uart1_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp1_uart1_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP1_UART1_APPS_CBCR,
+ .parent = &blsp1_uart1_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_uart1_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
static struct rcg_clk blsp1_uart2_apps_clk_src =
{
.cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
@@ -297,50 +365,117 @@
};
/* USB Clocks */
-static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] =
+static struct branch_clk gcc_pc_noc_usb30_axi_clk =
{
- F(100000000, gpll0, 10, 0, 0),
- F(133330000, gpll0, 6, 0, 0),
+ .cbcr_reg = (uint32_t *) PC_NOC_USB3_AXI_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_pc_noc_usb3_axi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb_phy_cfg_ahb_clk = {
+ .cbcr_reg = (uint32_t *) USB_PHY_CFG_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_usb_phy_cfg_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] =
+{
+ F(100000000, gpll0, 8, 0, 0),
+ F(133330000, gpll0, 6, 0, 0),
F_END
};
-static struct rcg_clk usb_hs_system_clk_src =
-{
- .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR,
- .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR,
+static struct rcg_clk usb30_master_clk_src = {
+ .cmd_reg = (uint32_t *) USB30_MASTER_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB30_MASTER_CFG_RCGR,
+ .m_reg = (uint32_t *) USB30_MASTER_M,
+ .n_reg = (uint32_t *) USB30_MASTER_N,
+ .d_reg = (uint32_t *) USB30_MASTER_D,
- .set_rate = clock_lib2_rcg_set_rate_hid,
- .freq_tbl = ftbl_gcc_usb_hs_system_clk,
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_usb30_master_clk,
.current_freq = &rcg_dummy_freq,
.c = {
- .dbg_name = "usb_hs_system_clk",
+ .dbg_name = "usb30_master_clk_src",
.ops = &clk_ops_rcg,
},
};
-static struct branch_clk gcc_usb_hs_system_clk =
+static struct branch_clk gcc_usb30_master_clk =
{
- .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR,
- .parent = &usb_hs_system_clk_src.c,
+ .cbcr_reg = (uint32_t *) USB30_MASTER_CBCR,
+ .bcr_reg = (uint32_t *) USB_30_BCR,
+ .parent = &usb30_master_clk_src.c,
.c = {
- .dbg_name = "gcc_usb_hs_system_clk",
+ .dbg_name = "gcc_usb30_master_clk",
.ops = &clk_ops_branch,
},
};
-static struct branch_clk gcc_usb_hs_ahb_clk =
-{
- .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR,
+
+static struct branch_clk gcc_usb30_pipe_clk = {
+ .bcr_reg = (uint32_t *) USB3PHY_PHY_BCR,
+ .cbcr_reg = (uint32_t *) USB3_PIPE_CBCR,
.has_sibling = 1,
+ .halt_check = 0,
.c = {
- .dbg_name = "gcc_usb_hs_ahb_clk",
+ .dbg_name = "usb30_pipe_clk",
.ops = &clk_ops_branch,
},
};
+static struct clk_freq_tbl ftbl_gcc_usb30_aux_clk[] = {
+ F( 19200000, cxo, 0, 0, 0),
+ F_END
+};
+
+static struct rcg_clk usb30_aux_clk_src = {
+ .cmd_reg = (uint32_t *) USB3_AUX_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB3_AUX_CFG_RCGR,
+ .m_reg = (uint32_t *) USB3_AUX_M,
+ .n_reg = (uint32_t *) USB3_AUX_N,
+ .d_reg = (uint32_t *) USB3_AUX_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_usb30_aux_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_aux_clk_src",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_usb30_aux_clk = {
+ .cbcr_reg = (uint32_t *) USB3_AUX_CBCR,
+ .parent = &usb30_aux_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_usb30_aux_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct reset_clk gcc_usb30_phy_reset = {
+ .bcr_reg = (uint32_t) USB3_PHY_BCR,
+
+ .c = {
+ .dbg_name = "usb30_phy_reset",
+ .ops = &clk_ops_reset,
+ },
+};
+
static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
F(160000000, gpll0, 5, 0, 0),
F_END
@@ -370,6 +505,54 @@
},
};
+static struct reset_clk gcc_usb2a_phy_sleep_clk = {
+ .bcr_reg = (uint32_t) GCC_QUSB2_PHY_BCR,
+
+ .c = {
+ .dbg_name = "usb2b_phy_sleep_clk",
+ .ops = &clk_ops_reset,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = {
+ F( 19200000, cxo, 0, 0, 0),
+ F( 60000000, gpll6, 6, 1, 3),
+ F_END
+};
+
+static struct rcg_clk usb30_mock_utmi_clk_src = {
+ .cmd_reg = (uint32_t *) USB30_MOCK_UTMI_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB30_MOCK_UTMI_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_mock_utmi_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb30_mock_utmi_clk = {
+ .cbcr_reg = (uint32_t *) USB30_MOCK_UTMI_CBCR,
+ .has_sibling = 0,
+ .parent = &usb30_mock_utmi_clk_src.c,
+
+ .c = {
+ .dbg_name = "usb30_mock_utmi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb30_sleep_clk = {
+ .cbcr_reg = (uint32_t *) USB30_SLEEP_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "usb30_sleep_clk",
+ .ops = &clk_ops_branch,
+ },
+};
static struct vote_clk gcc_ce1_ahb_clk = {
.cbcr_reg = (uint32_t *) GCC_CRYPTO_AHB_CBCR,
.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
@@ -401,11 +584,21 @@
CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c),
CLK_LOOKUP("sdc2_core_clk", gcc_sdcc2_apps_clk.c),
+ CLK_LOOKUP("uart1_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart1_core_clk", gcc_blsp1_uart1_apps_clk.c),
+
CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
- CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c),
- CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c),
+ CLK_LOOKUP("usb30_iface_clk", gcc_pc_noc_usb30_axi_clk.c),
+ CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
+ CLK_LOOKUP("usb30_pipe_clk", gcc_usb30_pipe_clk.c),
+ CLK_LOOKUP("usb30_aux_clk", gcc_usb30_aux_clk.c),
+ CLK_LOOKUP("usb2b_phy_sleep_clk", gcc_usb2a_phy_sleep_clk.c),
+ CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c),
+ CLK_LOOKUP("usb30_mock_utmi_clk", gcc_usb30_mock_utmi_clk.c),
+ CLK_LOOKUP("usb_phy_cfg_ahb_clk", gcc_usb_phy_cfg_ahb_clk.c),
+ CLK_LOOKUP("usb30_sleep_clk", gcc_usb30_sleep_clk.c),
CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c),
CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c),
diff --git a/platform/msmtitanium/platform.c b/platform/msmtitanium/platform.c
index 2168570..83d0b3b 100755
--- a/platform/msmtitanium/platform.c
+++ b/platform/msmtitanium/platform.c
@@ -66,6 +66,7 @@
{ APPS_SS_BASE, APPS_SS_BASE, APPS_SS_SIZE, IOMAP_MEMORY},
{ MSM_SHARED_IMEM_BASE, MSM_SHARED_IMEM_BASE, 1, COMMON_MEMORY},
{ SCRATCH_ADDR, SCRATCH_ADDR, 512, SCRATCH_MEMORY},
+ { RPMB_SND_RCV_BUF, RPMB_SND_RCV_BUF, RPMB_SND_RCV_BUF_SZ, IOMAP_MEMORY},
};
void platform_early_init(void)
@@ -168,3 +169,9 @@
else
return MSM_SHARED_BASE;
}
+
+uint32_t platform_get_qmp_rev()
+{
+ return readl(USB3_PHY_REVISION_ID3) << 24 | readl(USB3_PHY_REVISION_ID2) << 16 |
+ readl(USB3_PHY_REVISION_ID1) << 8 | readl(USB3_PHY_REVISION_ID0);
+}