target: msm8996: set the correct parent for DSI RCG clocks
The parent of DSI RCG clocks can be either DSI0 PLL or DSI1 PLL
based on the use case. In the current implementation, the parent
is always set to DSI0 PLL. Add change to set the parent correctly
based on the PLL used.
Change-Id: I67cbafb84ebfd4b186394748f6f833db48121466
diff --git a/platform/msm8996/acpuclock.c b/platform/msm8996/acpuclock.c
index 63dd958..9b1a23b 100644
--- a/platform/msm8996/acpuclock.c
+++ b/platform/msm8996/acpuclock.c
@@ -495,18 +495,18 @@
clk_disable(clk_get("mmss_mmagic_axi_clk"));
}
-void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t flags)
+void mmss_dsi_clock_enable(uint32_t cfg_rcgr, uint32_t flags)
{
int ret;
if (flags & MMSS_DSI_CLKS_FLAG_DSI0) {
/* Enable DSI0 branch clocks */
- writel(0x100, DSI_BYTE0_CFG_RCGR);
+ writel(cfg_rcgr, DSI_BYTE0_CFG_RCGR);
writel(0x1, DSI_BYTE0_CMD_RCGR);
writel(0x1, DSI_BYTE0_CBCR);
- writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
+ writel(cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
writel(0x1, DSI_PIXEL0_CMD_RCGR);
writel(0x1, DSI_PIXEL0_CBCR);
@@ -520,11 +520,11 @@
if (flags & MMSS_DSI_CLKS_FLAG_DSI1) {
/* Enable DSI1 branch clocks */
- writel(0x100, DSI_BYTE1_CFG_RCGR);
+ writel(cfg_rcgr, DSI_BYTE1_CFG_RCGR);
writel(0x1, DSI_BYTE1_CMD_RCGR);
writel(0x1, DSI_BYTE1_CBCR);
- writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL1_CFG_RCGR);
+ writel(cfg_rcgr, DSI_PIXEL1_CFG_RCGR);
writel(0x1, DSI_PIXEL1_CMD_RCGR);
writel(0x1, DSI_PIXEL1_CBCR);