diff --git a/dev/gcdb/display/panel_display.c b/dev/gcdb/display/panel_display.c
index d2675dc..d258db2 100755
--- a/dev/gcdb/display/panel_display.c
+++ b/dev/gcdb/display/panel_display.c
@@ -71,12 +71,26 @@
 		pinfo->mipi.phy_base = DSI0_PHY_BASE + base_offset;
 		pinfo->mipi.sctl_base = MIPI_DSI1_BASE + base1_offset;
 		pinfo->mipi.sphy_base = DSI1_PHY_BASE + base1_offset;
+		if (pinfo->mipi.use_dsi1_pll) {
+			dprintf(CRITICAL, "%s: Invalid combination: DSI0 controller + DSI1 PLL, using DSI0 PLL\n",
+				__func__);
+			pinfo->mipi.use_dsi1_pll = 0;
+		}
+		pinfo->mipi.pll_base = DSI0_PLL_BASE + base_offset;
+		pinfo->mipi.spll_base = DSI1_PLL_BASE + base1_offset;
 	} else if (!strcmp(panel_destination, "DISPLAY_2")) {
 		pinfo->dest = DISPLAY_2;
 		pinfo->mipi.ctl_base = MIPI_DSI1_BASE + base1_offset;
 		pinfo->mipi.phy_base = DSI1_PHY_BASE + base1_offset;
 		pinfo->mipi.sctl_base = MIPI_DSI0_BASE + base_offset;
 		pinfo->mipi.sphy_base = DSI0_PHY_BASE + base_offset;
+		if (pinfo->mipi.use_dsi1_pll) {
+			pinfo->mipi.pll_base = DSI1_PLL_BASE + base1_offset;
+			pinfo->mipi.spll_base = DSI0_PLL_BASE + base_offset;
+		} else {
+			pinfo->mipi.pll_base = DSI0_PLL_BASE + base_offset;
+			pinfo->mipi.spll_base = DSI1_PLL_BASE + base1_offset;
+		}
 	} else {
 		pinfo->dest = DISPLAY_UNKNOWN;
 		dprintf(CRITICAL, "%s: Unkown panel destination: %d\n",
@@ -84,9 +98,6 @@
 		return ERROR;
 	}
 
-	pinfo->mipi.pll_0_base = DSI0_PLL_BASE + base_offset;
-	pinfo->mipi.pll_1_base = DSI1_PLL_BASE + base1_offset;
-
 	/* Both DSI0 and DSI1 use the same regulator */
 	pinfo->mipi.reg_base = DSI0_REGULATOR_BASE + base_offset;
 	pinfo->mipi.sreg_base = DSI0_REGULATOR_BASE + base_offset;
@@ -94,8 +105,8 @@
 	dprintf(SPEW, "%s: panel dest=%s, ctl_base=0x%08x, phy_base=0x%08x\n",
 		__func__, panel_destination, pinfo->mipi.ctl_base,
 		pinfo->mipi.phy_base);
-	dprintf(SPEW, "pll_0_base=%08x, pll_1_base=0x%08x, reg_base=0x%08x, sreg_base=%08x\n",
-		pinfo->mipi.pll_0_base, pinfo->mipi.pll_1_base,
+	dprintf(SPEW, "pll_base=%08x, spll_base=0x%08x, reg_base=0x%08x, sreg_base=%08x\n",
+		pinfo->mipi.pll_base, pinfo->mipi.spll_base,
 		pinfo->mipi.reg_base, pinfo->mipi.sreg_base);
 	return NO_ERROR;
 }
@@ -178,6 +189,8 @@
 	pinfo->mipi.stream = pstruct->paneldata->dsi_stream;
 	if (pstruct->paneldata->panel_operating_mode & DUAL_DSI_FLAG)
 		pinfo->mipi.dual_dsi = 1;
+	if (pstruct->paneldata->panel_operating_mode & USE_DSI1_PLL_FLAG)
+		pinfo->mipi.use_dsi1_pll = 1;
 	pinfo->mipi.mode_gpio_state = pstruct->paneldata->mode_gpio_state;
 	pinfo->mipi.bitclock = pstruct->paneldata->panel_bitclock_freq;
 	if (pinfo->mipi.bitclock) {
diff --git a/dev/gcdb/display/panel_display.h b/dev/gcdb/display/panel_display.h
index 8860f00..3fd78ae 100755
--- a/dev/gcdb/display/panel_display.h
+++ b/dev/gcdb/display/panel_display.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -46,6 +46,7 @@
 #define PIPE_SWAP_FLAG 0x4
 #define SPLIT_DISPLAY_FLAG 0x8
 #define DST_SPLIT_FLAG 0x10
+#define USE_DSI1_PLL_FLAG 0x20
 
 #define MAX_PANEL_ID_LEN 64
 #include "panel.h"
diff --git a/platform/msm_shared/include/mipi_dsi.h b/platform/msm_shared/include/mipi_dsi.h
index c2ddd9b..d63a877 100644
--- a/platform/msm_shared/include/mipi_dsi.h
+++ b/platform/msm_shared/include/mipi_dsi.h
@@ -256,7 +256,7 @@
 	int rdbk_len);
 int32_t mdss_dsi_auto_pll_config(uint32_t pll_base, uint32_t ctl_base,
 	struct mdss_dsi_pll_config *pd);
-void mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t pll_1_base,
+void mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t spll_base,
 		struct mdss_dsi_pll_config *pd);
 void mdss_dsi_pll_20nm_sw_reset_st_machine(uint32_t pll_base);
 uint32_t mdss_dsi_pll_20nm_lock_status(uint32_t pll_base);
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index 75870a2..ff99ba3 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -245,6 +245,7 @@
 	char force_clk_lane_hs;
 	char lane_swap;
 	uint8_t dual_dsi;
+	uint8_t use_dsi1_pll;
 	uint8_t broadcast;
 	uint8_t mode_gpio_state;
 	uint32_t signature;
@@ -255,8 +256,8 @@
 	uint32_t sphy_base;
 	uint32_t reg_base;
 	uint32_t sreg_base;
-	uint32_t pll_0_base;
-	uint32_t pll_1_base;
+	uint32_t pll_base;
+	uint32_t spll_base;
 
 	struct dfps_pll_codes pll_codes;
 };
diff --git a/platform/msm_shared/mipi_dsi_autopll_20nm.c b/platform/msm_shared/mipi_dsi_autopll_20nm.c
index da0551e..e6f326f 100644
--- a/platform/msm_shared/mipi_dsi_autopll_20nm.c
+++ b/platform/msm_shared/mipi_dsi_autopll_20nm.c
@@ -281,15 +281,16 @@
 }
 
 
-void mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t pll_1_base,
+void mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t spll_base,
 	struct mdss_dsi_pll_config *pd)
 {
 	/*
-	 * For 20nm PHY, DSI PLL 1 drains some current in its reset state.
-	 * Need to turn off the DSI1 PLL explicitly.
+	 * For 20nm PHY, the DSI PLL which is not powered on to drive a panel
+	 * drains some current in its reset state.
+	 * Need to turn off that PLL explicitly.
 	 */
-	mdss_dsi_pll_20nm_config_common_block_1(pll_1_base);
-	mdss_dsi_pll_20nm_config_powerdown(pll_1_base);
+	mdss_dsi_pll_20nm_config_common_block_1(spll_base);
+	mdss_dsi_pll_20nm_config_powerdown(spll_base);
 
 	mdss_dsi_pll_20nm_config_common_block_1(pll_base);
 	mdss_dsi_pll_20nm_config_common_block_2(pll_base);
diff --git a/target/apq8084/target_display.c b/target/apq8084/target_display.c
index b46ef08..20e4d03 100755
--- a/target/apq8084/target_display.c
+++ b/target/apq8084/target_display.c
@@ -178,9 +178,9 @@
 			mdp_gdsc_ctrl(0);
 			return ret;
 		}
-		mdss_dsi_auto_pll_config(pinfo->mipi.pll_0_base,
+		mdss_dsi_auto_pll_config(pinfo->mipi.pll_base,
 						pinfo->mipi.ctl_base, pll_data);
-		dsi_pll_enable_seq(pinfo->mipi.pll_0_base);
+		dsi_pll_enable_seq(pinfo->mipi.pll_base);
 		mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, dual_dsi,
 					pll_data->pclk_m,
 					pll_data->pclk_n,
diff --git a/target/msm8226/target_display.c b/target/msm8226/target_display.c
index 77ca16e..fe2e6d5 100755
--- a/target/msm8226/target_display.c
+++ b/target/msm8226/target_display.c
@@ -308,9 +308,9 @@
 			mdp_gdsc_ctrl(0);
 			return ret;
 		}
-		mdss_dsi_auto_pll_config(pinfo->mipi.pll_0_base,
+		mdss_dsi_auto_pll_config(pinfo->mipi.pll_base,
 				pinfo->mipi.ctl_base, pll_data);
-		dsi_pll_enable_seq(pinfo->mipi.pll_0_base);
+		dsi_pll_enable_seq(pinfo->mipi.pll_base);
 		mmss_dsi_clocks_enable(pll_data->pclk_m,
 				pll_data->pclk_n,
 				pll_data->pclk_d);
diff --git a/target/msm8909/target_display.c b/target/msm8909/target_display.c
index 3f2a493..e949547 100755
--- a/target/msm8909/target_display.c
+++ b/target/msm8909/target_display.c
@@ -166,10 +166,10 @@
 			mdp_gdsc_ctrl(0);
 			return ret;
 		}
-		mdss_dsi_uniphy_pll_sw_reset_8909(DSI0_PLL_BASE);
-		mdss_dsi_auto_pll_config(pinfo->mipi.pll_0_base,
+		mdss_dsi_uniphy_pll_sw_reset_8909(pinfo->mipi.pll_base);
+		mdss_dsi_auto_pll_config(pinfo->mipi.pll_base,
 						pinfo->mipi.ctl_base, pll_data);
-		if (!dsi_pll_enable_seq_8909(pinfo->mipi.pll_0_base))
+		if (!dsi_pll_enable_seq_8909(pinfo->mipi.pll_base))
 			dprintf(CRITICAL, "Not able to enable the pll\n");
 		gcc_dsi_clocks_enable(pll_data->pclk_m,
 				pll_data->pclk_n,
diff --git a/target/msm8916/target_display.c b/target/msm8916/target_display.c
index 43a2903..42693d6 100644
--- a/target/msm8916/target_display.c
+++ b/target/msm8916/target_display.c
@@ -236,10 +236,10 @@
 			mdp_gdsc_ctrl(0);
 			return ret;
 		}
-		mdss_dsi_uniphy_pll_sw_reset_8916(DSI0_PLL_BASE);
-		mdss_dsi_auto_pll_config(pinfo->mipi.pll_0_base,
+		mdss_dsi_uniphy_pll_sw_reset_8916(pinfo->mipi.pll_base);
+		mdss_dsi_auto_pll_config(pinfo->mipi.pll_base,
 						pinfo->mipi.ctl_base, pll_data);
-		if (!dsi_pll_enable_seq_8916(pinfo->mipi.pll_0_base))
+		if (!dsi_pll_enable_seq_8916(pinfo->mipi.pll_base))
 			dprintf(CRITICAL, "Not able to enable the pll\n");
 		gcc_dsi_clocks_enable(pinfo->mipi.dual_dsi, pll_data->pclk_m,
 				pll_data->pclk_n,
diff --git a/target/msm8952/target_display.c b/target/msm8952/target_display.c
index 23976fd..9a86cd9 100644
--- a/target/msm8952/target_display.c
+++ b/target/msm8952/target_display.c
@@ -246,10 +246,10 @@
 			mdp_gdsc_ctrl(0);
 			return ret;
 		}
-		mdss_dsi_uniphy_pll_sw_reset_8952(DSI0_PLL_BASE);
-		mdss_dsi_auto_pll_config(pinfo->mipi.pll_0_base,
+		mdss_dsi_uniphy_pll_sw_reset_8952(pinfo->mipi.pll_base);
+		mdss_dsi_auto_pll_config(pinfo->mipi.pll_base,
 						pinfo->mipi.ctl_base, pll_data);
-		if (!dsi_pll_enable_seq_8952(pinfo->mipi.pll_0_base))
+		if (!dsi_pll_enable_seq_8952(pinfo->mipi.pll_base))
 			dprintf(CRITICAL, "Not able to enable the pll\n");
 		gcc_dsi_clocks_enable(pll_data->pclk_m, pll_data->pclk_n,
 				pll_data->pclk_d);
diff --git a/target/msm8974/target_display.c b/target/msm8974/target_display.c
index 6224f31..73319ea 100755
--- a/target/msm8974/target_display.c
+++ b/target/msm8974/target_display.c
@@ -247,9 +247,9 @@
 	if (enable) {
 		mdp_gdsc_ctrl(enable);
 		mdp_clock_init();
-		mdss_dsi_auto_pll_config(pinfo->mipi.pll_0_base,
+		mdss_dsi_auto_pll_config(pinfo->mipi.pll_base,
 						pinfo->mipi.ctl_base, pll_data);
-		dsi_pll_enable_seq(pinfo->mipi.pll_0_base);
+		dsi_pll_enable_seq(pinfo->mipi.pll_base);
 		mmss_clock_auto_pll_init(DSI0_PHY_PLL_OUT, dual_dsi,
 					pll_data->pclk_m,
 					pll_data->pclk_n,
diff --git a/target/msm8994/target_display.c b/target/msm8994/target_display.c
index 71fc136..35a7026 100644
--- a/target/msm8994/target_display.c
+++ b/target/msm8994/target_display.c
@@ -421,18 +421,18 @@
 		goto clks_disable;
 	}
 
-	mdss_dsi_auto_pll_20nm_config(pinfo->mipi.pll_0_base,
-		pinfo->mipi.pll_1_base, pll_data);
+	mdss_dsi_auto_pll_20nm_config(pinfo->mipi.pll_base,
+		pinfo->mipi.spll_base, pll_data);
 
-	if (!dsi_pll_20nm_enable_seq(pinfo->mipi.pll_0_base)) {
+	if (!dsi_pll_20nm_enable_seq(pinfo->mipi.pll_base)) {
 		ret = ERROR;
 		dprintf(CRITICAL, "PLL failed to lock!\n");
 		goto clks_disable;
 	}
 
-	pll_codes->codes[0] = readl_relaxed(pinfo->mipi.pll_0_base +
+	pll_codes->codes[0] = readl_relaxed(pinfo->mipi.pll_base +
 		MMSS_DSI_PHY_PLL_CORE_KVCO_CODE);
-	pll_codes->codes[1] = readl_relaxed(pinfo->mipi.pll_0_base +
+	pll_codes->codes[1] = readl_relaxed(pinfo->mipi.pll_base +
 		MMSS_DSI_PHY_PLL_CORE_VCO_TUNE);
 	dprintf(SPEW, "codes %d %d\n", pll_codes->codes[0],
 		pll_codes->codes[1]);