platform/target: thulium: Fix for bring up
- Update the freq plan for sdcc & usb
- Fix the gpio number for vol+ key
- Enable boot KPI logging
- Fix BLSP instance for UART
- Remove rpm message ram mapping as cacheable memory
Change-Id: I65a37bd2aa613dfa7db23c9c3b991195ae907f97
diff --git a/platform/thulium/acpuclock.c b/platform/thulium/acpuclock.c
index 445146c..03e1490 100644
--- a/platform/thulium/acpuclock.c
+++ b/platform/thulium/acpuclock.c
@@ -70,12 +70,16 @@
}
else if(freq == MMC_CLK_96MHZ)
{
- ret = clk_get_set_enable(clk_name, 100000000, true);
+ ret = clk_get_set_enable(clk_name, 96000000, true);
}
else if(freq == MMC_CLK_192MHZ)
{
ret = clk_get_set_enable(clk_name, 192000000, true);
}
+ else if(freq == MMC_CLK_400MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 384000000, 1);
+ }
else
{
dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
diff --git a/platform/thulium/include/platform/iomap.h b/platform/thulium/include/platform/iomap.h
index 16b3e15..345a537 100644
--- a/platform/thulium/include/platform/iomap.h
+++ b/platform/thulium/include/platform/iomap.h
@@ -38,6 +38,7 @@
#define MSM_SHARED_IMEM_BASE 0x066BF000
#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
+#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + 0x6B0)
#define MSM_GIC_DIST_BASE (MSM_IOMAP_HMSS_START + 0x003C0000)
#define MSM_GIC_REDIST_BASE (MSM_IOMAP_HMSS_START + 0x00400000)
@@ -93,8 +94,8 @@
#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x52004)
/* UART Clocks */
-#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x29004)
-#define BLSP2_UART2_APPS_CBCR (CLK_CTL_BASE + 0x29008)
+#define BLSP2_AHB_CBCR (CLK_CTL_BASE + 0x25004)
+#define BLSP2_UART2_APPS_CBCR (CLK_CTL_BASE + 0x29004)
#define BLSP2_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x2900C)
#define BLSP2_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x29010)
#define BLSP2_UART2_APPS_M (CLK_CTL_BASE + 0x29014)
@@ -163,7 +164,7 @@
#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x4A3000
/* DRV strength for sdcc */
-#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x0003C000)
+#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x0012C000)
/* SDHCI - power control registers */
#define SDCC_MCI_HC_MODE (0x00000078)
diff --git a/platform/thulium/platform.c b/platform/thulium/platform.c
index 315d05e..4b70f63 100644
--- a/platform/thulium/platform.c
+++ b/platform/thulium/platform.c
@@ -44,9 +44,6 @@
#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
MMU_MEMORY_AP_READ_WRITE)
-/* RPM MSG RAM memory - cacheable, write through */
-#define MSG_RAM_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
- MMU_MEMORY_AP_READ_WRITE)
/* Peripherals - non-shared device */
#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_SHARED | \
MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
@@ -62,7 +59,6 @@
{ KERNEL_ADDR, KERNEL_ADDR, KERNEL_SIZE, SCRATCH_MEMORY},
{ SCRATCH_ADDR, SCRATCH_ADDR, SCRATCH_SIZE, SCRATCH_MEMORY},
{ MSM_SHARED_BASE, MSM_SHARED_BASE, MSM_SHARED_SIZE, SCRATCH_MEMORY},
- { RPM_SS_MSG_RAM_START_ADDRESS_BASE, RPM_SS_MSG_RAM_START_ADDRESS_BASE, RPM_SS_MSG_RAM_START_ADDRESS_BASE_SIZE, MSG_RAM_MEMORY},
};
void platform_early_init(void)
@@ -134,3 +130,8 @@
{
return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
}
+
+addr_t get_bs_info_addr()
+{
+ return BS_INFO_ADDR;
+}
diff --git a/platform/thulium/thulium-clock.c b/platform/thulium/thulium-clock.c
index ae1d0de..c759df1 100644
--- a/platform/thulium/thulium-clock.c
+++ b/platform/thulium/thulium-clock.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -185,13 +185,13 @@
},
};
-static struct vote_clk gcc_blsp1_ahb_clk = {
- .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR,
+static struct vote_clk gcc_blsp2_ahb_clk = {
+ .cbcr_reg = (uint32_t *) BLSP2_AHB_CBCR,
.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
- .en_mask = BIT(17),
+ .en_mask = BIT(15),
.c = {
- .dbg_name = "gcc_blsp1_ahb_clk",
+ .dbg_name = "gcc_blsp2_ahb_clk",
.ops = &clk_ops_vote,
},
};
@@ -204,9 +204,9 @@
F( 20000000, gpll0, 15, 1, 2),
F( 25000000, gpll0, 12, 1, 2),
F( 50000000, gpll0, 12, 0, 0),
- F( 96000000, gpll4, 16, 0, 0),
- F(192000000, gpll4, 8, 0, 0),
- F(384000000, gpll4, 4, 0, 0),
+ F( 96000000, gpll4, 4, 0, 0),
+ F(192000000, gpll4, 2, 0, 0),
+ F(384000000, gpll4, 1, 0, 0),
F_END
};
@@ -261,7 +261,9 @@
};
static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] = {
- F( 125000000, gpll0, 1, 5, 24),
+ F( 19200000, gpll0, 1, 0, 0),
+ F( 125000000, gpll0, 5, 0, 0),
+ F( 150000000, gpll0, 4, 0, 0),
F_END
};
@@ -398,7 +400,7 @@
CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
- CLK_LOOKUP("uart8_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart8_iface_clk", gcc_blsp2_ahb_clk.c),
CLK_LOOKUP("uart8_core_clk", gcc_blsp2_uart2_apps_clk.c),
/* USB30 clocks */