diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index 6e8f000..437c45b 100755
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -1011,7 +1011,6 @@
 		return 0;
 }
 
-#define ROUND_TO_PAGE(x,y) (((x) + (y)) & (~(y)))
 
 BUF_DMA_ALIGN(buf, BOOT_IMG_MAX_PAGE_SIZE); //Equal to max-supported pagesize
 #if DEVICE_TREE
@@ -2110,6 +2109,7 @@
 			return;
 	}
 
+	memset(info, 0, BOOT_IMG_MAX_PAGE_SIZE);
 	memcpy(info, dev, sizeof(device_info));
 
 	if (flash_write(ptn, 0, (void *)info_buf, page_size))
diff --git a/app/aboot/mdtp.h b/app/aboot/mdtp.h
index adb3878..4e6fa73 100644
--- a/app/aboot/mdtp.h
+++ b/app/aboot/mdtp.h
@@ -40,7 +40,6 @@
 #define INITIAL_DELAY_MSECONDS      5000
 #define INVALID_PIN_DELAY_MSECONDS  5000
 
-#define ROUND_TO_PAGE(x,y) (((x) + (y)) & (~(y)))
 #define MDTP_FWLOCK_BLOCK_SIZE          (1024*1024*16)
 #define MDTP_FWLOCK_MAX_FILES           (100)
 #define MDTP_FWLOCK_MAX_FILE_NAME_LEN   (100)
diff --git a/app/aboot/mdtp_fs.c b/app/aboot/mdtp_fs.c
index 39f456a..1c1ea44 100644
--- a/app/aboot/mdtp_fs.c
+++ b/app/aboot/mdtp_fs.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -147,7 +147,7 @@
 	}
 
 	image_sets_num = mdtp_fs_get_param(IMAGE_SETS_NUM);
-	if (image_sets_num < 1) {
+	if ( (image_sets_num < 1) || (image_sets_num >= MAX_IMAGES) ) {
 		dprintf(CRITICAL, "ERROR: invalid number of image sets: %d\n", image_sets_num);
 		return -1;
 	}
diff --git a/app/aboot/recovery.c b/app/aboot/recovery.c
index 49f5057..a4048ab 100644
--- a/app/aboot/recovery.c
+++ b/app/aboot/recovery.c
@@ -43,14 +43,13 @@
 #include <partition_parser.h>
 #include <mmc.h>
 #include <malloc.h>
-
+#include <stdlib.h>
 #include "recovery.h"
 #include "bootimg.h"
 #include "smem.h"
 
 #define BOOT_FLAGS	1
 #define UPDATE_STATUS	2
-#define ROUND_TO_PAGE(x,y) (((x) + (y)) & (~(y)))
 
 static const int MISC_PAGES = 3;			// number of pages to save
 static const int MISC_COMMAND_PAGE = 1;		// bootloader command is this page
@@ -527,6 +526,11 @@
 			return -1;
 		}
 
+		/* This will ensure, we zeored out any extra bytes
+		   we will push to emmc, to prevent information leak */
+		if (aligned_size > size)
+			memset((scratch_addr + size), 0, (aligned_size-size));
+
 		if (scratch_addr != buf)
 			memcpy(scratch_addr, buf, size);
 
@@ -568,8 +572,14 @@
 			return -1;
 		}
 
+		/* This will ensure, we zeored out any extra bytes
+		   we will push, to prevent information leak */
+		if (aligned_size > size)
+			memset((scratch_addr + size), 0, (aligned_size-size));
+
 		if (scratch_addr != buf)
 			memcpy(scratch_addr, buf, size);
+
 		if (flash_write(ptn, offset, scratch_addr, aligned_size)) {
 			dprintf(CRITICAL, "Writing flash failed\n");
 			return -1;
diff --git a/dev/vib/vibrator.c b/dev/vib/vibrator.c
index cc47b24..8c7a031 100644
--- a/dev/vib/vibrator.c
+++ b/dev/vib/vibrator.c
@@ -105,7 +105,7 @@
 	timer_set_oneshot(&vib_timer, vibrate_time, vib_timer_func, NULL);
 #else
 	vib_time = (vibrate_time/CHECK_VIB_TIMER_FREQUENCY)+1;
-	thread_create("vibrator_thread", &vibrator_thread,
+	thr = thread_create("vibrator_thread", &vibrator_thread,
 			NULL, DEFAULT_PRIORITY, DEFAULT_STACK_SIZE);
 	if (!thr)
 	{
diff --git a/include/platform.h b/include/platform.h
index 6965c5a..55fd39e 100644
--- a/include/platform.h
+++ b/include/platform.h
@@ -91,4 +91,5 @@
 bool platform_is_glink_enabled();
 bool platform_is_mdm9206();
 int is_vb_le_enabled();
+void* get_rpmb_snd_rcv_buff();
 #endif
diff --git a/include/stdlib.h b/include/stdlib.h
index 22dcf4c..4a90831 100644
--- a/include/stdlib.h
+++ b/include/stdlib.h
@@ -49,6 +49,9 @@
 #define ROUNDUP(a, b) (((a) + ((b)-1)) & ~((b)-1))
 #define ROUNDDOWN(a, b) ((a) & ~((b)-1))
 
+/* Macro returns UINT_MAX in case of overflow */
+#define ROUND_TO_PAGE(x,y) (ROUNDUP((x),(y)+1) < (x))?UINT_MAX:ROUNDUP((x),(y)+1)
+
 /* allocate a buffer on the stack aligned and padded to the cpu's cache line size */
 #define STACKBUF_DMA_ALIGN(var, size) \
 	uint8_t __##var[(size) + CACHE_LINE] __attribute__((aligned(CACHE_LINE))); uint8_t *var = (uint8_t *)(ROUNDUP((addr_t)__##var, CACHE_LINE))
diff --git a/platform/msm8952/include/platform/iomap.h b/platform/msm8952/include/platform/iomap.h
index 6f4b28f..057d909 100644
--- a/platform/msm8952/include/platform/iomap.h
+++ b/platform/msm8952/include/platform/iomap.h
@@ -163,7 +163,8 @@
  * as device memory, define the start address
  * and size in MB
  */
-#define RPMB_SND_RCV_BUF            0xA0000000
+#define RPMB_SND_RCV_BUF            get_rpmb_snd_rcv_buff()
+#define RPMB_SND_RCV_BUF_STRT	    0xA0000000
 #define RPMB_SND_RCV_BUF_512        0x9FE00000
 #define RPMB_SND_RCV_BUF_SZ         0x1
 
diff --git a/platform/msm8952/platform.c b/platform/msm8952/platform.c
index 77b8f8a..11501c2 100644
--- a/platform/msm8952/platform.c
+++ b/platform/msm8952/platform.c
@@ -68,7 +68,7 @@
 	{    MSM_SHARED_IMEM_BASE,  MSM_SHARED_IMEM_BASE,    1,                      COMMON_MEMORY},
 	{    SCRATCH_ADDR,          SCRATCH_ADDR,            SCRATCH_SIZE,           SCRATCH_MEMORY},
 	{    MIPI_FB_ADDR,          MIPI_FB_ADDR,            20,                     COMMON_MEMORY},
-	{    RPMB_SND_RCV_BUF,      RPMB_SND_RCV_BUF,        RPMB_SND_RCV_BUF_SZ,    IOMAP_MEMORY},
+	{    RPMB_SND_RCV_BUF_STRT, RPMB_SND_RCV_BUF_STRT,   RPMB_SND_RCV_BUF_SZ,    IOMAP_MEMORY},
 };
 
 static mmu_section_t mmu_section_table_512[] = {
@@ -314,3 +314,11 @@
 
 	return ret;
 }
+
+void *get_rpmb_snd_rcv_buff()
+{
+	if(smem_get_ddr_size() > 0x20000000)
+		return (void *)RPMB_SND_RCV_BUF_STRT;
+	else
+		return (void *)RPMB_SND_RCV_BUF_512;
+}
diff --git a/platform/msm_shared/dev_tree.c b/platform/msm_shared/dev_tree.c
old mode 100755
new mode 100644
index 11f9616..1cf358a
--- a/platform/msm_shared/dev_tree.c
+++ b/platform/msm_shared/dev_tree.c
@@ -1318,13 +1318,13 @@
 	}
 
 	if (check_aboot_addr_range_overlap((uint32_t)fdt,
-				(fdt_totalsize(fdt) + DTB_PAD_SIZE))) {
+				(fdt_totalsize(fdt) + DTB_PAD_SIZE + strlen(cmdline)))) {
 		dprintf(CRITICAL, "Error: Fdt addresses overlap with aboot addresses.\n");
 		return ret;
 	}
 
 	/* Add padding to make space for new nodes and properties. */
-	ret = fdt_open_into(fdt, fdt, fdt_totalsize(fdt) + DTB_PAD_SIZE);
+	ret = fdt_open_into(fdt, fdt, fdt_totalsize(fdt) + DTB_PAD_SIZE + strlen(cmdline));
 	if (ret!= 0)
 	{
 		dprintf(CRITICAL, "Failed to move/resize dtb buffer: %d\n", ret);
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index d72d9b3..74e0688 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -513,6 +513,7 @@
 	HW_PLATFORM_SUBTYPE_SWOC_WEAR = 9,
 	HW_PLATFORM_SUBTYPE_SWOC_NOWGR_CIRC = 13,
 	HW_PLATFORM_SUBTYPE_8909_PM660 = 15,
+	HW_PLATFORM_SUBTYPE_8909_COMPAL_ALPHA = 19,
 	HW_PLATFORM_SUBTYPE_32BITS = 0x7FFFFFFF
 };
 
diff --git a/target/mdm9640/init.c b/target/mdm9640/init.c
index 97e55ec..487e7d8 100644
--- a/target/mdm9640/init.c
+++ b/target/mdm9640/init.c
@@ -512,12 +512,7 @@
 	ASSERT(t_usb_iface);
 
 	t_usb_iface->mux_config = NULL;
-	if (platform_is_sdx20()){
-		t_usb_iface->mux_config = target_mux_configure;
-		t_usb_iface->phy_init   = NULL;
-	}
-	else
-		t_usb_iface->phy_init   = usb30_qmp_phy_init;
+	t_usb_iface->phy_init   = usb30_qmp_phy_init;
 	t_usb_iface->phy_reset  = target_usb_phy_reset;
 	t_usb_iface->clock_init = clock_usb30_init;
 	t_usb_iface->vbus_override = 1;
@@ -632,18 +627,140 @@
 	{0x800, 0x00}, /* PCIE_USB3_PCS_SW_RESET */
 };
 
+/* QMP settings are different for sdx20 when compared to v2.0/v1.0 hardware.
+ * Use the QMP settings from target code to keep the common driver clean
+ */
+struct qmp_reg qmp_settings_sdx20[] =
+{
+	{0x804, 0x01}, /* USB3PHY_PCIE_USB3_PCS_POWER_DOWN_CONTROL */
+	{0x048, 0x07}, /* USB3PHY_QSERDES_COM_PLL_IVCO */
+	{0x080, 0x1A}, /* USB3PHY_QSERDES_COM_SYSCLK_EN_SEL */
+	{0x034, 0x04}, /* USB3PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN */
+	{0x138, 0x30}, /* USB3PHY_QSERDES_COM_CLK_SELECT */
+	{0x03C, 0x02}, /* USB3PHY_QSERDES_COM_SYS_CLK_CTRL */
+	{0x08C, 0x08}, /* USB3PHY_QSERDES_COM_RESETSM_CNTRL2 */
+	{0x15C, 0x06}, /* USB3PHY_QSERDES_COM_CMN_CONFIG */
+	{0x164, 0x01}, /* USB3PHY_QSERDES_COM_SVS_MODE_CLK_SEL */
+	{0x13C, 0x80}, /* USB3PHY_QSERDES_COM_HSCLK_SEL */
+	{0x0B0, 0x82}, /* USB3PHY_QSERDES_COM_DEC_START_MODE0 */
+	{0x0B8, 0xAB}, /* USB3PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 */
+	{0x0BC, 0xEA}, /* USB3PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 */
+	{0x0C0, 0x02}, /* USB3PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 */
+	{0x060, 0x06}, /* USB3PHY_QSERDES_COM_CP_CTRL_MODE0 */
+	{0x068, 0x16}, /* USB3PHY_QSERDES_COM_PLL_RCTRL_MODE0 */
+	{0x070, 0x36}, /* USB3PHY_QSERDES_COM_PLL_CCTRL_MODE0 */
+	{0x0DC, 0x00}, /* USB3PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 */
+	{0x0D8, 0x3F}, /* USB3PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 */
+	{0x0F8, 0x01}, /* USB3PHY_QSERDES_COM_VCO_TUNE2_MODE0 */
+	{0x0F4, 0xC9}, /* USB3PHY_QSERDES_COM_VCO_TUNE1_MODE0 */
+	{0x148, 0x0A}, /* USB3PHY_QSERDES_COM_CORECLK_DIV_MODE0 */
+	{0x0A0, 0x00}, /* USB3PHY_QSERDES_COM_LOCK_CMP3_MODE0 */
+	{0x09C, 0x34}, /* USB3PHY_QSERDES_COM_LOCK_CMP2_MODE0 */
+	{0x098, 0x15}, /* USB3PHY_QSERDES_COM_LOCK_CMP1_MODE0 */
+	{0x154, 0x00}, /* USB3PHY_QSERDES_COM_CORE_CLK_EN */
+	{0x094, 0x00}, /* USB3PHY_QSERDES_COM_LOCK_CMP_CFG */
+	{0x0F0, 0x00}, /* USB3PHY_QSERDES_COM_VCO_TUNE_MAP */
+	{0x00C, 0x0A}, /* USB3PHY_QSERDES_COM_BG_TIMER */
+	{0x010, 0x01}, /* USB3PHY_QSERDES_COM_SSC_EN_CENTER */
+	{0x01C, 0x31}, /* USB3PHY_QSERDES_COM_SSC_PER1 */
+	{0x020, 0x01}, /* USB3PHY_QSERDES_COM_SSC_PER2 */
+	{0x014, 0x00}, /* USB3PHY_QSERDES_COM_SSC_ADJ_PER1 */
+	{0x018, 0x00}, /* USB3PHY_QSERDES_COM_SSC_ADJ_PER2 */
+	{0x024, 0x85}, /* USB3PHY_QSERDES_COM_SSC_STEP_SIZE1 */
+	{0x028, 0x07}, /* USB3PHY_QSERDES_COM_SSC_STEP_SIZE2 */
+
+	/* Rx Settings */
+	{0x4C0, 0x0C}, /* USB3PHY_QSERDES_RX_VGA_CAL_CNTRL2 */
+	{0x564, 0x59}, /* USB3PHY_QSERDES_RX_RX_MODE_00 */
+	{0x430, 0x0B}, /* USB3PHY_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN */
+	{0x4D4, 0x0E}, /* USB3PHY_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 */
+	{0x4D8, 0x4E}, /* USB3PHY_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 */
+	{0x4DC, 0x18}, /* USB3PHY_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 */
+	{0x4F8, 0x77}, /* USB3PHY_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */
+	{0x4FC, 0x80}, /* USB3PHY_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 */
+	{0x504, 0x03}, /* USB3PHY_QSERDES_RX_SIGDET_CNTRL */
+	{0x50C, 0x1A}, /* USB3PHY_QSERDES_RX_SIGDET_DEGLITCH_CNTRL */
+	{0x50C, 0x1A}, /* USB3PHY_QSERDES_RX_SIGDET_DEGLITCH_CNTRL */
+	{0x260, 0x10}, /* USB3PHY_QSERDES_TX_HIGHZ_DRVR_EN */
+	{0x2A4, 0x12}, /* USB3PHY_QSERDES_TX_RCV_DETECT_LVL_2 */
+	{0x28C, 0xC6}, /* USB3PHY_QSERDES_TX_LANE_MODE_1 */
+	{0x8C8, 0x83}, /* USB3PHY_PCIE_USB3_UNI_PCS_FLL_CNTRL2 */
+	{0x8CC, 0x09}, /* USB3PHY_PCIE_USB3_UNI_PCS_FLL_CNT_VAL_L */
+	{0x8D0, 0xA2}, /* USB3PHY_PCIE_USB3_UNI_PCS_FLL_CNT_VAL_H_TOL */
+	{0x8D0, 0xA2}, /* USB3PHY_PCIE_USB3_UNI_PCS_FLL_CNT_VAL_H_TOL */
+	{0x8D4, 0x40}, /* USB3PHY_PCIE_USB3_UNI_PCS_FLL_MAN_CODE */
+	{0x8C4, 0x02}, /* USB3PHY_PCIE_USB3_UNI_PCS_FLL_CNTRL1 */
+	{0x880, 0xD1}, /* USB3PHY_PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG1 */
+	{0x884, 0x1F}, /* USB3PHY_PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG2 */
+	{0x888, 0x47}, /* USB3PHY_PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG3 */
+	{0x864, 0x1B}, /* USB3PHY_PCIE_USB3_UNI_PCS_POWER_STATE_CONFIG2 */
+	{0x0D0, 0x80}, /* USB3PHY_QSERDES_COM_INTEGLOOP_INITVAL */
+	{0x434, 0x75}, /* USB3PHY_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE */
+	{0x43C, 0x00}, /* USB3PHY_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW */
+	{0x440, 0x00}, /* USB3PHY_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH */
+	{0x444, 0x80}, /* USB3PHY_QSERDES_RX_UCDR_PI_CONTROLS */
+	{0x408, 0x0A}, /* USB3PHY_QSERDES_RX_UCDR_FO_GAIN */
+	{0x414, 0x06}, /* USB3PHY_QSERDES_RX_UCDR_SO_GAIN */
+	{0x500, 0x00}, /* USB3PHY_QSERDES_RX_SIGDET_ENABLES */
+	{0x244, 0x0D}, /* USB3PHY_QSERDES_TX_RES_CODE_LANE_OFFSET_TX */
+	{0x248, 0x09}, /* USB3PHY_QSERDES_TX_RES_CODE_LANE_OFFSET_RX */
+	{0x80C, 0x9F}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXMGN_V0 */
+	{0x810, 0x9F}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXMGN_V1 */
+	{0x814, 0xB5}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXMGN_V2 */
+	{0x818, 0x4C}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXMGN_V3 */
+	{0x81C, 0x64}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXMGN_V4 */
+	{0x820, 0x6A}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXMGN_LS */
+	{0x824, 0x15}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M6DB_V0 */
+	{0x828, 0x0D}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M3P5DB_V0 */
+	{0x82C, 0x15}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M6DB_V1 */
+	{0x830, 0x0D}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M3P5DB_V1 */
+	{0x834, 0x15}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M6DB_V2 */
+	{0x838, 0x0D}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M3P5DB_V2 */
+	{0x83C, 0x15}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M6DB_V3 */
+	{0x840, 0x0D}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M3P5DB_V3 */
+	{0x844, 0x15}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M6DB_V4 */
+	{0x848, 0x0D}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M3P5DB_V4 */
+	{0x84C, 0x15}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M6DB_LS */
+	{0x850, 0x0D}, /* USB3PHY_PCIE_USB3_UNI_PCS_TXDEEMPH_M3P5DB_LS */
+	{0x85C, 0x02}, /* USB3PHY_PCIE_USB3_UNI_PCS_RATE_SLEW_CNTRL */
+	{0x8B8, 0x75}, /* USB3PHY_PCIE_USB3_UNI_PCS_RXEQTRAINING_WAIT_TIME */
+	{0x8BC, 0x7A}, /* USB3PHY_PCIE_USB3_UNI_PCS_RXEQTRAINING_RUN_TIME */
+	{0x8B0, 0x86}, /* USB3PHY_PCIE_USB3_UNI_PCS_LFPS_TX_ECSTART_EQTLOCK */
+	{0x8A0, 0x04}, /* USB3PHY_PCIE_USB3_UNI_PCS_PWRUP_RESET_DLY_TIME_AUXCLK */
+	{0x88C, 0x44}, /* USB3PHY_PCIE_USB3_UNI_PCS_TSYNC_RSYNC_TIME */
+	{0x880, 0xD1}, /* USB3PHY_PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG1 */
+	{0x884, 0x1F}, /* USB3PHY_PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG2 */
+	{0x888, 0x47}, /* USB3PHY_PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG3 */
+	{0x870, 0xF1}, /* USB3PHY_PCIE_USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L */
+	{0x874, 0x01}, /* USB3PHY_PCIE_USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H */
+	{0x878, 0x40}, /* USB3PHY_PCIE_USB3_UNI_PCS_RCVR_DTCT_DLY_U3_L */
+	{0x87C, 0x00}, /* USB3PHY_PCIE_USB3_UNI_PCS_RCVR_DTCT_DLY_U3_H */
+//	{0x9DB, 0xBA}, /* USB3PHY_PCIE_USB3_UNI_PCS_RX_SIGDET_LVL */
+	{0x8B8, 0x75}, /* USB3PHY_PCIE_USB3_UNI_PCS_RXEQTRAINING_WAIT_TIME */
+	{0x8B0, 0x86}, /* USB3PHY_PCIE_USB3_UNI_PCS_LFPS_TX_ECSTART_EQTLOCK */
+	{0x8BC, 0x13}, /* USB3PHY_PCIE_USB3_UNI_PCS_RXEQTRAINING_RUN_TIME */
+	{0xA0C, 0x21}, /* USB3PHY_PCIE_USB3_UNI_PCS_REFGEN_REQ_CONFIG1 */
+	{0xA10, 0x60}, /* USB3PHY_PCIE_USB3_UNI_PCS_REFGEN_REQ_CONFIG2 */
+	{0x800, 0x00}, /* USB3PHY_PCIE_USB3_UNI_PCS_SW_RESET */
+	{0x808, 0x03}, /* USB3PHY_PCIE_USB3_UNI_PCS_START_CONTROL */
+};
+
 struct qmp_reg *target_get_qmp_settings()
 {
-	if (platform_is_mdm9650() || platform_is_sdx20())
+	if (platform_is_mdm9650())
 		return qmp_settings;
+	else if(platform_is_sdx20())
+		return qmp_settings_sdx20;
 	else
 		return NULL;
 }
 
 int target_get_qmp_regsize()
 {
-	if (platform_is_mdm9650() || platform_is_sdx20())
+	if (platform_is_mdm9650())
 		return ARRAY_SIZE(qmp_settings);
+	else if(platform_is_sdx20())
+		return ARRAY_SIZE(qmp_settings_sdx20);
 	else
 		return 0;
 }
diff --git a/target/msm8909/rules.mk b/target/msm8909/rules.mk
index 55aa9d0..5dbd21a 100644
--- a/target/msm8909/rules.mk
+++ b/target/msm8909/rules.mk
@@ -6,7 +6,7 @@
 PLATFORM := msm8909
 
 MEMBASE := 0x8F600000 # SDRAM
-MEMSIZE := 0x00100000 # 1MB
+MEMSIZE := 0x00400000 # 4MB
 
 BASE_ADDR        := 0x80000000
 SCRATCH_ADDR     := 0x90100000