| commit | a7fb106652a75c307e30fd2a145564e4377ff5b1 | [log] [tgz] |
|---|---|---|
| author | V S Ramanjaneya Kumar T <vsrama@codeaurora.org> | Fri Jan 04 22:36:29 2013 +0530 |
| committer | Amol Jadi <amoljadi@codeaurora.org> | Mon Jan 28 14:26:25 2013 -0800 |
| tree | 35bdc3f61f8c98eaf835bf38f427ca81dfd689c6 | |
| parent | 7bb7850d1bd031cf173d679d6a19baeb8a99a479 [diff] |
arch: arm: Fix bug in cache flush code Before invalidating the cache, make sure that all memory access is ordered. Otherwise, in some cases we got inconsistant results when the stack was poped after the disabling cache. Change-Id: I27083b18acc133937a4a095bb5ea42598123996e