commit | ab2de89a6ce6d819bd53424f45fbd396dd7becb1 | [log] [tgz] |
---|---|---|
author | Dhaval Patel <pdhaval@codeaurora.org> | Fri Oct 25 10:40:58 2013 -0700 |
committer | Dhaval Patel <pdhaval@codeaurora.org> | Wed Oct 30 15:48:44 2013 -0700 |
tree | b0003732fb415e8c08b28fc555df49cc7fdd5dcc | |
parent | b22f1bc803e60837db1caf55f41f9f3e2fbe6a29 [diff] |
target: apq8084: Configure VBIF & CLK_CTL for APQ8084 Configure VBIF & CLK_CTL registers for APQ8084 with target specific values before timing generator enable. This configuration matches with VBIF & CLK_CTL setting in kernel. Change-Id: I014be2b805f39da0edeec8ec6f8d772211b94c57