target: msm8226: update dsi pll enable sequence
Update dsi pll enable sequence for msm8226 platform,
so that it matches with the pll enable sequence of
display driver.
Change-Id: Ib76028d5596762457fa9ad2edf05ddb824f6b989
diff --git a/platform/msm_shared/mipi_dsi_autopll.c b/platform/msm_shared/mipi_dsi_autopll.c
index d21e8d7..0dfcdc1 100755
--- a/platform/msm_shared/mipi_dsi_autopll.c
+++ b/platform/msm_shared/mipi_dsi_autopll.c
@@ -105,7 +105,7 @@
writel(0x2b, ctl_base + 0x0278); /* Cal CFG3 */
writel(0x66, ctl_base + 0x027c); /* Cal CFG4 */
- writel(0x05, ctl_base + 0x0264); /* LKDetect CFG2 */
+ writel(0x0d, ctl_base + 0x0264); /* LKDetect CFG2 */
rem = pd->vco_clock % VCO_REF_CLOCK_RATE;
if (rem) {
@@ -149,11 +149,6 @@
cal_cfg11 = gen_vco_clk / 256000000;
cal_cfg10 = (gen_vco_clk % 256000000) / 1000000;
- writel(0x02, ctl_base + 0x0208); /* PUMP CFG */
- writel(0x2b, ctl_base + 0x0278); /* CAL CFG3 */
- writel(0x66, ctl_base + 0x027c); /* CAL CFG4 */
- writel(0x0d, ctl_base + 0x0264); /* LKDetect CFG2 */
-
writel(sdm_cfg1 & 0xff , ctl_base + 0x023c); /* SDM CFG1 */
writel(sdm_cfg2 & 0xff , ctl_base + 0x0240); /* SDM CFG2 */
writel(sdm_cfg3 & 0xff, ctl_base + 0x0244); /* SDM CFG3 */